2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
87 static int xhcidebug = 0;
89 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
90 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW,
91 &xhcidebug, 0, "Debug level");
93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
97 #define XHCI_INTR_ENDPT 1
99 struct xhci_std_temp {
100 struct xhci_softc *sc;
101 struct usb_page_cache *pc;
103 struct xhci_td *td_next;
106 uint32_t max_packet_size;
120 static void xhci_do_poll(struct usb_bus *);
121 static void xhci_device_done(struct usb_xfer *, usb_error_t);
122 static void xhci_root_intr(struct xhci_softc *);
123 static void xhci_free_device_ext(struct usb_device *);
124 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
125 struct usb_endpoint_descriptor *);
126 static usb_proc_callback_t xhci_configure_msg;
127 static usb_error_t xhci_configure_device(struct usb_device *);
128 static usb_error_t xhci_configure_endpoint(struct usb_device *,
129 struct usb_endpoint_descriptor *, uint64_t, uint16_t,
130 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
131 static usb_error_t xhci_configure_mask(struct usb_device *,
133 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
135 static void xhci_endpoint_doorbell(struct usb_xfer *);
136 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
137 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
138 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
140 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
143 extern struct usb_bus_methods xhci_bus_methods;
147 xhci_dump_trb(struct xhci_trb *trb)
149 DPRINTFN(5, "trb = %p\n", trb);
150 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
151 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
152 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
156 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
158 DPRINTFN(5, "pep = %p\n", pep);
159 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
160 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
161 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
162 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
163 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
164 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
165 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
169 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
171 DPRINTFN(5, "psl = %p\n", psl);
172 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
173 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
174 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
175 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
180 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
182 struct xhci_softc *sc = XHCI_BUS2SC(bus);
185 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
186 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
188 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
189 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
191 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
192 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
193 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
198 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
200 if (sc->sc_ctx_is_64_byte) {
202 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
203 /* all contexts are initially 32-bytes */
204 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
205 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
211 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
213 if (sc->sc_ctx_is_64_byte) {
215 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
216 /* all contexts are initially 32-bytes */
217 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
218 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
220 return (le32toh(*ptr));
224 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
226 if (sc->sc_ctx_is_64_byte) {
228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
229 /* all contexts are initially 32-bytes */
230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
231 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
238 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
240 if (sc->sc_ctx_is_64_byte) {
242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
243 /* all contexts are initially 32-bytes */
244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
245 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
247 return (le64toh(*ptr));
252 xhci_start_controller(struct xhci_softc *sc)
254 struct usb_page_search buf_res;
255 struct xhci_hw_root *phwr;
256 struct xhci_dev_ctx_addr *pdctxa;
264 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
265 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
266 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
268 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
269 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
270 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
272 sc->sc_event_ccs = 1;
273 sc->sc_event_idx = 0;
274 sc->sc_command_ccs = 1;
275 sc->sc_command_idx = 0;
277 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
279 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
281 DPRINTF("HCS0 = 0x%08x\n", temp);
283 if (XHCI_HCS0_CSZ(temp)) {
284 sc->sc_ctx_is_64_byte = 1;
285 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
287 sc->sc_ctx_is_64_byte = 0;
288 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
291 /* Reset controller */
292 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
294 for (i = 0; i != 100; i++) {
295 usb_pause_mtx(NULL, hz / 100);
296 temp = XREAD4(sc, oper, XHCI_USBCMD) &
297 (XHCI_CMD_HCRST | XHCI_STS_CNR);
303 device_printf(sc->sc_bus.parent, "Controller "
305 return (USB_ERR_IOERROR);
308 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
309 device_printf(sc->sc_bus.parent, "Controller does "
310 "not support 4K page size.\n");
311 return (USB_ERR_IOERROR);
314 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
316 i = XHCI_HCS1_N_PORTS(temp);
319 device_printf(sc->sc_bus.parent, "Invalid number "
320 "of ports: %u\n", i);
321 return (USB_ERR_IOERROR);
325 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
327 if (sc->sc_noslot > XHCI_MAX_DEVICES)
328 sc->sc_noslot = XHCI_MAX_DEVICES;
330 /* setup number of device slots */
332 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
333 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
335 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
337 DPRINTF("Max slots: %u\n", sc->sc_noslot);
339 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
341 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
343 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
344 device_printf(sc->sc_bus.parent, "XHCI request "
345 "too many scratchpads\n");
346 return (USB_ERR_NOMEM);
349 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
351 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
353 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
354 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
356 temp = XREAD4(sc, oper, XHCI_USBSTS);
358 /* clear interrupts */
359 XWRITE4(sc, oper, XHCI_USBSTS, temp);
360 /* disable all device notifications */
361 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
363 /* setup device context base address */
364 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
365 pdctxa = buf_res.buffer;
366 memset(pdctxa, 0, sizeof(*pdctxa));
368 addr = buf_res.physaddr;
369 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
371 /* slot 0 points to the table of scratchpad pointers */
372 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
374 for (i = 0; i != sc->sc_noscratch; i++) {
375 struct usb_page_search buf_scp;
376 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
377 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
380 addr = buf_res.physaddr;
382 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
383 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
384 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
385 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
387 /* Setup event table size */
389 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
391 DPRINTF("HCS2=0x%08x\n", temp);
393 temp = XHCI_HCS2_ERST_MAX(temp);
395 if (temp > XHCI_MAX_RSEG)
396 temp = XHCI_MAX_RSEG;
398 sc->sc_erst_max = temp;
400 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
401 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
403 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
405 /* Setup interrupt rate */
406 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
408 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
410 phwr = buf_res.buffer;
411 addr = buf_res.physaddr;
412 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
414 /* reset hardware root structure */
415 memset(phwr, 0, sizeof(*phwr));
417 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
418 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
420 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
422 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
423 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
425 addr = (uint64_t)buf_res.physaddr;
427 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
429 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
430 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
432 /* Setup interrupter registers */
434 temp = XREAD4(sc, runt, XHCI_IMAN(0));
435 temp |= XHCI_IMAN_INTR_ENA;
436 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
438 /* setup command ring control base address */
439 addr = buf_res.physaddr;
440 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
442 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
444 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
445 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
447 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
449 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
452 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
453 XHCI_CMD_INTE | XHCI_CMD_HSEE);
455 for (i = 0; i != 100; i++) {
456 usb_pause_mtx(NULL, hz / 100);
457 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
462 XWRITE4(sc, oper, XHCI_USBCMD, 0);
463 device_printf(sc->sc_bus.parent, "Run timeout.\n");
464 return (USB_ERR_IOERROR);
467 /* catch any lost interrupts */
468 xhci_do_poll(&sc->sc_bus);
474 xhci_halt_controller(struct xhci_softc *sc)
482 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
483 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
484 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
486 /* Halt controller */
487 XWRITE4(sc, oper, XHCI_USBCMD, 0);
489 for (i = 0; i != 100; i++) {
490 usb_pause_mtx(NULL, hz / 100);
491 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
497 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
498 return (USB_ERR_IOERROR);
504 xhci_init(struct xhci_softc *sc, device_t self)
506 /* initialise some bus fields */
507 sc->sc_bus.parent = self;
509 /* set the bus revision */
510 sc->sc_bus.usbrev = USB_REV_3_0;
512 /* set up the bus struct */
513 sc->sc_bus.methods = &xhci_bus_methods;
515 /* setup devices array */
516 sc->sc_bus.devices = sc->sc_devices;
517 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
519 /* setup command queue mutex and condition varible */
520 cv_init(&sc->sc_cmd_cv, "CMDQ");
521 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
523 /* get all DMA memory */
524 if (usb_bus_mem_alloc_all(&sc->sc_bus,
525 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
529 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
530 sc->sc_config_msg[0].bus = &sc->sc_bus;
531 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
532 sc->sc_config_msg[1].bus = &sc->sc_bus;
534 if (usb_proc_create(&sc->sc_config_proc,
535 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
536 printf("WARNING: Creation of XHCI configure "
537 "callback process failed.\n");
543 xhci_uninit(struct xhci_softc *sc)
545 usb_proc_free(&sc->sc_config_proc);
547 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
549 cv_destroy(&sc->sc_cmd_cv);
550 sx_destroy(&sc->sc_cmd_sx);
554 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
556 struct xhci_softc *sc = XHCI_BUS2SC(bus);
559 case USB_HW_POWER_SUSPEND:
560 DPRINTF("Stopping the XHCI\n");
561 xhci_halt_controller(sc);
563 case USB_HW_POWER_SHUTDOWN:
564 DPRINTF("Stopping the XHCI\n");
565 xhci_halt_controller(sc);
567 case USB_HW_POWER_RESUME:
568 DPRINTF("Starting the XHCI\n");
569 xhci_start_controller(sc);
577 xhci_generic_done_sub(struct usb_xfer *xfer)
580 struct xhci_td *td_alt_next;
584 td = xfer->td_transfer_cache;
585 td_alt_next = td->alt_next;
587 if (xfer->aframes != xfer->nframes)
588 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
592 usb_pc_cpu_invalidate(td->page_cache);
597 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
598 xfer, (unsigned int)xfer->aframes,
599 (unsigned int)xfer->nframes,
600 (unsigned int)len, (unsigned int)td->len,
601 (unsigned int)status);
604 * Verify the status length and
605 * add the length to "frlengths[]":
608 /* should not happen */
609 DPRINTF("Invalid status length, "
610 "0x%04x/0x%04x bytes\n", len, td->len);
611 status = XHCI_TRB_ERROR_LENGTH;
612 } else if (xfer->aframes != xfer->nframes) {
613 xfer->frlengths[xfer->aframes] += td->len - len;
615 /* Check for last transfer */
616 if (((void *)td) == xfer->td_transfer_last) {
620 /* Check for transfer error */
621 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
622 status != XHCI_TRB_ERROR_SUCCESS) {
623 /* the transfer is finished */
627 /* Check for short transfer */
629 if (xfer->flags_int.short_frames_ok ||
630 xfer->flags_int.isochronous_xfr ||
631 xfer->flags_int.control_xfr) {
632 /* follow alt next */
635 /* the transfer is finished */
642 if (td->alt_next != td_alt_next) {
643 /* this USB frame is complete */
648 /* update transfer cache */
650 xfer->td_transfer_cache = td;
652 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
653 (status != XHCI_TRB_ERROR_SHORT_PKT &&
654 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
655 USB_ERR_NORMAL_COMPLETION);
659 xhci_generic_done(struct usb_xfer *xfer)
663 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
664 xfer, xfer->endpoint);
668 xfer->td_transfer_cache = xfer->td_transfer_first;
670 if (xfer->flags_int.control_xfr) {
672 if (xfer->flags_int.control_hdr)
673 err = xhci_generic_done_sub(xfer);
677 if (xfer->td_transfer_cache == NULL)
681 while (xfer->aframes != xfer->nframes) {
683 err = xhci_generic_done_sub(xfer);
686 if (xfer->td_transfer_cache == NULL)
690 if (xfer->flags_int.control_xfr &&
691 !xfer->flags_int.control_act)
692 err = xhci_generic_done_sub(xfer);
694 /* transfer is complete */
695 xhci_device_done(xfer, err);
699 xhci_activate_transfer(struct usb_xfer *xfer)
703 td = xfer->td_transfer_cache;
705 usb_pc_cpu_invalidate(td->page_cache);
707 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
709 /* activate the transfer */
711 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
712 usb_pc_cpu_flush(td->page_cache);
714 xhci_endpoint_doorbell(xfer);
719 xhci_skip_transfer(struct usb_xfer *xfer)
722 struct xhci_td *td_last;
724 td = xfer->td_transfer_cache;
725 td_last = xfer->td_transfer_last;
729 usb_pc_cpu_invalidate(td->page_cache);
731 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
733 usb_pc_cpu_invalidate(td_last->page_cache);
735 /* copy LINK TRB to current waiting location */
737 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
738 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
739 usb_pc_cpu_flush(td->page_cache);
741 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
742 usb_pc_cpu_flush(td->page_cache);
744 xhci_endpoint_doorbell(xfer);
748 /*------------------------------------------------------------------------*
749 * xhci_check_transfer
750 *------------------------------------------------------------------------*/
752 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
765 td_event = le64toh(trb->qwTrb0);
766 temp = le32toh(trb->dwTrb2);
768 remainder = XHCI_TRB_2_REM_GET(temp);
769 status = XHCI_TRB_2_ERROR_GET(temp);
771 temp = le32toh(trb->dwTrb3);
772 epno = XHCI_TRB_3_EP_GET(temp);
773 index = XHCI_TRB_3_SLOT_GET(temp);
775 /* check if error means halted */
776 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
777 status != XHCI_TRB_ERROR_SUCCESS);
779 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
780 index, epno, remainder, status);
782 if (index > sc->sc_noslot) {
783 DPRINTF("Invalid slot.\n");
787 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
788 DPRINTF("Invalid endpoint.\n");
792 /* try to find the USB transfer that generated the event */
793 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
794 struct usb_xfer *xfer;
796 struct xhci_endpoint_ext *pepext;
798 pepext = &sc->sc_hw.devs[index].endp[epno];
800 xfer = pepext->xfer[i];
804 td = xfer->td_transfer_cache;
806 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
808 (long long)td->td_self,
809 (long long)td->td_self + sizeof(td->td_trb));
812 * NOTE: Some XHCI implementations might not trigger
813 * an event on the last LINK TRB so we need to
814 * consider both the last and second last event
815 * address as conditions for a successful transfer.
817 * NOTE: We assume that the XHCI will only trigger one
818 * event per chain of TRBs.
821 offset = td_event - td->td_self;
824 offset < (int64_t)sizeof(td->td_trb)) {
826 usb_pc_cpu_invalidate(td->page_cache);
828 /* compute rest of remainder, if any */
829 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
830 temp = le32toh(td->td_trb[i].dwTrb2);
831 remainder += XHCI_TRB_2_BYTES_GET(temp);
834 DPRINTFN(5, "New remainder: %u\n", remainder);
836 /* clear isochronous transfer errors */
837 if (xfer->flags_int.isochronous_xfr) {
840 status = XHCI_TRB_ERROR_SUCCESS;
845 /* "td->remainder" is verified later */
846 td->remainder = remainder;
849 usb_pc_cpu_flush(td->page_cache);
852 * 1) Last transfer descriptor makes the
855 if (((void *)td) == xfer->td_transfer_last) {
856 DPRINTF("TD is last\n");
857 xhci_generic_done(xfer);
862 * 2) Any kind of error makes the transfer
866 DPRINTF("TD has I/O error\n");
867 xhci_generic_done(xfer);
872 * 3) If there is no alternate next transfer,
873 * a short packet also makes the transfer done
875 if (td->remainder > 0) {
876 DPRINTF("TD has short pkt\n");
877 if (xfer->flags_int.short_frames_ok ||
878 xfer->flags_int.isochronous_xfr ||
879 xfer->flags_int.control_xfr) {
880 /* follow the alt next */
881 xfer->td_transfer_cache = td->alt_next;
882 xhci_activate_transfer(xfer);
885 xhci_skip_transfer(xfer);
886 xhci_generic_done(xfer);
891 * 4) Transfer complete - go to next TD
893 DPRINTF("Following next TD\n");
894 xfer->td_transfer_cache = td->obj_next;
895 xhci_activate_transfer(xfer);
896 break; /* there should only be one match */
902 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
904 if (sc->sc_cmd_addr == trb->qwTrb0) {
905 DPRINTF("Received command event\n");
906 sc->sc_cmd_result[0] = trb->dwTrb2;
907 sc->sc_cmd_result[1] = trb->dwTrb3;
908 cv_signal(&sc->sc_cmd_cv);
913 xhci_interrupt_poll(struct xhci_softc *sc)
915 struct usb_page_search buf_res;
916 struct xhci_hw_root *phwr;
925 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
927 phwr = buf_res.buffer;
929 /* Receive any events */
931 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
933 i = sc->sc_event_idx;
934 j = sc->sc_event_ccs;
939 temp = le32toh(phwr->hwr_events[i].dwTrb3);
941 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
946 event = XHCI_TRB_3_TYPE_GET(temp);
948 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
949 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
950 (long)le32toh(phwr->hwr_events[i].dwTrb2),
951 (long)le32toh(phwr->hwr_events[i].dwTrb3));
954 case XHCI_TRB_EVENT_TRANSFER:
955 xhci_check_transfer(sc, &phwr->hwr_events[i]);
957 case XHCI_TRB_EVENT_CMD_COMPLETE:
958 xhci_check_command(sc, &phwr->hwr_events[i]);
961 DPRINTF("Unhandled event = %u\n", event);
967 if (i == XHCI_MAX_EVENTS) {
971 /* check for timeout */
977 sc->sc_event_idx = i;
978 sc->sc_event_ccs = j;
981 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
982 * latched. That means to activate the register we need to
983 * write both the low and high double word of the 64-bit
987 addr = (uint32_t)buf_res.physaddr;
988 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
990 /* try to clear busy bit */
991 addr |= XHCI_ERDP_LO_BUSY;
993 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
994 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
998 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1001 struct usb_page_search buf_res;
1002 struct xhci_hw_root *phwr;
1009 XHCI_CMD_ASSERT_LOCKED(sc);
1011 /* get hardware root structure */
1013 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1015 phwr = buf_res.buffer;
1019 USB_BUS_LOCK(&sc->sc_bus);
1021 i = sc->sc_command_idx;
1022 j = sc->sc_command_ccs;
1024 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1025 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1026 (long long)le64toh(trb->qwTrb0),
1027 (long)le32toh(trb->dwTrb2),
1028 (long)le32toh(trb->dwTrb3));
1030 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1031 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1033 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1038 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1040 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1042 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1044 phwr->hwr_commands[i].dwTrb3 = temp;
1046 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1048 addr = buf_res.physaddr;
1049 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1051 sc->sc_cmd_addr = htole64(addr);
1055 if (i == (XHCI_MAX_COMMANDS - 1)) {
1058 temp = htole32(XHCI_TRB_3_TC_BIT |
1059 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1060 XHCI_TRB_3_CYCLE_BIT);
1062 temp = htole32(XHCI_TRB_3_TC_BIT |
1063 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1066 phwr->hwr_commands[i].dwTrb3 = temp;
1068 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1074 sc->sc_command_idx = i;
1075 sc->sc_command_ccs = j;
1077 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1079 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1080 USB_MS_TO_TICKS(timeout_ms));
1083 DPRINTFN(0, "Command timeout!\n");
1084 err = USB_ERR_TIMEOUT;
1088 temp = le32toh(sc->sc_cmd_result[0]);
1089 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1090 err = USB_ERR_IOERROR;
1092 trb->dwTrb2 = sc->sc_cmd_result[0];
1093 trb->dwTrb3 = sc->sc_cmd_result[1];
1096 USB_BUS_UNLOCK(&sc->sc_bus);
1103 xhci_cmd_nop(struct xhci_softc *sc)
1105 struct xhci_trb trb;
1112 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1114 trb.dwTrb3 = htole32(temp);
1116 return (xhci_do_command(sc, &trb, 100 /* ms */));
1121 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1123 struct xhci_trb trb;
1131 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1133 err = xhci_do_command(sc, &trb, 100 /* ms */);
1137 temp = le32toh(trb.dwTrb3);
1139 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1146 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1148 struct xhci_trb trb;
1155 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1156 XHCI_TRB_3_SLOT_SET(slot_id);
1158 trb.dwTrb3 = htole32(temp);
1160 return (xhci_do_command(sc, &trb, 100 /* ms */));
1164 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1165 uint8_t bsr, uint8_t slot_id)
1167 struct xhci_trb trb;
1172 trb.qwTrb0 = htole64(input_ctx);
1174 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1175 XHCI_TRB_3_SLOT_SET(slot_id);
1178 temp |= XHCI_TRB_3_BSR_BIT;
1180 trb.dwTrb3 = htole32(temp);
1182 return (xhci_do_command(sc, &trb, 500 /* ms */));
1186 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1188 struct usb_page_search buf_inp;
1189 struct usb_page_search buf_dev;
1190 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1191 struct xhci_hw_dev *hdev;
1192 struct xhci_dev_ctx *pdev;
1193 struct xhci_endpoint_ext *pepext;
1199 /* the root HUB case is not handled here */
1200 if (udev->parent_hub == NULL)
1201 return (USB_ERR_INVAL);
1203 index = udev->controller_slot_id;
1205 hdev = &sc->sc_hw.devs[index];
1212 switch (hdev->state) {
1213 case XHCI_ST_DEFAULT:
1214 case XHCI_ST_ENABLED:
1216 hdev->state = XHCI_ST_ENABLED;
1218 /* set configure mask to slot and EP0 */
1219 xhci_configure_mask(udev, 3, 0);
1221 /* configure input slot context structure */
1222 err = xhci_configure_device(udev);
1225 DPRINTF("Could not configure device\n");
1229 /* configure input endpoint context structure */
1230 switch (udev->speed) {
1232 case USB_SPEED_FULL:
1235 case USB_SPEED_HIGH:
1243 pepext = xhci_get_endpoint_ext(udev,
1244 &udev->ctrl_ep_desc);
1245 err = xhci_configure_endpoint(udev,
1246 &udev->ctrl_ep_desc, pepext->physaddr,
1247 0, 1, 1, 0, mps, mps);
1250 DPRINTF("Could not configure default endpoint\n");
1254 /* execute set address command */
1255 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1257 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1258 (address == 0), index);
1261 DPRINTF("Could not set address "
1262 "for slot %u.\n", index);
1267 /* update device address to new value */
1269 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1270 pdev = buf_dev.buffer;
1271 usb_pc_cpu_invalidate(&hdev->device_pc);
1273 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1274 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1276 /* update device state to new value */
1279 hdev->state = XHCI_ST_ADDRESSED;
1281 hdev->state = XHCI_ST_DEFAULT;
1285 DPRINTF("Wrong state for set address.\n");
1286 err = USB_ERR_IOERROR;
1289 XHCI_CMD_UNLOCK(sc);
1298 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1299 uint8_t deconfigure, uint8_t slot_id)
1301 struct xhci_trb trb;
1306 trb.qwTrb0 = htole64(input_ctx);
1308 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1309 XHCI_TRB_3_SLOT_SET(slot_id);
1312 temp |= XHCI_TRB_3_DCEP_BIT;
1314 trb.dwTrb3 = htole32(temp);
1316 return (xhci_do_command(sc, &trb, 100 /* ms */));
1320 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1323 struct xhci_trb trb;
1328 trb.qwTrb0 = htole64(input_ctx);
1330 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1331 XHCI_TRB_3_SLOT_SET(slot_id);
1332 trb.dwTrb3 = htole32(temp);
1334 return (xhci_do_command(sc, &trb, 100 /* ms */));
1338 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1339 uint8_t ep_id, uint8_t slot_id)
1341 struct xhci_trb trb;
1348 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1349 XHCI_TRB_3_SLOT_SET(slot_id) |
1350 XHCI_TRB_3_EP_SET(ep_id);
1353 temp |= XHCI_TRB_3_PRSV_BIT;
1355 trb.dwTrb3 = htole32(temp);
1357 return (xhci_do_command(sc, &trb, 100 /* ms */));
1361 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1362 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1364 struct xhci_trb trb;
1369 trb.qwTrb0 = htole64(dequeue_ptr);
1371 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1372 trb.dwTrb2 = htole32(temp);
1374 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1375 XHCI_TRB_3_SLOT_SET(slot_id) |
1376 XHCI_TRB_3_EP_SET(ep_id);
1377 trb.dwTrb3 = htole32(temp);
1379 return (xhci_do_command(sc, &trb, 100 /* ms */));
1383 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1384 uint8_t ep_id, uint8_t slot_id)
1386 struct xhci_trb trb;
1393 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1394 XHCI_TRB_3_SLOT_SET(slot_id) |
1395 XHCI_TRB_3_EP_SET(ep_id);
1398 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1400 trb.dwTrb3 = htole32(temp);
1402 return (xhci_do_command(sc, &trb, 100 /* ms */));
1406 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1408 struct xhci_trb trb;
1415 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1416 XHCI_TRB_3_SLOT_SET(slot_id);
1418 trb.dwTrb3 = htole32(temp);
1420 return (xhci_do_command(sc, &trb, 100 /* ms */));
1423 /*------------------------------------------------------------------------*
1424 * xhci_interrupt - XHCI interrupt handler
1425 *------------------------------------------------------------------------*/
1427 xhci_interrupt(struct xhci_softc *sc)
1432 USB_BUS_LOCK(&sc->sc_bus);
1434 status = XREAD4(sc, oper, XHCI_USBSTS);
1436 /* acknowledge interrupts */
1438 XWRITE4(sc, oper, XHCI_USBSTS, status);
1440 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1442 /* acknowledge pending event */
1444 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1446 DPRINTFN(16, "real interrupt (sts=0x%08x, "
1447 "iman=0x%08x)\n", status, temp);
1450 if (status & XHCI_STS_PCD) {
1454 if (status & XHCI_STS_HCH) {
1455 printf("%s: host controller halted\n",
1459 if (status & XHCI_STS_HSE) {
1460 printf("%s: host system error\n",
1464 if (status & XHCI_STS_HCE) {
1465 printf("%s: host controller error\n",
1470 xhci_interrupt_poll(sc);
1472 USB_BUS_UNLOCK(&sc->sc_bus);
1475 /*------------------------------------------------------------------------*
1476 * xhci_timeout - XHCI timeout handler
1477 *------------------------------------------------------------------------*/
1479 xhci_timeout(void *arg)
1481 struct usb_xfer *xfer = arg;
1483 DPRINTF("xfer=%p\n", xfer);
1485 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1487 /* transfer is transferred */
1488 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1492 xhci_do_poll(struct usb_bus *bus)
1494 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1496 USB_BUS_LOCK(&sc->sc_bus);
1497 xhci_interrupt_poll(sc);
1498 USB_BUS_UNLOCK(&sc->sc_bus);
1502 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1504 struct usb_page_search buf_res;
1506 struct xhci_td *td_next;
1507 struct xhci_td *td_alt_next;
1508 uint32_t buf_offset;
1512 uint8_t shortpkt_old;
1518 shortpkt_old = temp->shortpkt;
1519 len_old = temp->len;
1525 td_next = temp->td_next;
1529 if (temp->len == 0) {
1534 /* send a Zero Length Packet, ZLP, last */
1541 average = temp->average;
1543 if (temp->len < average) {
1544 if (temp->len % temp->max_packet_size) {
1547 average = temp->len;
1551 if (td_next == NULL)
1552 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1557 td_next = td->obj_next;
1559 /* check if we are pre-computing */
1563 /* update remaining length */
1565 temp->len -= average;
1569 /* fill out current TD */
1575 /* update remaining length */
1577 temp->len -= average;
1579 /* reset TRB index */
1583 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1584 /* immediate data */
1589 td->td_trb[0].qwTrb0 = 0;
1591 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1592 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1595 dword = XHCI_TRB_2_BYTES_SET(8) |
1596 XHCI_TRB_2_TDSZ_SET(0) |
1597 XHCI_TRB_2_IRQ_SET(0);
1599 td->td_trb[0].dwTrb2 = htole32(dword);
1601 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1602 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1605 if (td->td_trb[0].qwTrb0 &
1606 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1607 if (td->td_trb[0].qwTrb0 & htole64(1))
1608 dword |= XHCI_TRB_3_TRT_IN;
1610 dword |= XHCI_TRB_3_TRT_OUT;
1613 td->td_trb[0].dwTrb3 = htole32(dword);
1615 xhci_dump_trb(&td->td_trb[x]);
1623 /* fill out buffer pointers */
1627 memset(&buf_res, 0, sizeof(buf_res));
1629 usbd_get_page(temp->pc, temp->offset +
1630 buf_offset, &buf_res);
1632 /* get length to end of page */
1633 if (buf_res.length > average)
1634 buf_res.length = average;
1636 /* check for maximum length */
1637 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1638 buf_res.length = XHCI_TD_PAGE_SIZE;
1641 npkt = (average + temp->max_packet_size - 1) /
1642 temp->max_packet_size;
1648 /* fill out TRB's */
1649 td->td_trb[x].qwTrb0 =
1650 htole64((uint64_t)buf_res.physaddr);
1653 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1654 XHCI_TRB_2_TDSZ_SET(npkt) |
1655 XHCI_TRB_2_IRQ_SET(0);
1657 td->td_trb[x].dwTrb2 = htole32(dword);
1659 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1660 XHCI_TRB_3_TYPE_SET(temp->trb_type) |
1661 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) |
1662 XHCI_TRB_3_TBC_SET(temp->tbc) |
1663 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1665 if (temp->direction == UE_DIR_IN) {
1666 dword |= XHCI_TRB_3_DIR_IN;
1669 * NOTE: Only the SETUP stage should
1670 * use the IDT bit. Else transactions
1671 * can be sent using the wrong data
1674 if (temp->trb_type !=
1675 XHCI_TRB_TYPE_SETUP_STAGE &&
1677 XHCI_TRB_TYPE_STATUS_STAGE)
1678 dword |= XHCI_TRB_3_ISP_BIT;
1681 td->td_trb[x].dwTrb3 = htole32(dword);
1683 average -= buf_res.length;
1684 buf_offset += buf_res.length;
1686 xhci_dump_trb(&td->td_trb[x]);
1690 } while (average != 0);
1692 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1694 /* store number of data TRB's */
1698 DPRINTF("NTRB=%u\n", x);
1700 /* fill out link TRB */
1702 if (td_next != NULL) {
1703 /* link the current TD with the next one */
1704 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1705 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1707 /* this field will get updated later */
1708 DPRINTF("NOLINK\n");
1711 dword = XHCI_TRB_2_IRQ_SET(0);
1713 td->td_trb[x].dwTrb2 = htole32(dword);
1715 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1716 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1718 td->td_trb[x].dwTrb3 = htole32(dword);
1720 td->alt_next = td_alt_next;
1722 xhci_dump_trb(&td->td_trb[x]);
1724 usb_pc_cpu_flush(td->page_cache);
1730 /* setup alt next pointer, if any */
1731 if (temp->last_frame) {
1734 /* we use this field internally */
1735 td_alt_next = td_next;
1739 temp->shortpkt = shortpkt_old;
1740 temp->len = len_old;
1744 /* remove cycle bit from first if we are stepping the TRBs */
1746 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1748 /* remove chain bit because this is the last TRB in the chain */
1749 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1750 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1752 usb_pc_cpu_flush(td->page_cache);
1755 temp->td_next = td_next;
1759 xhci_setup_generic_chain(struct usb_xfer *xfer)
1761 struct xhci_std_temp temp;
1770 temp.average = xfer->max_hc_frame_size;
1771 temp.max_packet_size = xfer->max_packet_size;
1772 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1774 temp.last_frame = 0;
1776 temp.multishort = xfer->flags_int.isochronous_xfr ||
1777 xfer->flags_int.control_xfr ||
1778 xfer->flags_int.short_frames_ok;
1780 /* toggle the DMA set we are using */
1781 xfer->flags_int.curr_dma_set ^= 1;
1783 /* get next DMA set */
1784 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1789 xfer->td_transfer_first = td;
1790 xfer->td_transfer_cache = td;
1792 if (xfer->flags_int.isochronous_xfr) {
1795 /* compute multiplier for ISOCHRONOUS transfers */
1796 mult = xfer->endpoint->ecomp ?
1797 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1798 /* check for USB 2.0 multiplier */
1800 mult = (xfer->endpoint->edesc->
1801 wMaxPacketSize[1] >> 3) & 3;
1809 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1811 DPRINTF("MFINDEX=0x%08x\n", x);
1813 switch (usbd_get_speed(xfer->xroot->udev)) {
1814 case USB_SPEED_FULL:
1816 temp.isoc_delta = 8; /* 1ms */
1817 x += temp.isoc_delta - 1;
1818 x &= ~(temp.isoc_delta - 1);
1821 shift = usbd_xfer_get_fps_shift(xfer);
1822 temp.isoc_delta = 1U << shift;
1823 x += temp.isoc_delta - 1;
1824 x &= ~(temp.isoc_delta - 1);
1825 /* simple frame load balancing */
1826 x += xfer->endpoint->usb_uframe;
1830 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1832 if ((xfer->endpoint->is_synced == 0) ||
1833 (y < (xfer->nframes << shift)) ||
1834 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1836 * If there is data underflow or the pipe
1837 * queue is empty we schedule the transfer a
1838 * few frames ahead of the current frame
1839 * position. Else two isochronous transfers
1842 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1843 xfer->endpoint->is_synced = 1;
1844 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1847 /* compute isochronous completion time */
1849 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
1851 xfer->isoc_time_complete =
1852 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
1853 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
1856 temp.isoc_frame = xfer->endpoint->isoc_next;
1857 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
1859 xfer->endpoint->isoc_next += xfer->nframes << shift;
1861 } else if (xfer->flags_int.control_xfr) {
1863 /* check if we should prepend a setup message */
1865 if (xfer->flags_int.control_hdr) {
1867 temp.len = xfer->frlengths[0];
1868 temp.pc = xfer->frbuffers + 0;
1869 temp.shortpkt = temp.len ? 1 : 0;
1870 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
1873 /* check for last frame */
1874 if (xfer->nframes == 1) {
1875 /* no STATUS stage yet, SETUP is last */
1876 if (xfer->flags_int.control_act)
1877 temp.last_frame = 1;
1880 xhci_setup_generic_chain_sub(&temp);
1884 temp.isoc_delta = 0;
1885 temp.isoc_frame = 0;
1886 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
1890 temp.isoc_delta = 0;
1891 temp.isoc_frame = 0;
1892 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
1895 if (x != xfer->nframes) {
1896 /* setup page_cache pointer */
1897 temp.pc = xfer->frbuffers + x;
1898 /* set endpoint direction */
1899 temp.direction = UE_GET_DIR(xfer->endpointno);
1902 while (x != xfer->nframes) {
1904 /* DATA0 / DATA1 message */
1906 temp.len = xfer->frlengths[x];
1907 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
1908 x != 0 && temp.multishort == 0);
1912 if (x == xfer->nframes) {
1913 if (xfer->flags_int.control_xfr) {
1914 /* no STATUS stage yet, DATA is last */
1915 if (xfer->flags_int.control_act)
1916 temp.last_frame = 1;
1918 temp.last_frame = 1;
1921 if (temp.len == 0) {
1923 /* make sure that we send an USB packet */
1928 temp.tlbpc = mult - 1;
1930 } else if (xfer->flags_int.isochronous_xfr) {
1934 /* isochronous transfers don't have short packet termination */
1938 /* isochronous transfers have a transfer limit */
1940 if (temp.len > xfer->max_frame_size)
1941 temp.len = xfer->max_frame_size;
1943 /* compute TD packet count */
1944 tdpc = (temp.len + xfer->max_packet_size - 1) /
1945 xfer->max_packet_size;
1947 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
1948 temp.tlbpc = (tdpc % mult);
1950 if (temp.tlbpc == 0)
1951 temp.tlbpc = mult - 1;
1956 /* regular data transfer */
1958 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
1961 xhci_setup_generic_chain_sub(&temp);
1963 if (xfer->flags_int.isochronous_xfr) {
1964 temp.offset += xfer->frlengths[x - 1];
1965 temp.isoc_frame += temp.isoc_delta;
1967 /* get next Page Cache pointer */
1968 temp.pc = xfer->frbuffers + x;
1972 /* check if we should append a status stage */
1974 if (xfer->flags_int.control_xfr &&
1975 !xfer->flags_int.control_act) {
1978 * Send a DATA1 message and invert the current
1979 * endpoint direction.
1981 temp.step_td = (xfer->nframes != 0);
1982 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
1986 temp.last_frame = 1;
1987 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
1989 xhci_setup_generic_chain_sub(&temp);
1994 /* must have at least one frame! */
1996 xfer->td_transfer_last = td;
1998 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2002 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2004 struct usb_page_search buf_res;
2005 struct xhci_dev_ctx_addr *pdctxa;
2007 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2009 pdctxa = buf_res.buffer;
2011 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2013 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2015 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2019 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2021 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2022 struct usb_page_search buf_inp;
2023 struct xhci_input_dev_ctx *pinp;
2026 index = udev->controller_slot_id;
2028 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2030 pinp = buf_inp.buffer;
2033 mask &= XHCI_INCTX_NON_CTRL_MASK;
2034 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2035 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2037 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2038 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2044 xhci_configure_endpoint(struct usb_device *udev,
2045 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2046 uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2047 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2049 struct usb_page_search buf_inp;
2050 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2051 struct xhci_input_dev_ctx *pinp;
2057 index = udev->controller_slot_id;
2059 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2061 pinp = buf_inp.buffer;
2063 epno = edesc->bEndpointAddress;
2064 type = edesc->bmAttributes & UE_XFERTYPE;
2066 if (type == UE_CONTROL)
2069 epno = XHCI_EPNO2EPID(epno);
2072 return (USB_ERR_NO_PIPE); /* invalid */
2074 if (max_packet_count == 0)
2075 return (USB_ERR_BAD_BUFSIZE);
2080 return (USB_ERR_BAD_BUFSIZE);
2082 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2083 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2084 XHCI_EPCTX_0_LSA_SET(0);
2086 switch (udev->speed) {
2087 case USB_SPEED_FULL:
2100 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2102 case UE_ISOCHRONOUS:
2103 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2105 switch (udev->speed) {
2106 case USB_SPEED_SUPER:
2109 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2110 max_packet_count /= mult;
2120 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2123 XHCI_EPCTX_1_HID_SET(0) |
2124 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2125 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2127 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2128 if (type != UE_ISOCHRONOUS)
2129 temp |= XHCI_EPCTX_1_CERR_SET(3);
2134 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2136 case UE_ISOCHRONOUS:
2137 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2140 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2143 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2147 /* check for IN direction */
2149 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2151 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2153 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2155 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2157 switch (edesc->bmAttributes & UE_XFERTYPE) {
2159 case UE_ISOCHRONOUS:
2160 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2161 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2165 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2168 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2172 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2175 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2177 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2179 return (0); /* success */
2183 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2185 struct xhci_endpoint_ext *pepext;
2186 struct usb_endpoint_ss_comp_descriptor *ecomp;
2188 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2189 xfer->endpoint->edesc);
2191 ecomp = xfer->endpoint->ecomp;
2193 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2194 usb_pc_cpu_flush(pepext->page_cache);
2196 return (xhci_configure_endpoint(xfer->xroot->udev,
2197 xfer->endpoint->edesc, pepext->physaddr,
2198 xfer->interval, xfer->max_packet_count,
2199 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2200 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2201 xfer->max_frame_size));
2205 xhci_configure_device(struct usb_device *udev)
2207 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2208 struct usb_page_search buf_inp;
2209 struct usb_page_cache *pcinp;
2210 struct xhci_input_dev_ctx *pinp;
2211 struct usb_device *hubdev;
2219 index = udev->controller_slot_id;
2221 DPRINTF("index=%u\n", index);
2223 pcinp = &sc->sc_hw.devs[index].input_pc;
2225 usbd_get_page(pcinp, 0, &buf_inp);
2227 pinp = buf_inp.buffer;
2232 /* figure out route string and root HUB port number */
2234 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2236 if (hubdev->parent_hub == NULL)
2239 depth = hubdev->parent_hub->depth;
2242 * NOTE: HS/FS/LS devices and the SS root HUB can have
2243 * more than 15 ports
2246 rh_port = hubdev->port_no;
2255 route |= rh_port << (4 * (depth - 1));
2258 DPRINTF("Route=0x%08x\n", route);
2260 temp = XHCI_SCTX_0_ROUTE_SET(route);
2262 switch (sc->sc_hw.devs[index].state) {
2263 case XHCI_ST_CONFIGURED:
2264 temp |= XHCI_SCTX_0_CTX_NUM_SET(XHCI_MAX_ENDPOINTS - 1);
2267 temp |= XHCI_SCTX_0_CTX_NUM_SET(1);
2271 switch (udev->speed) {
2273 temp |= XHCI_SCTX_0_SPEED_SET(2);
2275 case USB_SPEED_HIGH:
2276 temp |= XHCI_SCTX_0_SPEED_SET(3);
2278 case USB_SPEED_FULL:
2279 temp |= XHCI_SCTX_0_SPEED_SET(1);
2282 temp |= XHCI_SCTX_0_SPEED_SET(4);
2286 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2287 (udev->speed == USB_SPEED_SUPER ||
2288 udev->speed == USB_SPEED_HIGH);
2291 temp |= XHCI_SCTX_0_HUB_SET(1);
2293 if (udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2294 DPRINTF("HUB supports MTT\n");
2295 temp |= XHCI_SCTX_0_MTT_SET(1);
2300 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2302 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2305 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2306 sc->sc_hw.devs[index].nports);
2309 switch (udev->speed) {
2310 case USB_SPEED_SUPER:
2311 switch (sc->sc_hw.devs[index].state) {
2312 case XHCI_ST_ADDRESSED:
2313 case XHCI_ST_CONFIGURED:
2314 /* enable power save */
2315 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2318 /* disable power save */
2326 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2328 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2331 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(sc->sc_hw.devs[index].tt);
2333 hubdev = udev->parent_hs_hub;
2335 /* check if we should activate the transaction translator */
2336 switch (udev->speed) {
2337 case USB_SPEED_FULL:
2339 if (hubdev != NULL) {
2340 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2341 hubdev->controller_slot_id);
2342 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2350 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2352 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2353 XHCI_SCTX_3_SLOT_STATE_SET(0);
2355 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2358 xhci_dump_device(sc, &pinp->ctx_slot);
2360 usb_pc_cpu_flush(pcinp);
2362 return (0); /* success */
2366 xhci_alloc_device_ext(struct usb_device *udev)
2368 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2369 struct usb_page_search buf_dev;
2370 struct usb_page_search buf_ep;
2371 struct xhci_trb *trb;
2372 struct usb_page_cache *pc;
2373 struct usb_page *pg;
2378 index = udev->controller_slot_id;
2380 pc = &sc->sc_hw.devs[index].device_pc;
2381 pg = &sc->sc_hw.devs[index].device_pg;
2383 /* need to initialize the page cache */
2384 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2386 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2387 (2 * sizeof(struct xhci_dev_ctx)) :
2388 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2391 usbd_get_page(pc, 0, &buf_dev);
2393 pc = &sc->sc_hw.devs[index].input_pc;
2394 pg = &sc->sc_hw.devs[index].input_pg;
2396 /* need to initialize the page cache */
2397 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2399 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2400 (2 * sizeof(struct xhci_input_dev_ctx)) :
2401 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE))
2404 pc = &sc->sc_hw.devs[index].endpoint_pc;
2405 pg = &sc->sc_hw.devs[index].endpoint_pg;
2407 /* need to initialize the page cache */
2408 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2410 if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE))
2413 /* initialise all endpoint LINK TRBs */
2415 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2417 /* lookup endpoint TRB ring */
2418 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2420 /* get TRB pointer */
2421 trb = buf_ep.buffer;
2422 trb += XHCI_MAX_TRANSFERS - 1;
2424 /* get TRB start address */
2425 addr = buf_ep.physaddr;
2427 /* create LINK TRB */
2428 trb->qwTrb0 = htole64(addr);
2429 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2430 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2431 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2434 usb_pc_cpu_flush(pc);
2436 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2441 xhci_free_device_ext(udev);
2443 return (USB_ERR_NOMEM);
2447 xhci_free_device_ext(struct usb_device *udev)
2449 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2452 index = udev->controller_slot_id;
2453 xhci_set_slot_pointer(sc, index, 0);
2455 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2456 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2457 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2460 static struct xhci_endpoint_ext *
2461 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2463 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2464 struct xhci_endpoint_ext *pepext;
2465 struct usb_page_cache *pc;
2466 struct usb_page_search buf_ep;
2470 epno = edesc->bEndpointAddress;
2471 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2474 epno = XHCI_EPNO2EPID(epno);
2476 index = udev->controller_slot_id;
2478 pc = &sc->sc_hw.devs[index].endpoint_pc;
2480 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2482 pepext = &sc->sc_hw.devs[index].endp[epno];
2483 pepext->page_cache = pc;
2484 pepext->trb = buf_ep.buffer;
2485 pepext->physaddr = buf_ep.physaddr;
2491 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2493 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2497 epno = xfer->endpointno;
2498 if (xfer->flags_int.control_xfr)
2501 epno = XHCI_EPNO2EPID(epno);
2502 index = xfer->xroot->udev->controller_slot_id;
2504 if (xfer->xroot->udev->flags.self_suspended == 0)
2505 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0));
2509 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2511 struct xhci_endpoint_ext *pepext;
2513 if (xfer->flags_int.bandwidth_reclaimed) {
2514 xfer->flags_int.bandwidth_reclaimed = 0;
2516 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2517 xfer->endpoint->edesc);
2521 pepext->xfer[xfer->qh_pos] = NULL;
2523 if (error && pepext->trb_running != 0) {
2524 pepext->trb_halted = 1;
2525 pepext->trb_running = 0;
2531 xhci_transfer_insert(struct usb_xfer *xfer)
2533 struct xhci_td *td_first;
2534 struct xhci_td *td_last;
2535 struct xhci_endpoint_ext *pepext;
2543 /* check if already inserted */
2544 if (xfer->flags_int.bandwidth_reclaimed) {
2545 DPRINTFN(8, "Already in schedule\n");
2549 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2550 xfer->endpoint->edesc);
2552 td_first = xfer->td_transfer_first;
2553 td_last = xfer->td_transfer_last;
2554 addr = pepext->physaddr;
2556 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2559 /* single buffered */
2563 /* multi buffered */
2564 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2568 if (pepext->trb_used >= trb_limit) {
2569 DPRINTFN(8, "Too many TDs queued.\n");
2570 return (USB_ERR_NOMEM);
2573 /* check for stopped condition, after putting transfer on interrupt queue */
2574 if (pepext->trb_running == 0) {
2575 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2577 DPRINTFN(8, "Not running\n");
2579 /* start configuration */
2580 (void)usb_proc_msignal(&sc->sc_config_proc,
2581 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2587 /* get current TRB index */
2588 i = pepext->trb_index;
2590 /* get next TRB index */
2593 /* the last entry of the ring is a hardcoded link TRB */
2594 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2597 /* compute terminating return address */
2598 addr += inext * sizeof(struct xhci_trb);
2600 /* update next pointer of last link TRB */
2601 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr);
2602 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2603 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2604 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2607 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2609 usb_pc_cpu_flush(td_last->page_cache);
2611 /* write ahead chain end marker */
2613 pepext->trb[inext].qwTrb0 = 0;
2614 pepext->trb[inext].dwTrb2 = 0;
2615 pepext->trb[inext].dwTrb3 = 0;
2617 /* update next pointer of link TRB */
2619 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2620 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2623 xhci_dump_trb(&pepext->trb[i]);
2625 usb_pc_cpu_flush(pepext->page_cache);
2627 /* toggle cycle bit which activates the transfer chain */
2629 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2630 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2632 usb_pc_cpu_flush(pepext->page_cache);
2634 DPRINTF("qh_pos = %u\n", i);
2636 pepext->xfer[i] = xfer;
2640 xfer->flags_int.bandwidth_reclaimed = 1;
2642 pepext->trb_index = inext;
2644 xhci_endpoint_doorbell(xfer);
2650 xhci_root_intr(struct xhci_softc *sc)
2654 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2656 /* clear any old interrupt data */
2657 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2659 for (i = 1; i <= sc->sc_noport; i++) {
2660 /* pick out CHANGE bits from the status register */
2661 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2662 XHCI_PS_CSC | XHCI_PS_PEC |
2663 XHCI_PS_OCC | XHCI_PS_WRC |
2664 XHCI_PS_PRC | XHCI_PS_PLC |
2666 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2667 DPRINTF("port %d changed\n", i);
2670 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2671 sizeof(sc->sc_hub_idata));
2674 /*------------------------------------------------------------------------*
2675 * xhci_device_done - XHCI done handler
2677 * NOTE: This function can be called two times in a row on
2678 * the same USB transfer. From close and from interrupt.
2679 *------------------------------------------------------------------------*/
2681 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2683 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2684 xfer, xfer->endpoint, error);
2686 /* remove transfer from HW queue */
2687 xhci_transfer_remove(xfer, error);
2689 /* dequeue transfer and start next transfer */
2690 usbd_transfer_done(xfer, error);
2693 /*------------------------------------------------------------------------*
2694 * XHCI data transfer support (generic type)
2695 *------------------------------------------------------------------------*/
2697 xhci_device_generic_open(struct usb_xfer *xfer)
2699 if (xfer->flags_int.isochronous_xfr) {
2700 switch (xfer->xroot->udev->speed) {
2701 case USB_SPEED_FULL:
2704 usb_hs_bandwidth_alloc(xfer);
2711 xhci_device_generic_close(struct usb_xfer *xfer)
2715 xhci_device_done(xfer, USB_ERR_CANCELLED);
2717 if (xfer->flags_int.isochronous_xfr) {
2718 switch (xfer->xroot->udev->speed) {
2719 case USB_SPEED_FULL:
2722 usb_hs_bandwidth_free(xfer);
2729 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2730 struct usb_xfer *enter_xfer)
2732 struct usb_xfer *xfer;
2734 /* check if there is a current transfer */
2735 xfer = ep->endpoint_q.curr;
2740 * Check if the current transfer is started and then pickup
2741 * the next one, if any. Else wait for next start event due to
2742 * block on failure feature.
2744 if (!xfer->flags_int.bandwidth_reclaimed)
2747 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2750 * In case of enter we have to consider that the
2751 * transfer is queued by the USB core after the enter
2760 /* try to multi buffer */
2761 xhci_transfer_insert(xfer);
2765 xhci_device_generic_enter(struct usb_xfer *xfer)
2769 /* setup TD's and QH */
2770 xhci_setup_generic_chain(xfer);
2772 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2776 xhci_device_generic_start(struct usb_xfer *xfer)
2780 /* try to insert xfer on HW queue */
2781 xhci_transfer_insert(xfer);
2783 /* try to multi buffer */
2784 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2786 /* add transfer last on interrupt queue */
2787 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2789 /* start timeout, if any */
2790 if (xfer->timeout != 0)
2791 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2794 struct usb_pipe_methods xhci_device_generic_methods =
2796 .open = xhci_device_generic_open,
2797 .close = xhci_device_generic_close,
2798 .enter = xhci_device_generic_enter,
2799 .start = xhci_device_generic_start,
2802 /*------------------------------------------------------------------------*
2803 * xhci root HUB support
2804 *------------------------------------------------------------------------*
2805 * Simulate a hardware HUB by handling all the necessary requests.
2806 *------------------------------------------------------------------------*/
2808 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2811 struct usb_device_descriptor xhci_devd =
2813 .bLength = sizeof(xhci_devd),
2814 .bDescriptorType = UDESC_DEVICE, /* type */
2815 HSETW(.bcdUSB, 0x0300), /* USB version */
2816 .bDeviceClass = UDCLASS_HUB, /* class */
2817 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
2818 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
2819 .bMaxPacketSize = 9, /* max packet size */
2820 HSETW(.idVendor, 0x0000), /* vendor */
2821 HSETW(.idProduct, 0x0000), /* product */
2822 HSETW(.bcdDevice, 0x0100), /* device version */
2826 .bNumConfigurations = 1, /* # of configurations */
2830 struct xhci_bos_desc xhci_bosd = {
2832 .bLength = sizeof(xhci_bosd.bosd),
2833 .bDescriptorType = UDESC_BOS,
2834 HSETW(.wTotalLength, sizeof(xhci_bosd)),
2835 .bNumDeviceCaps = 3,
2838 .bLength = sizeof(xhci_bosd.usb2extd),
2839 .bDescriptorType = 1,
2840 .bDevCapabilityType = 2,
2841 .bmAttributes[0] = 2,
2844 .bLength = sizeof(xhci_bosd.usbdcd),
2845 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
2846 .bDevCapabilityType = 3,
2847 .bmAttributes = 0, /* XXX */
2848 HSETW(.wSpeedsSupported, 0x000C),
2849 .bFunctionalitySupport = 8,
2850 .bU1DevExitLat = 255, /* dummy - not used */
2851 .wU2DevExitLat = { 0x00, 0x08 },
2854 .bLength = sizeof(xhci_bosd.cidd),
2855 .bDescriptorType = 1,
2856 .bDevCapabilityType = 4,
2858 .bContainerID = 0, /* XXX */
2863 struct xhci_config_desc xhci_confd = {
2865 .bLength = sizeof(xhci_confd.confd),
2866 .bDescriptorType = UDESC_CONFIG,
2867 .wTotalLength[0] = sizeof(xhci_confd),
2869 .bConfigurationValue = 1,
2870 .iConfiguration = 0,
2871 .bmAttributes = UC_SELF_POWERED,
2872 .bMaxPower = 0 /* max power */
2875 .bLength = sizeof(xhci_confd.ifcd),
2876 .bDescriptorType = UDESC_INTERFACE,
2878 .bInterfaceClass = UICLASS_HUB,
2879 .bInterfaceSubClass = UISUBCLASS_HUB,
2880 .bInterfaceProtocol = 0,
2883 .bLength = sizeof(xhci_confd.endpd),
2884 .bDescriptorType = UDESC_ENDPOINT,
2885 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
2886 .bmAttributes = UE_INTERRUPT,
2887 .wMaxPacketSize[0] = 2, /* max 15 ports */
2891 .bLength = sizeof(xhci_confd.endpcd),
2892 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
2899 struct usb_hub_ss_descriptor xhci_hubd = {
2900 .bLength = sizeof(xhci_hubd),
2901 .bDescriptorType = UDESC_SS_HUB,
2905 xhci_roothub_exec(struct usb_device *udev,
2906 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2908 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2909 const char *str_ptr;
2920 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2923 ptr = (const void *)&sc->sc_hub_desc;
2927 value = UGETW(req->wValue);
2928 index = UGETW(req->wIndex);
2930 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2931 "wValue=0x%04x wIndex=0x%04x\n",
2932 req->bmRequestType, req->bRequest,
2933 UGETW(req->wLength), value, index);
2935 #define C(x,y) ((x) | ((y) << 8))
2936 switch (C(req->bRequest, req->bmRequestType)) {
2937 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2938 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2939 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2941 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2942 * for the integrated root hub.
2945 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2947 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2949 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2950 switch (value >> 8) {
2952 if ((value & 0xff) != 0) {
2953 err = USB_ERR_IOERROR;
2956 len = sizeof(xhci_devd);
2957 ptr = (const void *)&xhci_devd;
2961 if ((value & 0xff) != 0) {
2962 err = USB_ERR_IOERROR;
2965 len = sizeof(xhci_bosd);
2966 ptr = (const void *)&xhci_bosd;
2970 if ((value & 0xff) != 0) {
2971 err = USB_ERR_IOERROR;
2974 len = sizeof(xhci_confd);
2975 ptr = (const void *)&xhci_confd;
2979 switch (value & 0xff) {
2980 case 0: /* Language table */
2984 case 1: /* Vendor */
2985 str_ptr = sc->sc_vendor;
2988 case 2: /* Product */
2989 str_ptr = "XHCI root HUB";
2997 len = usb_make_str_desc(
2998 sc->sc_hub_desc.temp,
2999 sizeof(sc->sc_hub_desc.temp),
3004 err = USB_ERR_IOERROR;
3008 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3010 sc->sc_hub_desc.temp[0] = 0;
3012 case C(UR_GET_STATUS, UT_READ_DEVICE):
3014 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3016 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3017 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3019 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3021 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3022 if (value >= XHCI_MAX_DEVICES) {
3023 err = USB_ERR_IOERROR;
3027 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3028 if (value != 0 && value != 1) {
3029 err = USB_ERR_IOERROR;
3032 sc->sc_conf = value;
3034 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3036 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3037 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3038 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3039 err = USB_ERR_IOERROR;
3041 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3043 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3046 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3048 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3049 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3052 (index > sc->sc_noport)) {
3053 err = USB_ERR_IOERROR;
3056 port = XHCI_PORTSC(index);
3058 v = XREAD4(sc, oper, port);
3059 i = XHCI_PS_PLS_GET(v);
3060 v &= ~XHCI_PS_CLEAR;
3063 case UHF_C_BH_PORT_RESET:
3064 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3066 case UHF_C_PORT_CONFIG_ERROR:
3067 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3069 case UHF_C_PORT_SUSPEND:
3070 case UHF_C_PORT_LINK_STATE:
3071 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3073 case UHF_C_PORT_CONNECTION:
3074 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3076 case UHF_C_PORT_ENABLE:
3077 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3079 case UHF_C_PORT_OVER_CURRENT:
3080 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3082 case UHF_C_PORT_RESET:
3083 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3085 case UHF_PORT_ENABLE:
3086 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3088 case UHF_PORT_POWER:
3089 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3091 case UHF_PORT_INDICATOR:
3092 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3094 case UHF_PORT_SUSPEND:
3098 XWRITE4(sc, oper, port, v |
3099 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3102 /* wait 20ms for resume sequence to complete */
3103 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3106 XWRITE4(sc, oper, port, v |
3107 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3110 err = USB_ERR_IOERROR;
3115 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3116 if ((value & 0xff) != 0) {
3117 err = USB_ERR_IOERROR;
3121 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3123 sc->sc_hub_desc.hubd = xhci_hubd;
3125 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3127 if (XHCI_HCS0_PPC(v))
3128 i = UHD_PWR_INDIVIDUAL;
3132 if (XHCI_HCS0_PIND(v))
3135 i |= UHD_OC_INDIVIDUAL;
3137 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3139 /* see XHCI section 5.4.9: */
3140 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3142 for (j = 1; j <= sc->sc_noport; j++) {
3144 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3145 if (v & XHCI_PS_DR) {
3146 sc->sc_hub_desc.hubd.
3147 DeviceRemovable[j / 8] |= 1U << (j % 8);
3150 len = sc->sc_hub_desc.hubd.bLength;
3153 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3155 memset(sc->sc_hub_desc.temp, 0, 16);
3158 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3159 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3162 (index > sc->sc_noport)) {
3163 err = USB_ERR_IOERROR;
3167 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3169 DPRINTFN(9, "port status=0x%08x\n", v);
3171 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3173 switch (XHCI_PS_SPEED_GET(v)) {
3175 i |= UPS_HIGH_SPEED;
3184 i |= UPS_OTHER_SPEED;
3188 if (v & XHCI_PS_CCS)
3189 i |= UPS_CURRENT_CONNECT_STATUS;
3190 if (v & XHCI_PS_PED)
3191 i |= UPS_PORT_ENABLED;
3192 if (v & XHCI_PS_OCA)
3193 i |= UPS_OVERCURRENT_INDICATOR;
3196 if (v & XHCI_PS_PP) {
3198 * The USB 3.0 RH is using the
3199 * USB 2.0's power bit
3201 i |= UPS_PORT_POWER;
3203 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3206 if (v & XHCI_PS_CSC)
3207 i |= UPS_C_CONNECT_STATUS;
3208 if (v & XHCI_PS_PEC)
3209 i |= UPS_C_PORT_ENABLED;
3210 if (v & XHCI_PS_OCC)
3211 i |= UPS_C_OVERCURRENT_INDICATOR;
3212 if (v & XHCI_PS_WRC)
3213 i |= UPS_C_BH_PORT_RESET;
3214 if (v & XHCI_PS_PRC)
3215 i |= UPS_C_PORT_RESET;
3216 if (v & XHCI_PS_PLC)
3217 i |= UPS_C_PORT_LINK_STATE;
3218 if (v & XHCI_PS_CEC)
3219 i |= UPS_C_PORT_CONFIG_ERROR;
3221 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3222 len = sizeof(sc->sc_hub_desc.ps);
3225 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3226 err = USB_ERR_IOERROR;
3229 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3232 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3238 (index > sc->sc_noport)) {
3239 err = USB_ERR_IOERROR;
3243 port = XHCI_PORTSC(index);
3244 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3247 case UHF_PORT_U1_TIMEOUT:
3248 if (XHCI_PS_SPEED_GET(v) != 4) {
3249 err = USB_ERR_IOERROR;
3252 port = XHCI_PORTPMSC(index);
3253 v = XREAD4(sc, oper, port);
3254 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3255 v |= XHCI_PM3_U1TO_SET(i);
3256 XWRITE4(sc, oper, port, v);
3258 case UHF_PORT_U2_TIMEOUT:
3259 if (XHCI_PS_SPEED_GET(v) != 4) {
3260 err = USB_ERR_IOERROR;
3263 port = XHCI_PORTPMSC(index);
3264 v = XREAD4(sc, oper, port);
3265 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3266 v |= XHCI_PM3_U2TO_SET(i);
3267 XWRITE4(sc, oper, port, v);
3269 case UHF_BH_PORT_RESET:
3270 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3272 case UHF_PORT_LINK_STATE:
3273 XWRITE4(sc, oper, port, v |
3274 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3275 /* 4ms settle time */
3276 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3278 case UHF_PORT_ENABLE:
3279 DPRINTFN(3, "set port enable %d\n", index);
3281 case UHF_PORT_SUSPEND:
3282 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3283 j = XHCI_PS_SPEED_GET(v);
3284 if ((j < 1) || (j > 3)) {
3285 /* non-supported speed */
3286 err = USB_ERR_IOERROR;
3289 XWRITE4(sc, oper, port, v |
3290 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3292 case UHF_PORT_RESET:
3293 DPRINTFN(6, "reset port %d\n", index);
3294 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3296 case UHF_PORT_POWER:
3297 DPRINTFN(3, "set port power %d\n", index);
3298 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3301 DPRINTFN(3, "set port test %d\n", index);
3303 case UHF_PORT_INDICATOR:
3304 DPRINTFN(3, "set port indicator %d\n", index);
3306 v &= ~XHCI_PS_PIC_SET(3);
3307 v |= XHCI_PS_PIC_SET(1);
3309 XWRITE4(sc, oper, port, v);
3312 err = USB_ERR_IOERROR;
3317 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3318 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3319 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3320 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3323 err = USB_ERR_IOERROR;
3333 xhci_xfer_setup(struct usb_setup_params *parm)
3335 struct usb_page_search page_info;
3336 struct usb_page_cache *pc;
3337 struct xhci_softc *sc;
3338 struct usb_xfer *xfer;
3343 sc = XHCI_BUS2SC(parm->udev->bus);
3344 xfer = parm->curr_xfer;
3347 * The proof for the "ntd" formula is illustrated like this:
3349 * +------------------------------------+
3353 * | | xxx | x | frm 0 |
3355 * | | xxx | xx | frm 1 |
3358 * +------------------------------------+
3360 * "xxx" means a completely full USB transfer descriptor
3362 * "x" and "xx" means a short USB packet
3364 * For the remainder of an USB transfer modulo
3365 * "max_data_length" we need two USB transfer descriptors.
3366 * One to transfer the remaining data and one to finalise with
3367 * a zero length packet in case the "force_short_xfer" flag is
3368 * set. We only need two USB transfer descriptors in the case
3369 * where the transfer length of the first one is a factor of
3370 * "max_frame_size". The rest of the needed USB transfer
3371 * descriptors is given by the buffer size divided by the
3372 * maximum data payload.
3374 parm->hc_max_packet_size = 0x400;
3375 parm->hc_max_packet_count = 16 * 3;
3376 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3378 xfer->flags_int.bdma_enable = 1;
3380 usbd_transfer_setup_sub(parm);
3382 if (xfer->flags_int.isochronous_xfr) {
3383 ntd = ((1 * xfer->nframes)
3384 + (xfer->max_data_length / xfer->max_hc_frame_size));
3385 } else if (xfer->flags_int.control_xfr) {
3386 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3387 + (xfer->max_data_length / xfer->max_hc_frame_size));
3389 ntd = ((2 * xfer->nframes)
3390 + (xfer->max_data_length / xfer->max_hc_frame_size));
3399 * Allocate queue heads and transfer descriptors
3403 if (usbd_transfer_setup_sub_malloc(
3404 parm, &pc, sizeof(struct xhci_td),
3405 XHCI_TD_ALIGN, ntd)) {
3406 parm->err = USB_ERR_NOMEM;
3410 for (n = 0; n != ntd; n++) {
3413 usbd_get_page(pc + n, 0, &page_info);
3415 td = page_info.buffer;
3418 td->td_self = page_info.physaddr;
3419 td->obj_next = last_obj;
3420 td->page_cache = pc + n;
3424 usb_pc_cpu_flush(pc + n);
3427 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3429 if (!xfer->flags_int.curr_dma_set) {
3430 xfer->flags_int.curr_dma_set = 1;
3436 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3438 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3439 struct usb_page_search buf_inp;
3440 struct usb_device *udev;
3441 struct xhci_endpoint_ext *pepext;
3442 struct usb_endpoint_descriptor *edesc;
3443 struct usb_page_cache *pcinp;
3448 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3449 xfer->endpoint->edesc);
3451 udev = xfer->xroot->udev;
3452 index = udev->controller_slot_id;
3454 pcinp = &sc->sc_hw.devs[index].input_pc;
3456 usbd_get_page(pcinp, 0, &buf_inp);
3458 edesc = xfer->endpoint->edesc;
3460 epno = edesc->bEndpointAddress;
3462 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3465 epno = XHCI_EPNO2EPID(epno);
3468 return (USB_ERR_NO_PIPE); /* invalid */
3472 /* configure endpoint */
3474 err = xhci_configure_endpoint_by_xfer(xfer);
3477 XHCI_CMD_UNLOCK(sc);
3482 * Get the endpoint into the stopped state according to the
3483 * endpoint context state diagram in the XHCI specification:
3486 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3489 DPRINTF("Could not stop endpoint %u\n", epno);
3491 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3494 DPRINTF("Could not reset endpoint %u\n", epno);
3496 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3497 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3500 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3503 * Get the endpoint into the running state according to the
3504 * endpoint context state diagram in the XHCI specification:
3507 xhci_configure_mask(udev, 1U << epno, 0);
3509 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3512 DPRINTF("Could not configure endpoint %u\n", epno);
3514 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3517 DPRINTF("Could not configure endpoint %u\n", epno);
3519 XHCI_CMD_UNLOCK(sc);
3525 xhci_xfer_unsetup(struct usb_xfer *xfer)
3531 xhci_start_dma_delay(struct usb_xfer *xfer)
3533 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3535 /* put transfer on interrupt queue (again) */
3536 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3538 (void)usb_proc_msignal(&sc->sc_config_proc,
3539 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3543 xhci_configure_msg(struct usb_proc_msg *pm)
3545 struct xhci_softc *sc;
3546 struct xhci_endpoint_ext *pepext;
3547 struct usb_xfer *xfer;
3549 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3552 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3554 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3555 xfer->endpoint->edesc);
3557 if ((pepext->trb_halted != 0) ||
3558 (pepext->trb_running == 0)) {
3562 /* clear halted and running */
3563 pepext->trb_halted = 0;
3564 pepext->trb_running = 0;
3566 /* nuke remaining buffered transfers */
3568 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3570 * NOTE: We need to use the timeout
3571 * error code here else existing
3572 * isochronous clients can get
3575 if (pepext->xfer[i] != NULL) {
3576 xhci_device_done(pepext->xfer[i],
3582 * NOTE: The USB transfer cannot vanish in
3586 USB_BUS_UNLOCK(&sc->sc_bus);
3588 xhci_configure_reset_endpoint(xfer);
3590 USB_BUS_LOCK(&sc->sc_bus);
3592 /* check if halted is still cleared */
3593 if (pepext->trb_halted == 0) {
3594 pepext->trb_running = 1;
3595 pepext->trb_index = 0;
3600 if (xfer->flags_int.did_dma_delay) {
3602 /* remove transfer from interrupt queue (again) */
3603 usbd_transfer_dequeue(xfer);
3605 /* we are finally done */
3606 usb_dma_delay_done_cb(xfer);
3608 /* queue changed - restart */
3613 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3615 /* try to insert xfer on HW queue */
3616 xhci_transfer_insert(xfer);
3618 /* try to multi buffer */
3619 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3624 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3625 struct usb_endpoint *ep)
3627 struct xhci_endpoint_ext *pepext;
3629 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3630 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3632 if (udev->flags.usb_mode != USB_MODE_HOST) {
3636 if (udev->parent_hub == NULL) {
3637 /* root HUB has special endpoint handling */
3641 ep->methods = &xhci_device_generic_methods;
3643 pepext = xhci_get_endpoint_ext(udev, edesc);
3645 USB_BUS_LOCK(udev->bus);
3646 pepext->trb_halted = 1;
3647 pepext->trb_running = 0;
3648 USB_BUS_UNLOCK(udev->bus);
3652 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3658 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3660 struct xhci_endpoint_ext *pepext;
3664 if (udev->flags.usb_mode != USB_MODE_HOST) {
3668 if (udev->parent_hub == NULL) {
3669 /* root HUB has special endpoint handling */
3673 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3675 USB_BUS_LOCK(udev->bus);
3676 pepext->trb_halted = 1;
3677 pepext->trb_running = 0;
3678 USB_BUS_UNLOCK(udev->bus);
3682 xhci_device_init(struct usb_device *udev)
3684 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3688 /* no init for root HUB */
3689 if (udev->parent_hub == NULL)
3694 /* set invalid default */
3696 udev->controller_slot_id = sc->sc_noslot + 1;
3698 /* try to get a new slot ID from the XHCI */
3700 err = xhci_cmd_enable_slot(sc, &temp);
3703 XHCI_CMD_UNLOCK(sc);
3707 if (temp > sc->sc_noslot) {
3708 XHCI_CMD_UNLOCK(sc);
3709 return (USB_ERR_BAD_ADDRESS);
3712 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3713 DPRINTF("slot %u already allocated.\n", temp);
3714 XHCI_CMD_UNLOCK(sc);
3715 return (USB_ERR_BAD_ADDRESS);
3718 /* store slot ID for later reference */
3720 udev->controller_slot_id = temp;
3722 /* reset data structure */
3724 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3726 /* set mark slot allocated */
3728 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3730 err = xhci_alloc_device_ext(udev);
3732 XHCI_CMD_UNLOCK(sc);
3734 /* get device into default state */
3737 err = xhci_set_address(udev, NULL, 0);
3743 xhci_device_uninit(struct usb_device *udev)
3745 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3748 /* no init for root HUB */
3749 if (udev->parent_hub == NULL)
3754 index = udev->controller_slot_id;
3756 if (index <= sc->sc_noslot) {
3757 xhci_cmd_disable_slot(sc, index);
3758 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3760 /* free device extension */
3761 xhci_free_device_ext(udev);
3764 XHCI_CMD_UNLOCK(sc);
3768 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3771 * Wait until the hardware has finished any possible use of
3772 * the transfer descriptor(s)
3774 *pus = 2048; /* microseconds */
3778 xhci_device_resume(struct usb_device *udev)
3780 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3786 /* check for root HUB */
3787 if (udev->parent_hub == NULL)
3790 index = udev->controller_slot_id;
3794 /* blindly resume all endpoints */
3796 USB_BUS_LOCK(udev->bus);
3798 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++)
3799 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0));
3801 USB_BUS_UNLOCK(udev->bus);
3803 XHCI_CMD_UNLOCK(sc);
3807 xhci_device_suspend(struct usb_device *udev)
3809 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3816 /* check for root HUB */
3817 if (udev->parent_hub == NULL)
3820 index = udev->controller_slot_id;
3824 /* blindly suspend all endpoints */
3826 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3827 err = xhci_cmd_stop_ep(sc, 1, n, index);
3829 DPRINTF("Failed to suspend endpoint "
3830 "%u on slot %u (ignored).\n", n, index);
3834 XHCI_CMD_UNLOCK(sc);
3838 xhci_set_hw_power(struct usb_bus *bus)
3844 xhci_device_state_change(struct usb_device *udev)
3846 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3847 struct usb_page_search buf_inp;
3851 /* check for root HUB */
3852 if (udev->parent_hub == NULL)
3855 index = udev->controller_slot_id;
3859 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
3860 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
3861 &sc->sc_hw.devs[index].tt);
3863 sc->sc_hw.devs[index].nports = 0;
3868 switch (usb_get_device_state(udev)) {
3869 case USB_STATE_POWERED:
3870 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
3873 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
3875 err = xhci_cmd_reset_dev(sc, index);
3878 DPRINTF("Device reset failed "
3879 "for slot %u.\n", index);
3883 case USB_STATE_ADDRESSED:
3884 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
3887 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
3889 err = xhci_cmd_configure_ep(sc, 0, 1, index);
3892 DPRINTF("Failed to deconfigure "
3893 "slot %u.\n", index);
3897 case USB_STATE_CONFIGURED:
3898 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
3901 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
3903 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
3905 xhci_configure_mask(udev, 1, 0);
3907 err = xhci_configure_device(udev);
3909 DPRINTF("Could not configure device "
3910 "at slot %u.\n", index);
3913 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3915 DPRINTF("Could not evaluate device "
3916 "context at slot %u.\n", index);
3923 XHCI_CMD_UNLOCK(sc);
3926 struct usb_bus_methods xhci_bus_methods = {
3927 .endpoint_init = xhci_ep_init,
3928 .endpoint_uninit = xhci_ep_uninit,
3929 .xfer_setup = xhci_xfer_setup,
3930 .xfer_unsetup = xhci_xfer_unsetup,
3931 .get_dma_delay = xhci_get_dma_delay,
3932 .device_init = xhci_device_init,
3933 .device_uninit = xhci_device_uninit,
3934 .device_resume = xhci_device_resume,
3935 .device_suspend = xhci_device_suspend,
3936 .set_hw_power = xhci_set_hw_power,
3937 .roothub_exec = xhci_roothub_exec,
3938 .xfer_poll = xhci_do_poll,
3939 .start_dma_delay = xhci_start_dma_delay,
3940 .set_address = xhci_set_address,
3941 .clear_stall = xhci_ep_clear_stall,
3942 .device_state_change = xhci_device_state_change,
3943 .set_hw_power_sleep = xhci_set_hw_power_sleep,