2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38 * Used in the LinkSys USB200M and various other adapters.
40 * Manuals available from:
41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43 * controller) to find the definitions for the RX control register.
44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
46 * Written by Bill Paul <wpaul@windriver.com>
52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53 * It uses an external PHY (reference designs use a RealTek chip),
54 * and has a 64-bit multicast hash filter. There is some information
55 * missing from the manual which one needs to know in order to make
58 * - You must set bit 7 in the RX control register, otherwise the
59 * chip won't receive any packets.
60 * - You must initialize all 3 IPG registers, or you won't be able
61 * to send any packets.
63 * Note that this device appears to only support loading the station
64 * address via autload from the EEPROM (i.e. there's no way to manaully
67 * (Adam Weinberger wanted me to name this driver if_gir.c.)
71 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
79 #include <sys/param.h>
80 #include <sys/systm.h>
82 #include <sys/condvar.h>
83 #include <sys/endian.h>
84 #include <sys/kernel.h>
86 #include <sys/malloc.h>
88 #include <sys/module.h>
89 #include <sys/mutex.h>
90 #include <sys/socket.h>
91 #include <sys/sockio.h>
92 #include <sys/sysctl.h>
96 #include <net/ethernet.h>
97 #include <net/if_types.h>
98 #include <net/if_media.h>
99 #include <net/if_vlan_var.h>
101 #include <dev/mii/mii.h>
102 #include <dev/mii/miivar.h>
104 #include <dev/usb/usb.h>
105 #include <dev/usb/usbdi.h>
106 #include <dev/usb/usbdi_util.h>
109 #define USB_DEBUG_VAR axe_debug
110 #include <dev/usb/usb_debug.h>
111 #include <dev/usb/usb_process.h>
113 #include <dev/usb/net/usb_ethernet.h>
114 #include <dev/usb/net/if_axereg.h>
117 * AXE_178_MAX_FRAME_BURST
118 * max frame burst size for Ax88178 and Ax88772
123 * use the largest your system can handle without USB stalling.
125 * NB: 88772 parts appear to generate lots of input errors with
126 * a 2K rx buffer and 8K is only slightly faster than 4K on an
127 * EHCI port on a T42 so change at your own risk.
129 #define AXE_178_MAX_FRAME_BURST 1
131 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
134 static int axe_debug = 0;
136 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
137 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
142 * Various supported device vendors/products.
144 static const STRUCT_USB_HOST_ID axe_devs[] = {
145 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
146 AXE_DEV(ABOCOM, UF200, 0),
147 AXE_DEV(ACERCM, EP1427X2, 0),
148 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
149 AXE_DEV(ASIX, AX88172, 0),
150 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
151 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
152 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
153 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
154 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
155 AXE_DEV(ATEN, UC210T, 0),
156 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
157 AXE_DEV(BILLIONTON, USB2AR, 0),
158 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
159 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
160 AXE_DEV(DLINK, DUBE100, 0),
161 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
162 AXE_DEV(GOODWAY, GWUSB2E, 0),
163 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
164 AXE_DEV(JVC, MP_PRX1, 0),
165 AXE_DEV(LINKSYS2, USB200M, 0),
166 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
167 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
168 AXE_DEV(MELCO, LUAU2KTX, 0),
169 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
170 AXE_DEV(NETGEAR, FA120, 0),
171 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
172 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
173 AXE_DEV(SITECOM, LN029, 0),
174 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
175 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
179 static device_probe_t axe_probe;
180 static device_attach_t axe_attach;
181 static device_detach_t axe_detach;
183 static usb_callback_t axe_bulk_read_callback;
184 static usb_callback_t axe_bulk_write_callback;
186 static miibus_readreg_t axe_miibus_readreg;
187 static miibus_writereg_t axe_miibus_writereg;
188 static miibus_statchg_t axe_miibus_statchg;
190 static uether_fn_t axe_attach_post;
191 static uether_fn_t axe_init;
192 static uether_fn_t axe_stop;
193 static uether_fn_t axe_start;
194 static uether_fn_t axe_tick;
195 static uether_fn_t axe_setmulti;
196 static uether_fn_t axe_setpromisc;
198 static int axe_attach_post_sub(struct usb_ether *);
199 static int axe_ifmedia_upd(struct ifnet *);
200 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
201 static int axe_cmd(struct axe_softc *, int, int, int, void *);
202 static void axe_ax88178_init(struct axe_softc *);
203 static void axe_ax88772_init(struct axe_softc *);
204 static void axe_ax88772_phywake(struct axe_softc *);
205 static void axe_ax88772a_init(struct axe_softc *);
206 static void axe_ax88772b_init(struct axe_softc *);
207 static int axe_get_phyno(struct axe_softc *, int);
208 static int axe_ioctl(struct ifnet *, u_long, caddr_t);
209 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
210 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *,
211 unsigned int offset, unsigned int, struct axe_csum_hdr *);
212 static void axe_csum_cfg(struct usb_ether *);
214 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
218 .endpoint = UE_ADDR_ANY,
219 .direction = UE_DIR_OUT,
221 .bufsize = 16 * MCLBYTES,
222 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
223 .callback = axe_bulk_write_callback,
224 .timeout = 10000, /* 10 seconds */
229 .endpoint = UE_ADDR_ANY,
230 .direction = UE_DIR_IN,
231 .bufsize = 16384, /* bytes */
232 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
233 .callback = axe_bulk_read_callback,
234 .timeout = 0, /* no timeout */
238 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
239 { 0x8000, 0x8001, 2048 },
240 { 0x8100, 0x8147, 4096},
241 { 0x8200, 0x81EB, 6144},
242 { 0x8300, 0x83D7, 8192},
243 { 0x8400, 0x851E, 16384},
244 { 0x8500, 0x8666, 20480},
245 { 0x8600, 0x87AE, 24576},
246 { 0x8700, 0x8A3D, 32768}
249 static device_method_t axe_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, axe_probe),
252 DEVMETHOD(device_attach, axe_attach),
253 DEVMETHOD(device_detach, axe_detach),
256 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
257 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
258 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
263 static driver_t axe_driver = {
265 .methods = axe_methods,
266 .size = sizeof(struct axe_softc),
269 static devclass_t axe_devclass;
271 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
272 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
273 MODULE_DEPEND(axe, uether, 1, 1, 1);
274 MODULE_DEPEND(axe, usb, 1, 1, 1);
275 MODULE_DEPEND(axe, ether, 1, 1, 1);
276 MODULE_DEPEND(axe, miibus, 1, 1, 1);
277 MODULE_VERSION(axe, 1);
279 static const struct usb_ether_methods axe_ue_methods = {
280 .ue_attach_post = axe_attach_post,
281 .ue_attach_post_sub = axe_attach_post_sub,
282 .ue_start = axe_start,
286 .ue_setmulti = axe_setmulti,
287 .ue_setpromisc = axe_setpromisc,
288 .ue_mii_upd = axe_ifmedia_upd,
289 .ue_mii_sts = axe_ifmedia_sts,
293 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
295 struct usb_device_request req;
298 AXE_LOCK_ASSERT(sc, MA_OWNED);
300 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
301 UT_WRITE_VENDOR_DEVICE :
302 UT_READ_VENDOR_DEVICE);
303 req.bRequest = AXE_CMD_CMD(cmd);
304 USETW(req.wValue, val);
305 USETW(req.wIndex, index);
306 USETW(req.wLength, AXE_CMD_LEN(cmd));
308 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
314 axe_miibus_readreg(device_t dev, int phy, int reg)
316 struct axe_softc *sc = device_get_softc(dev);
320 locked = mtx_owned(&sc->sc_mtx);
324 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
325 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
326 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
329 if (AXE_IS_772(sc) && reg == MII_BMSR) {
331 * BMSR of AX88772 indicates that it supports extended
332 * capability but the extended status register is
333 * revered for embedded ethernet PHY. So clear the
334 * extended capability bit of BMSR.
345 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
347 struct axe_softc *sc = device_get_softc(dev);
351 locked = mtx_owned(&sc->sc_mtx);
355 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
356 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
357 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
365 axe_miibus_statchg(device_t dev)
367 struct axe_softc *sc = device_get_softc(dev);
368 struct mii_data *mii = GET_MII(sc);
373 locked = mtx_owned(&sc->sc_mtx);
377 ifp = uether_getifp(&sc->sc_ue);
378 if (mii == NULL || ifp == NULL ||
379 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
382 sc->sc_flags &= ~AXE_FLAG_LINK;
383 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
384 (IFM_ACTIVE | IFM_AVALID)) {
385 switch (IFM_SUBTYPE(mii->mii_media_active)) {
388 sc->sc_flags |= AXE_FLAG_LINK;
391 if ((sc->sc_flags & AXE_FLAG_178) == 0)
393 sc->sc_flags |= AXE_FLAG_LINK;
400 /* Lost link, do nothing. */
401 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
405 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
406 val |= AXE_MEDIA_FULL_DUPLEX;
407 if (AXE_IS_178_FAMILY(sc)) {
408 if ((IFM_OPTIONS(mii->mii_media_active) &
409 IFM_ETH_TXPAUSE) != 0)
410 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
411 if ((IFM_OPTIONS(mii->mii_media_active) &
412 IFM_ETH_RXPAUSE) != 0)
413 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
416 if (AXE_IS_178_FAMILY(sc)) {
417 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
418 if ((sc->sc_flags & AXE_FLAG_178) != 0)
419 val |= AXE_178_MEDIA_ENCK;
420 switch (IFM_SUBTYPE(mii->mii_media_active)) {
422 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
425 val |= AXE_178_MEDIA_100TX;
428 /* doesn't need to be handled */
432 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
434 device_printf(dev, "media change failed, error %d\n", err);
444 axe_ifmedia_upd(struct ifnet *ifp)
446 struct axe_softc *sc = ifp->if_softc;
447 struct mii_data *mii = GET_MII(sc);
448 struct mii_softc *miisc;
451 AXE_LOCK_ASSERT(sc, MA_OWNED);
453 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
455 error = mii_mediachg(mii);
460 * Report current media status.
463 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
465 struct axe_softc *sc = ifp->if_softc;
466 struct mii_data *mii = GET_MII(sc);
470 ifmr->ifm_active = mii->mii_media_active;
471 ifmr->ifm_status = mii->mii_media_status;
476 axe_setmulti(struct usb_ether *ue)
478 struct axe_softc *sc = uether_getsc(ue);
479 struct ifnet *ifp = uether_getifp(ue);
480 struct ifmultiaddr *ifma;
483 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
485 AXE_LOCK_ASSERT(sc, MA_OWNED);
487 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
488 rxmode = le16toh(rxmode);
490 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
491 rxmode |= AXE_RXCMD_ALLMULTI;
492 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
495 rxmode &= ~AXE_RXCMD_ALLMULTI;
498 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
500 if (ifma->ifma_addr->sa_family != AF_LINK)
502 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
503 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
504 hashtbl[h / 8] |= 1 << (h % 8);
506 if_maddr_runlock(ifp);
508 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
509 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
513 axe_get_phyno(struct axe_softc *sc, int sel)
517 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
518 case PHY_TYPE_100_HOME:
520 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
522 case PHY_TYPE_SPECIAL:
526 case PHY_TYPE_NON_SUP:
536 #define AXE_GPIO_WRITE(x, y) do { \
537 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
538 uether_pause(ue, (y)); \
542 axe_ax88178_init(struct axe_softc *sc)
544 struct usb_ether *ue;
545 int gpio0, ledmode, phymode;
546 uint16_t eeprom, val;
549 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
551 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
552 eeprom = le16toh(eeprom);
553 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
555 /* if EEPROM is invalid we have to use to GPIO0 */
556 if (eeprom == 0xffff) {
557 phymode = AXE_PHY_MODE_MARVELL;
561 phymode = eeprom & 0x7f;
562 gpio0 = (eeprom & 0x80) ? 0 : 1;
563 ledmode = eeprom >> 8;
567 device_printf(sc->sc_ue.ue_dev,
568 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
570 /* Program GPIOs depending on PHY hardware. */
572 case AXE_PHY_MODE_MARVELL:
574 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
576 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
578 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
579 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
582 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
583 AXE_GPIO1_EN, hz / 3);
585 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
586 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
589 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
590 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
591 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
592 AXE_GPIO2_EN, hz / 4);
593 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
594 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
598 case AXE_PHY_MODE_CICADA:
599 case AXE_PHY_MODE_CICADA_V2:
600 case AXE_PHY_MODE_CICADA_V2_ASIX:
602 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
603 AXE_GPIO0_EN, hz / 32);
605 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
606 AXE_GPIO1_EN, hz / 32);
608 case AXE_PHY_MODE_AGERE:
609 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
610 AXE_GPIO1_EN, hz / 32);
611 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
612 AXE_GPIO2_EN, hz / 32);
613 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
614 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
615 AXE_GPIO2_EN, hz / 32);
617 case AXE_PHY_MODE_REALTEK_8211CL:
618 case AXE_PHY_MODE_REALTEK_8211BN:
619 case AXE_PHY_MODE_REALTEK_8251CL:
620 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
621 AXE_GPIO1 | AXE_GPIO1_EN;
622 AXE_GPIO_WRITE(val, hz / 32);
623 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
624 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
625 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
626 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
627 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
629 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
631 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
633 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
635 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
640 /* Unknown PHY model or no need to program GPIOs. */
645 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
646 uether_pause(ue, hz / 4);
648 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
649 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
650 uether_pause(ue, hz / 4);
651 /* Enable MII/GMII/RGMII interface to work with external PHY. */
652 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
653 uether_pause(ue, hz / 4);
655 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
659 axe_ax88772_init(struct axe_softc *sc)
661 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
662 uether_pause(&sc->sc_ue, hz / 16);
664 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
665 /* ask for the embedded PHY */
666 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
667 uether_pause(&sc->sc_ue, hz / 64);
669 /* power down and reset state, pin reset state */
670 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
671 AXE_SW_RESET_CLEAR, NULL);
672 uether_pause(&sc->sc_ue, hz / 16);
674 /* power down/reset state, pin operating state */
675 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
676 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
677 uether_pause(&sc->sc_ue, hz / 4);
679 /* power up, reset */
680 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
682 /* power up, operating */
683 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
684 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
686 /* ask for external PHY */
687 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
688 uether_pause(&sc->sc_ue, hz / 64);
690 /* power down internal PHY */
691 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
692 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
695 uether_pause(&sc->sc_ue, hz / 4);
696 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
700 axe_ax88772_phywake(struct axe_softc *sc)
702 struct usb_ether *ue;
705 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
706 /* Manually select internal(embedded) PHY - MAC mode. */
707 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
708 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
710 uether_pause(&sc->sc_ue, hz / 32);
713 * Manually select external PHY - MAC mode.
714 * Reverse MII/RMII is for AX88772A PHY mode.
716 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
717 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
718 uether_pause(&sc->sc_ue, hz / 32);
720 /* Take PHY out of power down. */
721 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
722 AXE_SW_RESET_IPRL, NULL);
723 uether_pause(&sc->sc_ue, hz / 4);
724 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
725 uether_pause(&sc->sc_ue, hz);
726 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
727 uether_pause(&sc->sc_ue, hz / 32);
728 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
729 uether_pause(&sc->sc_ue, hz / 32);
733 axe_ax88772a_init(struct axe_softc *sc)
735 struct usb_ether *ue;
739 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
740 axe_ax88772_phywake(sc);
742 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
746 axe_ax88772b_init(struct axe_softc *sc)
748 struct usb_ether *ue;
755 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
757 * Save PHY power saving configuration(high byte) and
758 * clear EEPROM checksum value(low byte).
760 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
761 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
764 * Auto-loaded default station address from internal ROM is
765 * 00:00:00:00:00:00 such that an explicit access to EEPROM
766 * is required to get real station address.
768 eaddr = ue->ue_eaddr;
769 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
770 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
772 eeprom = le16toh(eeprom);
773 *eaddr++ = (uint8_t)(eeprom & 0xFF);
774 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
777 axe_ax88772_phywake(sc);
779 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
782 #undef AXE_GPIO_WRITE
785 axe_reset(struct axe_softc *sc)
787 struct usb_config_descriptor *cd;
790 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
792 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
793 cd->bConfigurationValue);
795 DPRINTF("reset failed (ignored)\n");
797 /* Wait a little while for the chip to get its brains in order. */
798 uether_pause(&sc->sc_ue, hz / 100);
800 /* Reinitialize controller to achieve full reset. */
801 if (sc->sc_flags & AXE_FLAG_178)
802 axe_ax88178_init(sc);
803 else if (sc->sc_flags & AXE_FLAG_772)
804 axe_ax88772_init(sc);
805 else if (sc->sc_flags & AXE_FLAG_772A)
806 axe_ax88772a_init(sc);
807 else if (sc->sc_flags & AXE_FLAG_772B)
808 axe_ax88772b_init(sc);
812 axe_attach_post(struct usb_ether *ue)
814 struct axe_softc *sc = uether_getsc(ue);
817 * Load PHY indexes first. Needed by axe_xxx_init().
819 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
821 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
822 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
823 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
824 if (sc->sc_phyno == -1)
825 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
826 if (sc->sc_phyno == -1) {
827 device_printf(sc->sc_ue.ue_dev,
828 "no valid PHY address found, assuming PHY address 0\n");
832 /* Initialize controller and get station address. */
833 if (sc->sc_flags & AXE_FLAG_178) {
834 axe_ax88178_init(sc);
835 sc->sc_tx_bufsz = 16 * 1024;
836 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
837 } else if (sc->sc_flags & AXE_FLAG_772) {
838 axe_ax88772_init(sc);
839 sc->sc_tx_bufsz = 8 * 1024;
840 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
841 } else if (sc->sc_flags & AXE_FLAG_772A) {
842 axe_ax88772a_init(sc);
843 sc->sc_tx_bufsz = 8 * 1024;
844 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
845 } else if (sc->sc_flags & AXE_FLAG_772B) {
846 axe_ax88772b_init(sc);
847 sc->sc_tx_bufsz = 8 * 1024;
849 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
854 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
855 /* Set IPG values. */
856 sc->sc_ipgs[0] = 0x15;
857 sc->sc_ipgs[1] = 0x16;
858 sc->sc_ipgs[2] = 0x1A;
860 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
864 axe_attach_post_sub(struct usb_ether *ue)
866 struct axe_softc *sc;
871 sc = uether_getsc(ue);
873 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
874 ifp->if_start = uether_start;
875 ifp->if_ioctl = axe_ioctl;
876 ifp->if_init = uether_init;
877 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
878 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
879 IFQ_SET_READY(&ifp->if_snd);
881 if (AXE_IS_178_FAMILY(sc))
882 ifp->if_capabilities |= IFCAP_VLAN_MTU;
883 if (sc->sc_flags & AXE_FLAG_772B) {
884 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM;
885 ifp->if_hwassist = AXE_CSUM_FEATURES;
887 * Checksum offloading of AX88772B also works with VLAN
888 * tagged frames but there is no way to take advantage
889 * of the feature because vlan(4) assumes
890 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
891 * support checksum offloading with VLAN. VLAN hardware
892 * tagging support of AX88772B is very limited so it's
893 * not possible to announce IFCAP_VLAN_HWTAGGING.
896 ifp->if_capenable = ifp->if_capabilities;
897 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
898 adv_pause = MIIF_DOPAUSE;
902 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
903 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
904 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
911 * Probe for a AX88172 chip.
914 axe_probe(device_t dev)
916 struct usb_attach_arg *uaa = device_get_ivars(dev);
918 if (uaa->usb_mode != USB_MODE_HOST)
920 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
922 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
925 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
929 * Attach the interface. Allocate softc structures, do ifmedia
930 * setup and ethernet/BPF attach.
933 axe_attach(device_t dev)
935 struct usb_attach_arg *uaa = device_get_ivars(dev);
936 struct axe_softc *sc = device_get_softc(dev);
937 struct usb_ether *ue = &sc->sc_ue;
941 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
943 device_set_usb_desc(dev);
945 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
947 iface_index = AXE_IFACE_IDX;
948 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
949 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
951 device_printf(dev, "allocating USB transfers failed\n");
957 ue->ue_udev = uaa->device;
958 ue->ue_mtx = &sc->sc_mtx;
959 ue->ue_methods = &axe_ue_methods;
961 error = uether_ifattach(ue);
963 device_printf(dev, "could not attach interface\n");
966 return (0); /* success */
970 return (ENXIO); /* failure */
974 axe_detach(device_t dev)
976 struct axe_softc *sc = device_get_softc(dev);
977 struct usb_ether *ue = &sc->sc_ue;
979 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
981 mtx_destroy(&sc->sc_mtx);
986 #if (AXE_BULK_BUF_SIZE >= 0x10000)
987 #error "Please update axe_bulk_read_callback()!"
991 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
993 struct axe_softc *sc = usbd_xfer_softc(xfer);
994 struct usb_ether *ue = &sc->sc_ue;
995 struct usb_page_cache *pc;
998 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
1000 switch (USB_GET_STATE(xfer)) {
1001 case USB_ST_TRANSFERRED:
1002 pc = usbd_xfer_get_frame(xfer, 0);
1003 axe_rx_frame(ue, pc, actlen);
1008 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1009 usbd_transfer_submit(xfer);
1013 default: /* Error */
1014 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1016 if (error != USB_ERR_CANCELLED) {
1017 /* try to clear stall first */
1018 usbd_xfer_set_stall(xfer);
1027 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1029 struct axe_softc *sc;
1030 struct axe_sframe_hdr hdr;
1031 struct axe_csum_hdr csum_hdr;
1032 int error, len, pos;
1034 sc = uether_getsc(ue);
1038 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1039 while (pos < actlen) {
1040 if ((int)(pos + sizeof(hdr)) > actlen) {
1041 /* too little data */
1045 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1047 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1053 len = le16toh(hdr.len);
1054 if (pos + len > actlen) {
1055 /* invalid length */
1059 axe_rxeof(ue, pc, pos, len, NULL);
1060 pos += len + (len % 2);
1062 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1063 while (pos < actlen) {
1064 if ((int)(pos + sizeof(csum_hdr)) > actlen) {
1065 /* too little data */
1069 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1071 csum_hdr.len = le16toh(csum_hdr.len);
1072 csum_hdr.ilen = le16toh(csum_hdr.ilen);
1073 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1074 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1075 AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1082 * Get total transferred frame length including
1083 * checksum header. The length should be multiple
1086 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1087 len = (len + 3) & ~3;
1088 if (pos + len > actlen) {
1089 /* invalid length */
1093 axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1094 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1098 axe_rxeof(ue, pc, 0, actlen, NULL);
1101 ue->ue_ifp->if_ierrors++;
1106 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1107 unsigned int len, struct axe_csum_hdr *csum_hdr)
1109 struct ifnet *ifp = ue->ue_ifp;
1112 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1117 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1122 m->m_len = m->m_pkthdr.len = MCLBYTES;
1123 m_adj(m, ETHER_ALIGN);
1125 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1128 m->m_pkthdr.rcvif = ifp;
1129 m->m_pkthdr.len = m->m_len = len;
1131 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1132 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1133 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1134 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1136 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1137 AXE_CSUM_HDR_L4_TYPE_TCP ||
1138 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1139 AXE_CSUM_HDR_L4_TYPE_UDP) {
1140 m->m_pkthdr.csum_flags |=
1141 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1142 m->m_pkthdr.csum_data = 0xffff;
1147 _IF_ENQUEUE(&ue->ue_rxq, m);
1151 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1152 #error "Please update axe_bulk_write_callback()!"
1156 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1158 struct axe_softc *sc = usbd_xfer_softc(xfer);
1159 struct axe_sframe_hdr hdr;
1160 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1161 struct usb_page_cache *pc;
1165 switch (USB_GET_STATE(xfer)) {
1166 case USB_ST_TRANSFERRED:
1167 DPRINTFN(11, "transfer complete\n");
1168 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1172 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1173 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
1175 * Don't send anything if there is no link or
1176 * controller is busy.
1181 for (nframes = 0; nframes < 16 &&
1182 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
1183 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1186 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1189 pc = usbd_xfer_get_frame(xfer, nframes);
1190 if (AXE_IS_178_FAMILY(sc)) {
1191 hdr.len = htole16(m->m_pkthdr.len);
1192 hdr.ilen = ~hdr.len;
1194 * If upper stack computed checksum, driver
1195 * should tell controller not to insert
1196 * computed checksum for checksum offloading
1197 * enabled controller.
1199 if (ifp->if_capabilities & IFCAP_TXCSUM) {
1200 if ((m->m_pkthdr.csum_flags &
1201 AXE_CSUM_FEATURES) != 0)
1203 AXE_TX_CSUM_PSEUDO_HDR);
1208 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1210 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1211 pos += m->m_pkthdr.len;
1212 if ((pos % 512) == 0) {
1215 usbd_copy_in(pc, pos, &hdr,
1220 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1221 pos += m->m_pkthdr.len;
1226 * Update TX packet counter here. This is not
1227 * correct way but it seems that there is no way
1228 * to know how many packets are sent at the end
1229 * of transfer because controller combines
1230 * multiple writes into single one if there is
1231 * room in TX buffer of controller.
1236 * if there's a BPF listener, bounce a copy
1237 * of this frame to him:
1243 /* Set frame length. */
1244 usbd_xfer_set_frame_len(xfer, nframes, pos);
1247 usbd_xfer_set_frames(xfer, nframes);
1248 usbd_transfer_submit(xfer);
1249 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1253 default: /* Error */
1254 DPRINTFN(11, "transfer error, %s\n",
1255 usbd_errstr(error));
1258 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1260 if (error != USB_ERR_CANCELLED) {
1261 /* try to clear stall first */
1262 usbd_xfer_set_stall(xfer);
1271 axe_tick(struct usb_ether *ue)
1273 struct axe_softc *sc = uether_getsc(ue);
1274 struct mii_data *mii = GET_MII(sc);
1276 AXE_LOCK_ASSERT(sc, MA_OWNED);
1279 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1280 axe_miibus_statchg(ue->ue_dev);
1281 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1287 axe_start(struct usb_ether *ue)
1289 struct axe_softc *sc = uether_getsc(ue);
1292 * start the USB transfers, if not already started:
1294 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1295 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1299 axe_csum_cfg(struct usb_ether *ue)
1301 struct axe_softc *sc;
1303 uint16_t csum1, csum2;
1305 sc = uether_getsc(ue);
1306 AXE_LOCK_ASSERT(sc, MA_OWNED);
1308 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1309 ifp = uether_getifp(ue);
1312 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1313 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1315 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1318 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1319 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1320 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1322 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1327 axe_init(struct usb_ether *ue)
1329 struct axe_softc *sc = uether_getsc(ue);
1330 struct ifnet *ifp = uether_getifp(ue);
1333 AXE_LOCK_ASSERT(sc, MA_OWNED);
1335 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1338 /* Cancel pending I/O */
1343 /* Set MAC address and transmitter IPG values. */
1344 if (AXE_IS_178_FAMILY(sc)) {
1345 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1346 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1347 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1349 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1350 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1351 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1352 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1355 if (AXE_IS_178_FAMILY(sc)) {
1356 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1357 if ((sc->sc_flags & AXE_FLAG_772B) != 0)
1358 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1360 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1361 if ((sc->sc_flags & AXE_FLAG_772B) != 0 &&
1362 (ifp->if_capenable & IFCAP_RXCSUM) != 0)
1363 sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1365 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1368 /* Configure TX/RX checksum offloading. */
1371 if (sc->sc_flags & AXE_FLAG_772B) {
1372 /* AX88772B uses different maximum frame burst configuration. */
1373 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1374 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1375 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1378 /* Enable receiver, set RX mode. */
1379 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1380 if (AXE_IS_178_FAMILY(sc)) {
1381 if (sc->sc_flags & AXE_FLAG_772B) {
1383 * Select RX header format type 1. Aligning IP
1384 * header on 4 byte boundary is not needed when
1385 * checksum offloading feature is not used
1386 * because we always copy the received frame in
1387 * RX handler. When RX checksum offloading is
1388 * active, aligning IP header is required to
1389 * reflect actual frame length including RX
1392 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1393 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1394 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1397 * Default Rx buffer size is too small to get
1398 * maximum performance.
1400 rxmode |= AXE_178_RXCMD_MFB_16384;
1403 rxmode |= AXE_172_RXCMD_UNICAST;
1406 /* If we want promiscuous mode, set the allframes bit. */
1407 if (ifp->if_flags & IFF_PROMISC)
1408 rxmode |= AXE_RXCMD_PROMISC;
1410 if (ifp->if_flags & IFF_BROADCAST)
1411 rxmode |= AXE_RXCMD_BROADCAST;
1413 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1415 /* Load the multicast filter. */
1418 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1420 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1421 /* Switch to selected media. */
1422 axe_ifmedia_upd(ifp);
1426 axe_setpromisc(struct usb_ether *ue)
1428 struct axe_softc *sc = uether_getsc(ue);
1429 struct ifnet *ifp = uether_getifp(ue);
1432 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1434 rxmode = le16toh(rxmode);
1436 if (ifp->if_flags & IFF_PROMISC) {
1437 rxmode |= AXE_RXCMD_PROMISC;
1439 rxmode &= ~AXE_RXCMD_PROMISC;
1442 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1448 axe_stop(struct usb_ether *ue)
1450 struct axe_softc *sc = uether_getsc(ue);
1451 struct ifnet *ifp = uether_getifp(ue);
1453 AXE_LOCK_ASSERT(sc, MA_OWNED);
1455 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1456 sc->sc_flags &= ~AXE_FLAG_LINK;
1459 * stop all the transfers, if not already stopped:
1461 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1462 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1466 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1468 struct usb_ether *ue = ifp->if_softc;
1469 struct axe_softc *sc;
1471 int error, mask, reinit;
1473 sc = uether_getsc(ue);
1474 ifr = (struct ifreq *)data;
1477 if (cmd == SIOCSIFCAP) {
1479 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1480 if ((mask & IFCAP_TXCSUM) != 0 &&
1481 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1482 ifp->if_capenable ^= IFCAP_TXCSUM;
1483 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1484 ifp->if_hwassist |= AXE_CSUM_FEATURES;
1486 ifp->if_hwassist &= ~AXE_CSUM_FEATURES;
1489 if ((mask & IFCAP_RXCSUM) != 0 &&
1490 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1491 ifp->if_capenable ^= IFCAP_RXCSUM;
1494 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
1495 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1502 error = uether_ioctl(ifp, cmd, data);