1 /* $NetBSD: ohcireg.h,v 1.17 2000/04/01 09:27:35 augustss Exp $ */
6 * Copyright (c) 1998 The NetBSD Foundation, Inc.
9 * This code is derived from software contributed to The NetBSD Foundation
10 * by Lennart Augustsson (lennart@augustsson.net) at
11 * Carlstedt Research & Technology.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the NetBSD
24 * Foundation, Inc. and its contributors.
25 * 4. Neither the name of The NetBSD Foundation nor the names of its
26 * contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
42 #ifndef _DEV_PCI_OHCIREG_H_
43 #define _DEV_PCI_OHCIREG_H_
45 /*** PCI config registers ***/
47 #define PCI_CBMEM 0x10 /* configuration base memory */
49 #define PCI_INTERFACE_OHCI 0x10
51 /*** OHCI registers */
53 #define OHCI_REVISION 0x00 /* OHCI revision # */
54 #define OHCI_REV_LO(rev) ((rev)&0xf)
55 #define OHCI_REV_HI(rev) (((rev)>>4)&0xf)
56 #define OHCI_REV_LEGACY(rev) ((rev) & 0x100)
58 #define OHCI_CONTROL 0x04
59 #define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */
60 #define OHCI_RATIO_1_1 0x00000000
61 #define OHCI_RATIO_1_2 0x00000001
62 #define OHCI_RATIO_1_3 0x00000002
63 #define OHCI_RATIO_1_4 0x00000003
64 #define OHCI_PLE 0x00000004 /* Periodic List Enable */
65 #define OHCI_IE 0x00000008 /* Isochronous Enable */
66 #define OHCI_CLE 0x00000010 /* Control List Enable */
67 #define OHCI_BLE 0x00000020 /* Bulk List Enable */
68 #define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalState */
69 #define OHCI_HCFS_RESET 0x00000000
70 #define OHCI_HCFS_RESUME 0x00000040
71 #define OHCI_HCFS_OPERATIONAL 0x00000080
72 #define OHCI_HCFS_SUSPEND 0x000000c0
73 #define OHCI_IR 0x00000100 /* Interrupt Routing */
74 #define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */
75 #define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */
76 #define OHCI_COMMAND_STATUS 0x08
77 #define OHCI_HCR 0x00000001 /* Host Controller Reset */
78 #define OHCI_CLF 0x00000002 /* Control List Filled */
79 #define OHCI_BLF 0x00000004 /* Bulk List Filled */
80 #define OHCI_OCR 0x00000008 /* Ownership Change Request */
81 #define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */
82 #define OHCI_INTERRUPT_STATUS 0x0c
83 #define OHCI_SO 0x00000001 /* Scheduling Overrun */
84 #define OHCI_WDH 0x00000002 /* Writeback Done Head */
85 #define OHCI_SF 0x00000004 /* Start of Frame */
86 #define OHCI_RD 0x00000008 /* Resume Detected */
87 #define OHCI_UE 0x00000010 /* Unrecoverable Error */
88 #define OHCI_FNO 0x00000020 /* Frame Number Overflow */
89 #define OHCI_RHSC 0x00000040 /* Root Hub Status Change */
90 #define OHCI_OC 0x40000000 /* Ownership Change */
91 #define OHCI_MIE 0x80000000 /* Master Interrupt Enable */
92 #define OHCI_INTERRUPT_ENABLE 0x10
93 #define OHCI_INTERRUPT_DISABLE 0x14
94 #define OHCI_HCCA 0x18
95 #define OHCI_PERIOD_CURRENT_ED 0x1c
96 #define OHCI_CONTROL_HEAD_ED 0x20
97 #define OHCI_CONTROL_CURRENT_ED 0x24
98 #define OHCI_BULK_HEAD_ED 0x28
99 #define OHCI_BULK_CURRENT_ED 0x2c
100 #define OHCI_DONE_HEAD 0x30
101 #define OHCI_FM_INTERVAL 0x34
102 #define OHCI_GET_IVAL(s) ((s) & 0x3fff)
103 #define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff)
104 #define OHCI_FIT 0x80000000
105 #define OHCI_FM_REMAINING 0x38
106 #define OHCI_FM_NUMBER 0x3c
107 #define OHCI_PERIODIC_START 0x40
108 #define OHCI_LS_THRESHOLD 0x44
109 #define OHCI_RH_DESCRIPTOR_A 0x48
110 #define OHCI_GET_NDP(s) ((s) & 0xff)
111 #define OHCI_PSM 0x0100 /* Power Switching Mode */
112 #define OHCI_NPS 0x0200 /* No Power Switching */
113 #define OHCI_DT 0x0400 /* Device Type */
114 #define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */
115 #define OHCI_NOCP 0x1000 /* No Overcurrent Protection */
116 #define OHCI_GET_POTPGT(s) ((s) >> 24)
117 #define OHCI_RH_DESCRIPTOR_B 0x4c
118 #define OHCI_RH_STATUS 0x50
119 #define OHCI_LPS 0x00000001 /* Local Power Status */
120 #define OHCI_OCI 0x00000002 /* OverCurrent Indicator */
121 #define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */
122 #define OHCI_LPSC 0x00010000 /* Local Power Status Change */
123 #define OHCI_CCIC 0x00020000 /* OverCurrent Indicator Change */
124 #define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */
125 #define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */
127 #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
128 #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \
129 OHCI_FNO | OHCI_RHSC | OHCI_OC)
130 #define OHCI_NORMAL_INTRS (OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
132 #define OHCI_FSMPS(i) (((i-210)*6/7) << 16)
133 #define OHCI_PERIODIC(i) ((i)*9/10)
135 typedef u_int32_t ohci_physaddr_t;
137 #define OHCI_NO_INTRS 32
139 ohci_physaddr_t hcca_interrupt_table[OHCI_NO_INTRS];
140 u_int32_t hcca_frame_number;
141 ohci_physaddr_t hcca_done_head;
142 #define OHCI_DONE_INTRS 1
144 #define OHCI_HCCA_SIZE 256
145 #define OHCI_HCCA_ALIGN 256
147 #define OHCI_PAGE_SIZE 0x1000
148 #define OHCI_PAGE(x) ((x) &~ 0xfff)
149 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
150 #define OHCI_PAGE_MASK(x) ((x) & 0xfff)
154 #define OHCI_ED_GET_FA(s) ((s) & 0x7f)
155 #define OHCI_ED_ADDRMASK 0x0000007f
156 #define OHCI_ED_SET_FA(s) (s)
157 #define OHCI_ED_GET_EN(s) (((s) >> 7) & 0xf)
158 #define OHCI_ED_SET_EN(s) ((s) << 7)
159 #define OHCI_ED_DIR_MASK 0x00001800
160 #define OHCI_ED_DIR_TD 0x00000000
161 #define OHCI_ED_DIR_OUT 0x00000800
162 #define OHCI_ED_DIR_IN 0x00001000
163 #define OHCI_ED_SPEED 0x00002000
164 #define OHCI_ED_SKIP 0x00004000
165 #define OHCI_ED_FORMAT_GEN 0x00000000
166 #define OHCI_ED_FORMAT_ISO 0x00008000
167 #define OHCI_ED_GET_MAXP(s) (((s) >> 16) & 0x07ff)
168 #define OHCI_ED_SET_MAXP(s) ((s) << 16)
169 #define OHCI_ED_MAXPMASK (0x7ff << 16)
170 ohci_physaddr_t ed_tailp;
171 ohci_physaddr_t ed_headp;
172 #define OHCI_HALTED 0x00000001
173 #define OHCI_TOGGLECARRY 0x00000002
174 #define OHCI_HEADMASK 0xfffffffc
175 ohci_physaddr_t ed_nexted;
177 /* #define OHCI_ED_SIZE 16 */
178 #define OHCI_ED_ALIGN 16
182 #define OHCI_TD_R 0x00040000 /* Buffer Rounding */
183 #define OHCI_TD_DP_MASK 0x00180000 /* Direction / PID */
184 #define OHCI_TD_SETUP 0x00000000
185 #define OHCI_TD_OUT 0x00080000
186 #define OHCI_TD_IN 0x00100000
187 #define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */
188 #define OHCI_TD_SET_DI(x) ((x) << 21)
189 #define OHCI_TD_NOINTR 0x00e00000
190 #define OHCI_TD_INTR_MASK 0x00e00000
191 #define OHCI_TD_TOGGLE_CARRY 0x00000000
192 #define OHCI_TD_TOGGLE_0 0x02000000
193 #define OHCI_TD_TOGGLE_1 0x03000000
194 #define OHCI_TD_TOGGLE_MASK 0x03000000
195 #define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) /* Error Count */
196 #define OHCI_TD_GET_CC(x) ((x) >> 28) /* Condition Code */
197 #define OHCI_TD_NOCC 0xf0000000
198 ohci_physaddr_t td_cbp; /* Current Buffer Pointer */
199 ohci_physaddr_t td_nexttd; /* Next TD */
200 ohci_physaddr_t td_be; /* Buffer End */
202 /* #define OHCI_TD_SIZE 16 */
203 #define OHCI_TD_ALIGN 16
205 #define OHCI_ITD_NOFFSET 8
208 #define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff)
209 #define OHCI_ITD_SET_SF(x) ((x) & 0xffff)
210 #define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */
211 #define OHCI_ITD_SET_DI(x) ((x) << 21)
212 #define OHCI_ITD_NOINTR 0x00e00000
213 #define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) /* Frame Count */
214 #define OHCI_ITD_SET_FC(x) (((x)-1) << 24)
215 #define OHCI_ITD_GET_CC(x) ((x) >> 28) /* Condition Code */
216 #define OHCI_ITD_NOCC 0xf0000000
217 ohci_physaddr_t itd_bp0; /* Buffer Page 0 */
218 ohci_physaddr_t itd_nextitd; /* Next ITD */
219 ohci_physaddr_t itd_be; /* Buffer End */
220 u_int16_t itd_offset[OHCI_ITD_NOFFSET]; /* Buffer offsets */
221 #define itd_pswn itd_offset /* Packet Status Word*/
222 #define OHCI_ITD_PAGE_SELECT 0x00001000
223 #define OHCI_ITD_MK_OFFS(page, off) \
224 (0xe000 | ((page) ? OHCI_ITD_PAGE_SELECT : 0) | ((off) & 0xfff))
225 #define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) /* Transfer length */
226 #define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) /* Condition Code */
228 /* #define OHCI_ITD_SIZE 32 */
229 #define OHCI_ITD_ALIGN 32
232 #define OHCI_CC_NO_ERROR 0
233 #define OHCI_CC_CRC 1
234 #define OHCI_CC_BIT_STUFFING 2
235 #define OHCI_CC_DATA_TOGGLE_MISMATCH 3
236 #define OHCI_CC_STALL 4
237 #define OHCI_CC_DEVICE_NOT_RESPONDING 5
238 #define OHCI_CC_PID_CHECK_FAILURE 6
239 #define OHCI_CC_UNEXPECTED_PID 7
240 #define OHCI_CC_DATA_OVERRUN 8
241 #define OHCI_CC_DATA_UNDERRUN 9
242 #define OHCI_CC_BUFFER_OVERRUN 12
243 #define OHCI_CC_BUFFER_UNDERRUN 13
244 #define OHCI_CC_NOT_ACCESSED 15
246 /* Some delay needed when changing certain registers. */
247 #define OHCI_ENABLE_POWER_DELAY 5
248 #define OHCI_READ_DESC_DELAY 5
250 #endif /* _DEV_PCI_OHCIREG_H_ */