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33 #ifndef VXGE_HAL_CONFIG_H
34 #define VXGE_HAL_CONFIG_H
38 #define VXGE_HAL_USE_FLASH_DEFAULT VXGE_HAL_DEFAULT_32
40 #define VXGE_HAL_MAX_INTR_PER_VP 4
42 #define VXGE_HAL_VPATH_MSIX_MAX 4
44 #define VXGE_HAL_VPATH_INTR_TX 0
46 #define VXGE_HAL_VPATH_INTR_RX 1
48 #define VXGE_HAL_VPATH_INTR_EINTA 2
50 #define VXGE_HAL_VPATH_INTR_BMAP 3
54 * struct vxge_hal_driver_config_t - HAL driver object configuration.
56 * @level: Debug Level. See vxge_debug_level_e {}
58 * Currently this structure contains just a few basic values.
60 typedef struct vxge_hal_driver_config_t {
61 vxge_debug_level_e level;
62 } vxge_hal_driver_config_t;
65 * struct vxge_hal_wire_port_config_t - Wire Port configuration (Physical ports)
66 * @port_id: Port number
67 * @media: Transponder type.
68 * @mtu: mtu size used on this port.
69 * @autoneg_mode: The device supports several mechanisms to auto-negotiate the
70 * port data rate. The Fixed mode essentially means no
71 * auto-negotiation and the data rate is determined by the RATE
72 * field of this register. The MDIO-based mode determines the data
73 * rate by reading MDIO registers in the external PHY chip. The
74 * Backplane Ethernet mode using parallel detect and/or
75 * DME-signaled exchange of page information with the PHY chip in
76 * order to figure out the proper rate.
79 * 10 - Backplane Ethernet
81 * @autoneg_rate: When MODE is set to Fixed, then this field determines the data
85 * @fixed_use_fsm: When MODE is set to Fixed, then this field determines whether
86 * a processor (i.e. F/W or host driver) or hardware-based state
87 * machine is used to run the auto-negotiation.
88 * 0 - Use processor. Either on-chip F/W or host-based driver used.
89 * 1 - Use H/W state machine
90 * @antp_use_fsm: When MODE is set to ANTP (Auto-Negotiation for Twisted Pair),
91 * this field determines whether a processor (F/W or host driver)
92 * or hardware-based state machine is used to talk to the PHY chip
93 * via the MDIO interface.
94 * 0 - Use processor. Either on-chip F/W or host-based driver used.
95 * 1 - Use H/W state machine
96 * @anbe_use_fsm: When MODE is set to ANBE-based, then this field determines
97 * whether a processor (i.e. F/W or host driver) or hardware-based
98 * state machine is used to talk to the Backplane Ethernet logic
100 * 0 - Use processor. Either on-chip F/W or host-based driver used.
101 * 1 - Use H/W state machine
102 * @link_stability_period: Timeout for the link stability
103 * @port_stability_period: Timeout for the port stability
104 * @tmac_en: TMAC enable. 0 - Disable; 1 - Enable
105 * @rmac_en: RMAC enable. 0 - Disable; 1 - Enable
106 * @tmac_pad: Determines whether padding is appended to transmitted frames.
107 * 0 - No padding appended
108 * 1 - Pad to 64 bytes (not including preamble/SFD)
109 * @tmac_pad_byte: The byte that is used to pad
110 * @tmac_util_period: The sampling period over which the transmit utilization
112 * @rmac_strip_fcs: Determines whether FCS of received frames is removed by the
113 * MAC or sent to the host.
114 * 0 - Send FCS to host.
115 * 1 - FCS removed by MAC.
116 * @rmac_prom_en: Enable/Disable promiscuous mode. In promiscuous mode all
117 * received frames are passed to the host. PROM_EN overrules the
118 * configuration determined by the UCAST_ALL_ADDR_EN,
119 * MCAST_ALL_ADDR_EN and ALL_VID_EN fields of RXMAC_VCFG, as well
120 * as the configurable discard fields in RMAC_ERR_CFG_PORTn.
121 * Note: PROM_EN does not overrule DISCARD_PFRM (i.e. discard of
122 * pause frames by receive MAC is controlled solely by
126 * @rmac_discard_pfrm: Determines whether received pause frames are discarded at
127 * the receive MAC or passed to the host.
128 * Note: Other MAC control frames are always passed to the host.
130 * 1 - Pause frames discarded by MAC.
131 * @rmac_util_period: The sampling period over which the receive utilization
133 * @rmac_strip_pad: Determines whether padding of received frames is removed by
134 * the MAC or sent to the host.
135 * @rmac_bcast_en: Enable frames containing broadcast address to be
136 * passed to the host.
137 * @rmac_pause_gen_en: Received pause generation enable.
138 * @rmac_pause_rcv_en: Receive pause enable.
139 * @rmac_pause_time: The value to be inserted in outgoing pause frames.
140 * Has units of pause quanta (one pause quanta = 512 bit times).
141 * @limiter_en: Enables logic that limits the contribution that any one receive
142 * queue can have on the transmission of pause frames. This avoids
143 * a situation where the adapter will permanently send pause frames
144 * due to a receive VPATH that is either undergoing a long reset or
145 * is in a dead state.
146 * 0 - Don't limit the contribution of any queue. If any queue's
147 * fill level sits above the high threshold, then a pause frame
149 * 1 - Place a cap on the number of pause frames that are sent
150 * because any one queue has crossed its high threshold.
151 * See MAX_LIMIT for more details.
152 * @max_limit: Contains the value that is loaded into the per-queue limiting
153 * counters that exist in the flow control logic. Essentially,
154 * this represents the maximum number of pause frames that are sent
155 * due to any one particular queue having crossed its high
156 * threshold. Each counter is set to this max limit the first time
157 * the corresponding queue's high threshold is crossed. The counter
158 * decrements each time the queue remains above the high threshold
159 * and the adapter requests pause frame transmission. Once the
160 * counter expires that queue no longer contributes to pause frame
161 * transmission requests. The queue's fill level must drop below
162 * the low pause threshold before it is once again allowed to
163 * contribute. Note: This field is only used when LIMITER_EN is set
166 * Wire Port Configuration
168 typedef struct vxge_hal_wire_port_config_t {
171 #define VXGE_HAL_WIRE_PORT_PORT0 0
172 #define VXGE_HAL_WIRE_PORT_PORT1 1
173 #define VXGE_HAL_WIRE_PORT_MAX_PORTS VXGE_HAL_MAC_MAX_WIRE_PORTS
176 #define VXGE_HAL_WIRE_PORT_MIN_MEDIA 0
177 #define VXGE_HAL_WIRE_PORT_MEDIA_SR 0
178 #define VXGE_HAL_WIRE_PORT_MEDIA_SW 1
179 #define VXGE_HAL_WIRE_PORT_MEDIA_LR 2
180 #define VXGE_HAL_WIRE_PORT_MEDIA_LW 3
181 #define VXGE_HAL_WIRE_PORT_MEDIA_ER 4
182 #define VXGE_HAL_WIRE_PORT_MEDIA_EW 5
183 #define VXGE_HAL_WIRE_PORT_MAX_MEDIA 5
184 #define VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
187 #define VXGE_HAL_WIRE_PORT_MIN_INITIAL_MTU VXGE_HAL_MIN_MTU
188 #define VXGE_HAL_WIRE_PORT_MAX_INITIAL_MTU VXGE_HAL_MAX_MTU
189 #define VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU VXGE_HAL_USE_FLASH_DEFAULT
192 #define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_FIXED 0
193 #define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_ANTP 1
194 #define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_ANBE 2
195 #define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_RESERVED 3
196 #define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
199 #define VXGE_HAL_WIRE_PORT_AUTONEG_RATE_1G 0
200 #define VXGE_HAL_WIRE_PORT_AUTONEG_RATE_10G 1
201 #define VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
204 #define VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_PROCESSOR 0
205 #define VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_HW 1
206 #define VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
209 #define VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_PROCESSOR 0
210 #define VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_HW 1
211 #define VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
214 #define VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_PROCESSOR 0
215 #define VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_HW 1
216 #define VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
218 u32 link_stability_period;
219 #define VXGE_HAL_WIRE_PORT_MIN_LINK_STABILITY_PERIOD 0x0 /* 0s */
220 #define VXGE_HAL_WIRE_PORT_MAX_LINK_STABILITY_PERIOD 0xF /* 2s */
221 #define VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD \
222 VXGE_HAL_USE_FLASH_DEFAULT
224 u32 port_stability_period;
225 #define VXGE_HAL_WIRE_PORT_MIN_PORT_STABILITY_PERIOD 0x0 /* 0s */
226 #define VXGE_HAL_WIRE_PORT_MAX_PORT_STABILITY_PERIOD 0xF /* 2s */
227 #define VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD \
228 VXGE_HAL_USE_FLASH_DEFAULT
231 #define VXGE_HAL_WIRE_PORT_TMAC_ENABLE 1
232 #define VXGE_HAL_WIRE_PORT_TMAC_DISABLE 0
233 #define VXGE_HAL_WIRE_PORT_TMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
236 #define VXGE_HAL_WIRE_PORT_RMAC_ENABLE 1
237 #define VXGE_HAL_WIRE_PORT_RMAC_DISABLE 0
238 #define VXGE_HAL_WIRE_PORT_RMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
241 #define VXGE_HAL_WIRE_PORT_TMAC_NO_PAD 0
242 #define VXGE_HAL_WIRE_PORT_TMAC_64B_PAD 1
243 #define VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
246 #define VXGE_HAL_WIRE_PORT_MIN_TMAC_PAD_BYTE 0
247 #define VXGE_HAL_WIRE_PORT_MAX_TMAC_PAD_BYTE 255
248 #define VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE VXGE_HAL_USE_FLASH_DEFAULT
250 u32 tmac_util_period;
251 #define VXGE_HAL_WIRE_PORT_MIN_TMAC_UTIL_PERIOD 0
252 #define VXGE_HAL_WIRE_PORT_MAX_TMAC_UTIL_PERIOD 15
253 #define VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT
256 #define VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS 1
257 #define VXGE_HAL_WIRE_PORT_RMAC_SEND_FCS_TO_HOST 0
258 #define VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
261 #define VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_ENABLE 1
262 #define VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DISABLE 0
263 #define VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
265 u32 rmac_discard_pfrm;
266 #define VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM 1
267 #define VXGE_HAL_WIRE_PORT_RMAC_SEND_PFRM_TO_HOST 0
268 #define VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT \
269 VXGE_HAL_USE_FLASH_DEFAULT
271 u32 rmac_util_period;
272 #define VXGE_HAL_WIRE_PORT_MIN_RMAC_UTIL_PERIOD 0
273 #define VXGE_HAL_WIRE_PORT_MAX_RMAC_UTIL_PERIOD 15
274 #define VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT
276 u32 rmac_pause_gen_en;
277 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_ENABLE 1
278 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DISABLE 0
279 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT \
280 VXGE_HAL_USE_FLASH_DEFAULT
282 u32 rmac_pause_rcv_en;
283 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_ENABLE 1
284 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DISABLE 0
285 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT \
286 VXGE_HAL_USE_FLASH_DEFAULT
289 #define VXGE_HAL_WIRE_PORT_MIN_RMAC_HIGH_PTIME 16
290 #define VXGE_HAL_WIRE_PORT_MAX_RMAC_HIGH_PTIME 65535
291 #define VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME VXGE_HAL_USE_FLASH_DEFAULT
294 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_ENABLE 1
295 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DISABLE 0
296 #define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT \
297 VXGE_HAL_USE_FLASH_DEFAULT
300 #define VXGE_HAL_WIRE_PORT_MIN_RMAC_MAX_LIMIT 0
301 #define VXGE_HAL_WIRE_PORT_MAX_RMAC_MAX_LIMIT 255
302 #define VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT VXGE_HAL_USE_FLASH_DEFAULT
304 } vxge_hal_wire_port_config_t;
307 * struct vxge_hal_switch_port_config_t - Switch Port configuration(vm-vm port)
308 * @mtu: mtu size used on this port.
309 * @tmac_en: TMAC enable. 0 - Disable; 1 - Enable
310 * @rmac_en: RMAC enable. 0 - Disable; 1 - Enable
311 * @tmac_pad: Determines whether padding is appended to transmitted frames.
312 * 0 - No padding appended
313 * 1 - Pad to 64 bytes (not including preamble/SFD)
314 * @tmac_pad_byte: The byte that is used to pad
315 * @tmac_util_period: The sampling period over which the transmit utilization
317 * @rmac_strip_fcs: Determines whether FCS of received frames is removed by the
318 * MAC or sent to the host.
319 * 0 - Send FCS to host.
320 * 1 - FCS removed by MAC.
321 * @rmac_prom_en: Enable/Disable promiscuous mode. In promiscuous mode all
322 * received frames are passed to the host. PROM_EN overrules the
323 * configuration determined by the UCAST_ALL_ADDR_EN,
324 * MCAST_ALL_ADDR_EN and ALL_VID_EN fields of RXMAC_VCFG, as well
325 * as the configurable discard fields in RMAC_ERR_CFG_PORTn.
326 * Note: PROM_EN does not overrule DISCARD_PFRM (i.e. discard of
327 * pause frames by receive MAC is controlled solely by
331 * @rmac_discard_pfrm: Determines whether received pause frames are discarded at
332 * the receive MAC or passed to the host.
333 * Note: Other MAC control frames are always passed to the host.
335 * 1 - Pause frames discarded by MAC.
336 * @rmac_util_period: The sampling period over which the receive utilization
338 * @rmac_strip_pad: Determines whether padding of received frames is removed by
339 * the MAC or sent to the host.
340 * @rmac_bcast_en: Enable frames containing broadcast address to be
341 * passed to the host.
342 * @rmac_pause_gen_en: Received pause generation enable.
343 * @rmac_pause_rcv_en: Receive pause enable.
344 * @rmac_pause_time: The value to be inserted in outgoing pause frames.
345 * Has units of pause quanta (one pause quanta = 512 bit times).
346 * @limiter_en: Enables logic that limits the contribution that any one receive
347 * queue can have on the transmission of pause frames. This avoids
348 * a situation where the adapter will permanently send pause frames
349 * due to a receive VPATH that is either undergoing a long reset or
350 * is in a dead state.
351 * 0 - Don't limit the contribution of any queue. If any queue's
352 * fill level sits above the high threshold, then a pause frame
354 * 1 - Place a cap on the number of pause frames that are sent
355 * because any one queue has crossed its high threshold.
356 * See MAX_LIMIT for more details.
357 * @max_limit: Contains the value that is loaded into the per-queue limiting
358 * counters that exist in the flow control logic. Essentially,
359 * this represents the maximum number of pause frames that are sent
360 * due to any one particular queue having crossed its high
361 * threshold. Each counter is set to this max limit the first time
362 * the corresponding queue's high threshold is crossed. The counter
363 * decrements each time the queue remains above the high threshold
364 * and the adapter requests pause frame transmission. Once the
365 * counter expires that queue no longer contributes to pause frame
366 * transmission requests. The queue's fill level must drop below
367 * the low pause threshold before it is once again allowed to
368 * contribute. Note: This field is only used when LIMITER_EN is set
371 * Switch Port Configuration
373 typedef struct vxge_hal_switch_port_config_t {
376 #define VXGE_HAL_SWITCH_PORT_MIN_INITIAL_MTU VXGE_HAL_MIN_MTU
377 #define VXGE_HAL_SWITCH_PORT_MAX_INITIAL_MTU VXGE_HAL_MAX_MTU
378 #define VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU VXGE_HAL_USE_FLASH_DEFAULT
381 #define VXGE_HAL_SWITCH_PORT_TMAC_ENABLE 1
382 #define VXGE_HAL_SWITCH_PORT_TMAC_DISABLE 0
383 #define VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
386 #define VXGE_HAL_SWITCH_PORT_RMAC_ENABLE 1
387 #define VXGE_HAL_SWITCH_PORT_RMAC_DISABLE 0
388 #define VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
391 #define VXGE_HAL_SWITCH_PORT_TMAC_NO_PAD 0
392 #define VXGE_HAL_SWITCH_PORT_TMAC_64B_PAD 1
393 #define VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
396 #define VXGE_HAL_SWITCH_PORT_MIN_TMAC_PAD_BYTE 0
397 #define VXGE_HAL_SWITCH_PORT_MAX_TMAC_PAD_BYTE 255
398 #define VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE VXGE_HAL_USE_FLASH_DEFAULT
400 u32 tmac_util_period;
401 #define VXGE_HAL_SWITCH_PORT_MIN_TMAC_UTIL_PERIOD 0
402 #define VXGE_HAL_SWITCH_PORT_MAX_TMAC_UTIL_PERIOD 15
403 #define VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT
406 #define VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS 1
407 #define VXGE_HAL_SWITCH_PORT_RMAC_SEND_FCS_TO_HOST 0
408 #define VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
411 #define VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_ENABLE 1
412 #define VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DISABLE 0
413 #define VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
415 u32 rmac_discard_pfrm;
416 #define VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM 1
417 #define VXGE_HAL_SWITCH_PORT_RMAC_SEND_PFRM_TO_HOST 0
418 #define VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT \
419 VXGE_HAL_USE_FLASH_DEFAULT
421 u32 rmac_util_period;
422 #define VXGE_HAL_SWITCH_PORT_MIN_RMAC_UTIL_PERIOD 0
423 #define VXGE_HAL_SWITCH_PORT_MAX_RMAC_UTIL_PERIOD 15
424 #define VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT
426 u32 rmac_pause_gen_en;
427 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_ENABLE 1
428 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DISABLE 0
429 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT \
430 VXGE_HAL_USE_FLASH_DEFAULT
432 u32 rmac_pause_rcv_en;
433 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_ENABLE 1
434 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DISABLE 0
435 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT \
436 VXGE_HAL_USE_FLASH_DEFAULT
439 #define VXGE_HAL_SWITCH_PORT_MIN_RMAC_HIGH_PTIME 16
440 #define VXGE_HAL_SWITCH_PORT_MAX_RMAC_HIGH_PTIME 65535
441 #define VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME VXGE_HAL_USE_FLASH_DEFAULT
444 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_ENABLE 1
445 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DISABLE 0
446 #define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT \
447 VXGE_HAL_USE_FLASH_DEFAULT
450 #define VXGE_HAL_SWITCH_PORT_MIN_RMAC_MAX_LIMIT 0
451 #define VXGE_HAL_SWITCH_PORT_MAX_RMAC_MAX_LIMIT 255
452 #define VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT VXGE_HAL_USE_FLASH_DEFAULT
454 } vxge_hal_switch_port_config_t;
457 * struct vxge_hal_mac_config_t - MAC configuration (Physical ports).
458 * @wire_port_config: Wire Port configuration
459 * @switch_port_config: Switch Port configuration
460 * @network_stability_period: The wait period for network stability
461 * @mc_pause_threshold: Contains thresholds for pause frame generation
462 * for queues 0 through 15. The threshold value indicates portion
463 * of the individual receive buffer queue size. Thresholds have a
464 * range of 0 to 255, allowing 256 possible watermarks in a queue.
465 * @tmac_perma_stop_en: Controls TMAC reaction to double ECC errors on its
467 * 0 - Disable TMAC permanent stop
468 * 1 - Enable TMAC permanent stop whenever double ECC errors are
469 * detected on the internal transmit SRAMs.
470 * @tmac_tx_switch_dis: Allows the user to disable the switching of transmit
471 * frames back to the receive path.
472 * 0 - Tx frames are switched based on the result of the DA lookup
473 * 1 - The DA lookup result is ignored and all traffic is sent to
475 * Note that this register field does not impact the multicast
476 * replication on the receive side.
477 * @tmac_lossy_switch_en: Controls the behaviour of the internal Tx to Rx switch
478 * in the event of back-pressure on the receive path due to
479 * priority given to traffic arriving off the wire or simply due to
480 * a full receive external buffer. br>
481 * 0 - No frames are dropped on the switch path. Instead, in the
482 * event of back-pressure, the transmit path is backed up.
483 * 1 - Whenever back-pressure is present and the next frame is
484 * bound for the switch path, then the frame is dropped.
485 * If it is also destined for the transmit wire, it is still
487 * Note: HIP traffic that is bound for the switch path is never
488 * dropped - the transmit path is forced to backup.
489 * @tmac_lossy_wire_en: Controls the behaviour of the TMAC when the wire path
490 * is unavailable. This occurs when the target wire port is down.
491 * 0 - No frames are dropped on the wire path. Instead,in the event
492 * of port failure, the transmit path is backed up.
493 * 1 - Whenever a wire port is down and the next frame is bound for
494 * that port, then the frame is dropped. If it is also destined
495 * for the switch path, it is still sent there.
496 * @tmac_bcast_to_wire_dis: Suppresses the transmission of broadcast frames to
498 * 0 - Transmit broadcast frames are sent out the wire and also
499 * sent along the switch path.
500 * 1 - Transmit broadcast frame are only sent along the switch path
501 * @tmac_bcast_to_switch_dis: Suppresses the transmission of broadcast frames
502 * along the switch path.
503 * 0 - Transmit broadcast frames are sent out the wire and also
504 * sent along the switch path.
505 * 1 - Transmit broadcast frame are only sent out the wire.
506 * @tmac_host_append_fcs_en: Suppresses the H/W from appending the FCS to the
507 * end of transmitted frames. The host is responsible for tacking
508 * on the 4-byte FCS at the end of the frame.
509 * 0 - Normal operation. H/W appends FCS to all transmitted frames.
510 * 1 - Host appends FCS to frame. Transmit MAC passes it through
511 * @tpa_support_snap_ab_n: When set to 0, the TPA will accept LLC-SAP values of
512 * 0xAB as valid. If set to 1, the TPA rejects LLC-SAP values of
513 * 0xAB (only 0xAA is accepted).
514 * @tpa_ecc_enable_n: Allows ECC protection of TPA internal memories to be
515 * disabled without having to disable ECC protection for entire
517 * 0 - Disable TPA ECC protection
518 * 1 - Enable TPA ECC protection.
519 * Note: If chip-wide ECC protection is disabled, then so is TPA
521 * @rpa_ignore_frame_err: Ignore Frame Error. The RPA may detect frame integrity
522 * errors as it processes each received frame. If this bit is set
523 * to '0', the RPA will tag such frames as "errored" in the RxDMA
524 * descriptor. If the bit is set to '1', the frame will not be
525 * tagged as "errored".
526 * Detectable errors include:
527 * 1) early end-of-frame error, which occurs when the frame ends
528 * before the number of bytes predicted by the IP "total length"
529 * field have been received;
530 * 2) IP version mismatches;
531 * 3) IPv6 packets that include routing headers that are not type 0
532 * 4) Frames which contain IP packets but have an illegal SNAP-OUI
533 * or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL
535 * @rpa_support_snap_ab_n: When set to 0, the RPA will accept LLC-SAP values of
536 * 0xAB as valid. If set to 1, the RPA rejects LLC-SAP values of
537 * 0xAB (only 0xAA is accepted).
538 * @rpa_search_for_hao: Enable searching for the Home Address Option.If this bit
539 * is set, the RPA will parse through Destination Address Headers
540 * searching for the H.A.O. If the bit is not set, the RPA will not
541 * perform a search and these headers will effectively be ignored.
542 * @rpa_support_ipv6_mobile_hdrs: Enable/disable support for the mobile-ipv6
543 * Home Address Option (HAO) and Route 2 Routing Headers,as defined
545 * 0 - Do not support mobile IPv6.
546 * 1 - Support mobile IPv6
547 * @rpa_ipv6_stop_searching: Enable/disable unknown IPv6 extension header
548 * parsing. If the adapter discovers an unknown extension header,
549 * it can either continue to search for a L4 protocol, or stop
551 * 0 - do not stop searching for L4 when an unknown header is
553 * 1 - stop searching when an unknown header is encountered.
554 * @rpa_no_ps_if_unknown: Enable/disable pseudo-header inclusion if an unknown
555 * IPv6 extension header is encountered.
556 * If this bit is set to '1' and an unknown routing header or IPv6
557 * extension header is discovered, the L4 checksum will not include
559 * If it is set to '0', the adapter will use the addresses found
560 * in the IPv6 base header, and/or the addresses found in a Routing
561 * Header or Home Address Option (if it is enabled).
562 * This applies to frames not on LRO sessions only. For frames on
563 * LRO sessions, the pseudo-header is always included in the L4
565 * @rpa_search_for_etype: For receive traffic steering purposes, indicates
566 * whether the RPA should parse through the LLC header to find the
567 * Ethertype of the packet.
568 * 0 - RPA presents the 802.3 length/type field, which for an
569 * LLC-encoded frame is interpreted as a length.
570 * 1 - RPA parses the LLC-header and presents the Ethertype to the
571 * traffic steering logic. When SEARCH_FOR_ETYPE is set and a jumbo
572 * snap frame is received then GLOBAL_PA_CFG.EN_JS determines the
573 * value that is presented to the traffic steering logic. If EN_JS
574 * is set, then the RPA parses inside the header to find the
575 * Ethertype, while if EN_JS is not set the RPA presents 0x8870.
576 * @rpa_repl_l4_comp_csum: Controls whether or not to complement the L4 checksum
577 * after the final calculation.
578 * 0: Do not complement the L4 checksum.
579 * 1: Complement the L4 checksum.
580 * For the behaviour on non-replicated frames see FAU_RPA_VCFG.
581 * @rpa_repl_l3_incl_cf: Controls whether or not to include the L3 checksum
582 * field in the checksum calculation.
583 * 0: Do not include the L3 checksum field in checksum calculation
584 * 1: Include the L4 checksum field in the checksum calculation.
585 * For the behaviour on non-replicated frames see FAU_RPA_VCFG.
586 * @rpa_repl_l3_comp_csum: Controls whether or not to complement the L3 checksum
587 * after the final calculation.
588 * 0: Do not complement the L3 checksum.
589 * 1: Complement the L3 checksum.
590 * For the behaviour on non-replicated frames see FAU_RPA_VCFG.
591 * @rpa_repl_ipv4_tcp_incl_ph: For received frames that are replicated at the
592 * internal L2 switch, determines whether the pseudo-header is
593 * included in the calculation of the L4 checksum that is passed to
595 * @rpa_repl_ipv6_tcp_incl_ph: For received frames that are replicated at the
596 * internal L2 switch, determines whether the pseudo-header is
597 * included in the calculation of the L4 checksum that is passed to
599 * @rpa_repl_ipv4_udp_incl_ph: For received frames that are replicated at the
600 * internal L2 switch, determines whether the pseudo-header is
601 * included in the calculation of the L4 checksum that is passed to
603 * @rpa_repl_ipv6_udp_incl_ph: For received frames that are replicated at the
604 * internal L2 switch, determines whether the pseudo-header is
605 * included in the calculation of the L4 checksum that is passed to
607 * @rpa_repl_l4_incl_cf: For received frames that are replicated at the internal
608 * L2 switch, determines whether the checksum field (CF) of the
609 * received frame is included in the calculation of the L4
610 * checksum that is passed to the host.
611 * @rpa_repl_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device
612 * to remove the VLAN tag from all received tagged frames that
613 * are replicated at the internal L2 switch (i.e. multicast frames
614 * that are placed in the replication queue).
615 * 0 - Do not strip the VLAN tag.
616 * 1 - Strip the VLAN tag.
617 * Regardless of this setting, VLAN tags are always placed into
618 * the RxDMA descriptor.
620 * MAC configuration. This includes various aspects of configuration, including:
621 * - Pause frame threshold;
622 * - sampling rate to calculate link utilization;
623 * - enabling/disabling broadcasts.
625 * See X3100 ER User Guide for more details.
626 * Note: Valid (min, max) range for each attribute is specified in the body of
627 * the vxge_hal_mac_config_t {} structure. Please refer to the
628 * corresponding include file.
630 typedef struct vxge_hal_mac_config_t {
632 vxge_hal_wire_port_config_t wire_port_config[ \
633 VXGE_HAL_MAC_MAX_WIRE_PORTS];
634 vxge_hal_switch_port_config_t switch_port_config;
636 u32 network_stability_period;
637 #define VXGE_HAL_MAC_MIN_NETWORK_STABILITY_PERIOD 0x0 /* 0s */
638 #define VXGE_HAL_MAC_MAX_NETWORK_STABILITY_PERIOD 0x7 /* 2s */
639 #define VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD VXGE_HAL_USE_FLASH_DEFAULT
641 u32 mc_pause_threshold[16];
642 #define VXGE_HAL_MAC_MIN_MC_PAUSE_THRESHOLD 0
643 #define VXGE_HAL_MAC_MAX_MC_PAUSE_THRESHOLD 254
644 #define VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD VXGE_HAL_USE_FLASH_DEFAULT
646 u32 tmac_perma_stop_en;
647 #define VXGE_HAL_MAC_TMAC_PERMA_STOP_ENABLE 1
648 #define VXGE_HAL_MAC_TMAC_PERMA_STOP_DISABLE 0
649 #define VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
651 u32 tmac_tx_switch_dis;
652 #define VXGE_HAL_MAC_TMAC_TX_SWITCH_ENABLE 0
653 #define VXGE_HAL_MAC_TMAC_TX_SWITCH_DISABLE 1
654 #define VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
656 u32 tmac_lossy_switch_en;
657 #define VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_ENABLE 1
658 #define VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DISABLE 0
659 #define VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
661 u32 tmac_lossy_wire_en;
662 #define VXGE_HAL_MAC_TMAC_LOSSY_WIRE_ENABLE 1
663 #define VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DISABLE 0
664 #define VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
666 u32 tmac_bcast_to_wire_dis;
667 #define VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DISABLE 1
668 #define VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_ENABLE 0
669 #define VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
671 u32 tmac_bcast_to_switch_dis;
672 #define VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DISABLE 1
673 #define VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_ENABLE 0
674 #define VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
676 u32 tmac_host_append_fcs_en;
677 #define VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_ENABLE 1
678 #define VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DISABLE 0
679 #define VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
681 u32 tpa_support_snap_ab_n;
682 #define VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AB 0
683 #define VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AA 1
684 #define VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
686 u32 tpa_ecc_enable_n;
687 #define VXGE_HAL_MAC_TPA_ECC_ENABLE_N_ENABLE 1
688 #define VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DISABLE 0
689 #define VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
691 u32 rpa_ignore_frame_err;
692 #define VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_ENABLE 1
693 #define VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DISABLE 0
694 #define VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
696 u32 rpa_support_snap_ab_n;
697 #define VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_ENABLE 1
698 #define VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DISABLE 0
699 #define VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
701 u32 rpa_search_for_hao;
702 #define VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_ENABLE 1
703 #define VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DISABLE 0
704 #define VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
706 u32 rpa_support_ipv6_mobile_hdrs;
707 #define VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_ENABLE 1
708 #define VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DISABLE 0
709 #define VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT \
710 VXGE_HAL_USE_FLASH_DEFAULT
712 u32 rpa_ipv6_stop_searching;
713 #define VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING 1
714 #define VXGE_HAL_MAC_RPA_IPV6_DONT_STOP_SEARCHING 0
715 #define VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT \
716 VXGE_HAL_USE_FLASH_DEFAULT
718 u32 rpa_no_ps_if_unknown;
719 #define VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_ENABLE 1
720 #define VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DISABLE 0
721 #define VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
723 u32 rpa_search_for_etype;
724 #define VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_ENABLE 1
725 #define VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DISABLE 0
726 #define VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
728 u32 rpa_repl_l4_comp_csum;
729 #define VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_ENABLE 1
730 #define VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_DISABLE 0
731 #define VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
733 u32 rpa_repl_l3_incl_cf;
734 #define VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_ENABLE 1
735 #define VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DISABLE 0
736 #define VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
738 u32 rpa_repl_l3_comp_csum;
739 #define VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_ENABLE 1
740 #define VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_DISABLE 0
741 #define VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
743 u32 rpa_repl_ipv4_tcp_incl_ph;
744 #define VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_ENABLE 1
745 #define VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DISABLE 0
746 #define VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT \
747 VXGE_HAL_USE_FLASH_DEFAULT
749 u32 rpa_repl_ipv6_tcp_incl_ph;
750 #define VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_ENABLE 1
751 #define VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DISABLE 0
752 #define VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT \
753 VXGE_HAL_USE_FLASH_DEFAULT
755 u32 rpa_repl_ipv4_udp_incl_ph;
756 #define VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_ENABLE 1
757 #define VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DISABLE 0
758 #define VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT \
759 VXGE_HAL_USE_FLASH_DEFAULT
761 u32 rpa_repl_ipv6_udp_incl_ph;
762 #define VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_ENABLE 1
763 #define VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DISABLE 0
764 #define VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT \
765 VXGE_HAL_USE_FLASH_DEFAULT
767 u32 rpa_repl_l4_incl_cf;
768 #define VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_ENABLE 1
769 #define VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DISABLE 0
770 #define VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
772 u32 rpa_repl_strip_vlan_tag;
773 #define VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE 1
774 #define VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE 0
775 #define VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT \
776 VXGE_HAL_USE_FLASH_DEFAULT
778 } vxge_hal_mac_config_t;
781 * struct vxge_hal_lag_port_config_t - LAG Port configuration(For privileged
785 * @lag_en: Enables or disables the port from joining a link aggregation group.
786 * If link aggregation is enabled and this port is disabled, then
787 * this port does not carry traffic (it is not associated with an
788 * Aggregator). Both this bit and port_enabled from the physical
789 * layer logic must be asserted to permit the Receive machine to
790 * move beyond the PORT_DISABLED state.
793 * @discard_slow_proto: Discard received frames that contain the Slow Protocols
794 * Multicast address (IEEE 802.3-2005 Clause 43B) -- Such frames
795 * are used for link aggregation Marker Protocol and for LACP.
798 * @host_chosen_aggr: When the host is running the Link Aggregation Control
799 * algorithm, this field determines which aggregator is attached
800 * to this port. This field is only valid when LAG_LACP_CFG.EN is 0
801 * 0 - Aggregator 0 is attached to this port.
802 * 1 - Aggregator 1 is attached to this port.
803 * @discard_unknown_slow_proto: Discard received frames that contain the Slow
804 * Protocols Multicast address (IEEE 802.3-2005 Clause 43B),
805 * but have an unknown Slow Protocols PDU.
808 * Note: This field is only relevant when DISCARD_SLOW_PROTO
810 * @actor_port_num: The port number assigned to the port. Port Number 0 is
811 * reserved and must not be assigned to any port.
812 * @actor_port_priority: The priority value assigned to the port.
813 * @actor_key_10g: The port's administrative Key when auto-negotiated to 10Gbps
814 * The null (all zeros) Key value is not available for local use.
815 * @actor_key_1g: The port's administrative Key when auto-negotiated to 1Gbps.
816 * The null (all zeros) Key value is not available for local use.
817 * @actor_lacp_activity: Indicates the Activity control value for this port.
820 * @actor_lacp_timeout: Indicates the Timeout control value for this port.
823 * @actor_aggregation: Indicates if the port is a potential candidate for
825 * 0 - Link is Individual
826 * 1 - Link is Aggregateable
827 * @actor_synchronization: Indicates if the port is in sync.
828 * 0 - Link is out of sync; it is in the wrong Aggregation
829 * 1 - Link is in sync (allocated to the correct Link Aggregation
830 * Group, the group is associated with a compatible Aggregator,
831 * and the identity of the Link Aggregation Group is consistent
832 * with the System ID and operational Key information transmitted)
833 * @actor_collecting: Indicates whether collecting of incoming frames is enabled
836 * 1 - Collection is enabled
837 * @actor_distributing: Indicates whether distribution of outgoing frames is
838 * enabled on this port.
839 * 0 - Not distributing
840 * 1 - Distribution is enabled
841 * @actor_defaulted: Indicates whether the Actor's Receive state machine is
842 * using administratively configured information for the Partner.
843 * 0 - The operational Partner info has been received in a LACPDU
844 * 1 - The operation Partner info is using administrative defaults
845 * @actor_expired: Indicates whether the Actor's Receive state machine is in the
847 * 0 - Not in the EXPIRED state
848 * 1 - Is in the EXPIRED state
849 * @partner_sys_pri: The administrative default for the System Priority
850 * component of the System Identifier of the Partner.
851 * @partner_key: The administrative default for the Partner's Key. The null
852 * (all zeros) Key value is not available for local use.
853 * @partner_port_num: The administrative default for the Port Number component
854 * of the Partner's Port Identifier.
855 * @partner_port_priority: The administrative default for the Port Identifier
856 * component of the Partner's Port Identifier.
857 * @partner_lacp_activity: Indicates the Activity control value for this port.
860 * @partner_lacp_timeout: Indicates the Timeout control value for this port.
863 * @partner_aggregation: Indicates if the port is a potential candidate for
865 * 0 - Link is Individual
866 * 1 - Link is Aggregateable
867 * @partner_synchronization: Indicates if the port is in sync.
868 * 0 - Link is out of sync; it is in the wrong Aggregation
869 * 1 - Link is in sync (allocated to the correct Link Aggregation
870 * Group, the group is associated with a compatible Aggregator,
871 * and the identity of the Link Aggregation Group is consistent
872 * with the System ID and operational Key information transmitted)
873 * @partner_collecting: Indicates whether collecting of incoming frames is
874 * enabled on this port.
876 * 1 - Collection is enabled.
877 * Note: According to IEEE 802.3-2005, the value of the
878 * partner_collecting field of this register must be the same as
879 * the value of the partner_synchronization field of this register
880 * @partner_distributing: Indicates whether distribution of outgoing frames is
881 * enabled on this port.
882 * 0 - Not distributing
883 * 1 - Distribution is enabled
884 * @partner_defaulted: Indicates whether the Actor's Receive state machine is
885 * using administratively configured information for the Partner.
886 * 0 - The operational Partner information has been received in
888 * 1 - The operation Partner information is using administrative
890 * @partner_expired: Indicates whether the Actor's Receive state machine is in
892 * 0 - Not in the EXPIRED state
893 * 1 - Is in the EXPIRED state
894 * @partner_mac_addr: Default value for the MAC address of the Partner.
896 * This structure is configuration for LAG Port of device
898 typedef struct vxge_hal_lag_port_config_t {
900 #define VXGE_HAL_LAG_PORT_PORT_ID_0 1
901 #define VXGE_HAL_LAG_PORT_PORT_ID_1 2
902 #define VXGE_HAL_LAG_PORT_MAX_PORTS VXGE_HAL_MAC_MAX_WIRE_PORTS
905 #define VXGE_HAL_LAG_PORT_LAG_EN_DISABLE 0
906 #define VXGE_HAL_LAG_PORT_LAG_EN_ENABLE 1
907 #define VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
909 u32 discard_slow_proto;
910 #define VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DISABLE 0
911 #define VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE 1
912 #define VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT \
913 VXGE_HAL_USE_FLASH_DEFAULT
915 u32 host_chosen_aggr;
916 #define VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_0 0
917 #define VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1 1
918 #define VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
920 u32 discard_unknown_slow_proto;
921 #define VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DISABLE 0
922 #define VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE 1
923 #define VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT \
924 VXGE_HAL_USE_FLASH_DEFAULT
927 #define VXGE_HAL_LAG_PORT_MIN_ACTOR_PORT_NUM 0
928 #define VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_NUM 65535
929 #define VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM VXGE_HAL_USE_FLASH_DEFAULT
931 u32 actor_port_priority;
932 #define VXGE_HAL_LAG_PORT_MIN_ACTOR_PORT_PRIORITY 0
933 #define VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_PRIORITY 65535
934 #define VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY VXGE_HAL_USE_FLASH_DEFAULT
937 #define VXGE_HAL_LAG_PORT_MIN_ACTOR_KEY_10G 0
938 #define VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_10G 65535
939 #define VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G VXGE_HAL_USE_FLASH_DEFAULT
942 #define VXGE_HAL_LAG_PORT_MIN_ACTOR_KEY_1G 0
943 #define VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_1G 65535
944 #define VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G VXGE_HAL_USE_FLASH_DEFAULT
946 u32 actor_lacp_activity;
947 #define VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_PASSIVE 0
948 #define VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE 1
949 #define VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT \
950 VXGE_HAL_USE_FLASH_DEFAULT
952 u32 actor_lacp_timeout;
953 #define VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_LONG 0
954 #define VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT 1
955 #define VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT \
956 VXGE_HAL_USE_FLASH_DEFAULT
958 u32 actor_aggregation;
959 #define VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_INDIVIDUAL 0
960 #define VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE 1
961 #define VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
963 u32 actor_synchronization;
964 #define VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_OUT_OF_SYNC 0
965 #define VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC 1
966 #define VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT \
967 VXGE_HAL_USE_FLASH_DEFAULT
969 u32 actor_collecting;
970 #define VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DISABLE 0
971 #define VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE 1
972 #define VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
974 u32 actor_distributing;
975 #define VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE 0
976 #define VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE 1
977 #define VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT \
978 VXGE_HAL_USE_FLASH_DEFAULT
981 #define VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED 0
982 #define VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED 1
983 #define VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
986 #define VXGE_HAL_LAG_PORT_ACTOR_EXPIRED 0
987 #define VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED 1
988 #define VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
991 #define VXGE_HAL_LAG_PORT_MIN_PARTNER_SYS_PRI 0
992 #define VXGE_HAL_LAG_PORT_MAX_PARTNER_SYS_PRI 65535
993 #define VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI VXGE_HAL_USE_FLASH_DEFAULT
996 #define VXGE_HAL_LAG_PORT_MIN_PARTNER_KEY 0
997 #define VXGE_HAL_LAG_PORT_MAX_PARTNER_KEY 65535
998 #define VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY VXGE_HAL_USE_FLASH_DEFAULT
1000 u32 partner_port_num;
1001 #define VXGE_HAL_LAG_PORT_MIN_PARTNER_PORT_NUM 0
1002 #define VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_NUM 65535
1003 #define VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM VXGE_HAL_USE_FLASH_DEFAULT
1005 u32 partner_port_priority;
1006 #define VXGE_HAL_LAG_PORT_MIN_PARTNER_PORT_PRIORITY 0
1007 #define VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_PRIORITY 65535
1008 #define VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY VXGE_HAL_USE_FLASH_DEFAULT
1010 u32 partner_lacp_activity;
1011 #define VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_PASSIVE 0
1012 #define VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE 1
1013 #define VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT \
1014 VXGE_HAL_USE_FLASH_DEFAULT
1016 u32 partner_lacp_timeout;
1017 #define VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_LONG 0
1018 #define VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT 1
1019 #define VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT \
1020 VXGE_HAL_USE_FLASH_DEFAULT
1022 u32 partner_aggregation;
1023 #define VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_INDIVIDUAL 0
1024 #define VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE 1
1025 #define VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT \
1026 VXGE_HAL_USE_FLASH_DEFAULT
1028 u32 partner_synchronization;
1029 #define VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_OUT_OF_SYNC 0
1030 #define VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC 1
1031 #define VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT \
1032 VXGE_HAL_USE_FLASH_DEFAULT
1034 u32 partner_collecting;
1035 #define VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DISABLE 0
1036 #define VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE 1
1037 #define VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT \
1038 VXGE_HAL_USE_FLASH_DEFAULT
1040 u32 partner_distributing;
1041 #define VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE 0
1042 #define VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE 1
1043 #define VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT \
1044 VXGE_HAL_USE_FLASH_DEFAULT
1046 u32 partner_defaulted;
1047 #define VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED 0
1048 #define VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED 1
1049 #define VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1051 u32 partner_expired;
1052 #define VXGE_HAL_LAG_PORT_PARTNER_EXPIRED 0
1053 #define VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED 1
1054 #define VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1056 macaddr_t partner_mac_addr;
1058 } vxge_hal_lag_port_config_t;
1061 * struct vxge_hal_lag_aggr_config_t - LAG Aggregator configuration
1062 * (For privileged mode driver only)
1064 * @aggr_id: Aggregator Id
1065 * @mac_addr: The MAC address assigned to the Aggregator.
1066 * @use_port_mac_addr: Indicates whether the Aggregator should use:
1067 * 0 - the address specified in this register
1068 * 1 - the station address of one of the ports to which
1070 * @mac_addr_sel: Indicates which port address to use, if use_port_mac_addr
1071 * is set and two ports are attached to the aggregator:
1072 * 0 - the station address of port 0
1073 * 1 - the station address of port 1.
1074 * @admin_key: The Aggregator's administrative Key under most circumstances
1075 * (see alt_admin_key for exceptions). The null (all zeros) Key
1076 * value is not available for local use.
1077 * This structure is configuration for LAG Aggregators of device
1079 typedef struct vxge_hal_lag_aggr_config_t {
1081 #define VXGE_HAL_LAG_AGGR_AGGR_ID_1 1
1082 #define VXGE_HAL_LAG_AGGR_AGGR_ID_2 2
1083 #define VXGE_HAL_LAG_AGGR_MAX_PORTS VXGE_HAL_MAC_MAX_AGGR_PORTS
1087 u32 use_port_mac_addr;
1088 #define VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DISBALE 0
1089 #define VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE 1
1090 #define VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1093 #define VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_0 0
1094 #define VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1 1
1095 #define VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1098 #define VXGE_HAL_LAG_AGGR_MIN_ADMIN_KEY 0
1099 #define VXGE_HAL_LAG_AGGR_MAX_ADMIN_KEY 65535
1100 #define VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY VXGE_HAL_USE_FLASH_DEFAULT
1102 } vxge_hal_lag_aggr_config_t;
1105 * struct vxge_hal_lag_la_config_t - LAG Link Aggregator mode configuration(
1106 * For privileged mode driver only)
1108 * @tx_discard: When the state of the port state attached to the Tx Aggregator
1109 * is not Distributing, this field determines whether frames from
1110 * the Frame Distributor are discarded by the Aggregator Mux
1111 * @distrib_alg_sel: Configures the link aggregation distribution algorithm,
1112 * which determines the destination port of each wire-bound frame.
1113 * 0x0 - The source VPATH determines the target port and the
1114 * mapping is controlled by the MAP_VPATHn fields of this
1116 * 0x1 - Even parity over the frame's MAC destination address
1117 * 0x2 - Even parity over the frame's MAC source address
1118 * 0x3 - Even parity over the frame's MAC destination address and
1119 * MAC source address
1120 * Note: If the host changes this mapping while traffic is flowing,
1121 * then (to avoid mis-ordering at the receiver) host must either
1122 * enable the Marker protocol or assume responsibility for ensuring
1123 * that no frames pertaining to the conversations (that are moving
1124 * to a new port) are in flight.
1125 * @distrib_dest: When LAG_TX_CFG.DISTRIB_ALG_SEL is set to use the source
1126 * VPATH, then this field indicates the target adapter port for
1127 * frames that come from a particular VPATH.
1128 * 0 - Send frames from this VPATH to port 0
1129 * 1 - Send frames from this VPATH to port 1
1130 * Note: If the host updates this mapping while traffic is flowing,
1131 * then (to avoid mis-ordering at the receiver) the host must
1132 * either enable the Marker protocol or assume responsibility for
1133 * ensuring that no frames pertaining to the conversations (that
1134 * are moving to a new port) are in flight.
1135 * @distrib_remap_if_fail: When lag_mode is Link Aggregated, this field controls
1136 * whether frames are re-distributed to the working port if one
1138 * 0 - Don't remap. Enforce frames destined for port 'x' to remain
1139 * destined for it and let LAG_CFG.TX_DISCARD_BEHAV determine
1140 * what happens to the frames.
1141 * 1 - Remap the frames to the working port, essentially ignoring
1142 * the mapping table.
1143 * @coll_max_delay: Collector Max Delay - the maximum amount of time (measured
1144 * in units of tens of microseconds) that the Frame Collector is
1145 * allowed to delay delivery of frames to the host. The contents
1146 * of this field are placed into the transmitted LACPDU.
1147 * @rx_discard: When the state of the port state attached to the Rx Aggregator
1148 * is not Collecting, this field determines whether frames to the
1149 * Frame Collector are discarded by the Aggregator Parser
1151 * Link Aggregation Link Aggregator Mode Configuration
1153 typedef struct vxge_hal_lag_la_config_t {
1155 #define VXGE_HAL_LAG_TX_DISCARD_DISBALE 0
1156 #define VXGE_HAL_LAG_TX_DISCARD_ENABLE 1
1157 #define VXGE_HAL_LAG_TX_DISCARD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1159 u32 distrib_alg_sel;
1160 #define VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_VPATH 0
1161 #define VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEST_MAC_ADDR 1
1162 #define VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_MAC_ADDR 2
1163 #define VXGE_HAL_LAG_DISTRIB_ALG_SEL_BOTH_MAC_ADDR 3
1164 #define VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1167 #define VXGE_HAL_LAG_DISTRIB_DEST_VPATH_TO_PORT_PORT0(vpid) 0
1168 #define VXGE_HAL_LAG_DISTRIB_DEST_VPATH_TO_PORT_PORT1(vpid) mBIT(vpid)
1169 #define VXGE_HAL_LAG_DISTRIB_DEST_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1171 u32 distrib_remap_if_fail;
1172 #define VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DISBALE 0
1173 #define VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE 1
1174 #define VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1177 #define VXGE_HAL_LAG_MIN_COLL_MAX_DELAY 0
1178 #define VXGE_HAL_LAG_MAX_COLL_MAX_DELAY 65535
1179 #define VXGE_HAL_LAG_DEF_COLL_MAX_DELAY VXGE_HAL_USE_FLASH_DEFAULT
1182 #define VXGE_HAL_LAG_RX_DISCARD_DISBALE 0
1183 #define VXGE_HAL_LAG_RX_DISCARD_ENABLE 1
1184 #define VXGE_HAL_LAG_RX_DISCARD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1187 } vxge_hal_lag_la_config_t;
1190 * struct vxge_hal_lag_ap_config_t - LAG Active Passive Failover mode
1191 * configuration(For privileged mode driver only)
1193 * @hot_standby: Keep the standby port alive even when it is not carrying
1195 * 0 - Standby port disabled until needed. The hardware behaves as
1196 * if XGMAC_CFG_PORTn.PORT_EN has disabled the port.
1197 * 1 - Standby port kept up
1198 * @lacp_decides: This field determines whether or not the LACP Selection logic
1199 * handles hot standby port interaction. This field is only used
1200 * when hot_standby is 1.
1201 * 0 - LACP Selection logic does not explicitly determine standby
1202 * port, instead internal logic changes the aggregator's key
1203 * using information found in the alt_admin_key
1204 * field. Note that this does not disable LACP.
1205 * 1 - LACP Selection logic explicitly determines standby port by
1206 * enforcing a rule that if one port is already attached to any
1207 * aggregator, then the other port is put into STANDBY. Assuming
1208 * both ports have the same Key, at startup (or anytime both
1209 * ports have become UNSELECTED) the Selection logic uses
1210 * pref_active_port to choose the active (and consequently
1211 * standby) port. After that it only selects a new port when
1212 * the active port goes down.
1213 * @pref_active_port: Indicates the preferred active port number.
1214 * If hot_standby is disabled (i.e. "cold standby"), then
1215 * pref_active_port determines which port remains powered up
1216 * (and consequently which one is powered down). If hot_standby is
1217 * enabled, then pref_active_port is used by the Selection logic
1218 * whenever both ports have become UNSELECTED and the Selection
1219 * logic must decide which to make SELECTED and which to make
1221 * 0 - Link0 is preferred (Link1 becomes the standby port).
1222 * 1 - Link1 is preferred
1223 * @auto_failback: When LACP Selection logic is not handling standby port
1224 * interaction, this register provides additional user flexibility
1225 * for standby port handling. The AUTO_FAILBACK field controls
1226 * whether the device automatically fails back to the preferred
1227 * (i.e. non-alternate) Aggregator+Port pair in the event that the
1228 * preferred port comes back up after a failure. Only used when
1229 * hot_standby is set to 1 and lacp_decides is set to 0.
1230 * 0 - After a failure on the preferred port, stay on alternate
1231 * port even if the preferred port comes back up. Return to
1232 * preferred port only when host indicates to return
1234 * 1 - After a failure on the preferred port,automatically failback
1235 * to preferred port whenever it comes back up.
1236 * @failback_en: This field is used when hot_standby is set to 1,lacp_decides is
1237 * set to 0, and AUTO_FAILBACK is set to 0. The field is also used
1238 * when hot_standby is set to 0. The failback_en field allow the
1239 * host to control when the adapter is allowed to fail back to the
1240 * preferred port. The driver sets this field to indicate to the
1241 * adapter that it okay to fail back to the preferred port (i.e.
1242 * attempt to acquire a good port on the preferred port). This
1243 * field is self-clearing -- the adapter clears it immediately.
1244 * Note that the host can use waiting_to_fallback to tell if the
1245 * adapter is waiting for host intervention.
1246 * 0 - Adapter has acknowledged the request to fail back.
1247 * 1 - Host requests that the adapter fail back to preferred port.
1248 * @cold_failover_timeout: When cold standby mode is entered, this field
1249 * controls how long (in msec) the adapter waits for the preferred
1250 * port to come alive (assuming it isn't alreay alive. It the
1251 * preferred port does not come up, then the adapter fails over
1252 * to the standby port when the timer expires. At the time of
1253 * standby port initialization, the timer is started again and
1254 * if the standby port does not come up after the timer expires,
1255 * then both ports are shut down.
1256 * @alt_admin_key: The Aggregator's administrative Key whenever the device is in
1257 * active-passive failover mode and both ports are up. This
1258 * prevents both ports from becoming active in this case.
1259 * The H/W is responsible for choosing the proper key to use in
1260 * this case. The null (all zeros) Key value is not available for
1262 * @alt_aggr: Identifies which Aggregator is designated as the alternate
1263 * (i.e. unused) Aggregator, when both ports are up.
1264 * 0 - Aggregator0 is the alternate
1265 * 1 - Aggregator1 is the alternate
1267 * Link Aggregation Active Passive failover mode Configuration
1269 typedef struct vxge_hal_lag_ap_config_t {
1271 #define VXGE_HAL_LAG_HOT_STANDBY_DISBALE_PORT 0
1272 #define VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT 1
1273 #define VXGE_HAL_LAG_HOT_STANDBY_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1276 #define VXGE_HAL_LAG_LACP_DECIDES_DISBALE 0
1277 #define VXGE_HAL_LAG_LACP_DECIDES_ENBALE 1
1278 #define VXGE_HAL_LAG_LACP_DECIDES_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1280 u32 pref_active_port;
1281 #define VXGE_HAL_LAG_PREF_ACTIVE_PORT_0 0
1282 #define VXGE_HAL_LAG_PREF_ACTIVE_PORT_1 1
1283 #define VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1286 #define VXGE_HAL_LAG_AUTO_FAILBACK_DISBALE 0
1287 #define VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE 1
1288 #define VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1291 #define VXGE_HAL_LAG_FAILBACK_EN_DISBALE 0
1292 #define VXGE_HAL_LAG_FAILBACK_EN_ENBALE 1
1293 #define VXGE_HAL_LAG_FAILBACK_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1295 u32 cold_failover_timeout;
1296 #define VXGE_HAL_LAG_MIN_COLD_FAILOVER_TIMEOUT 0
1297 #define VXGE_HAL_LAG_MAX_COLD_FAILOVER_TIMEOUT 65535
1298 #define VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT
1301 #define VXGE_HAL_LAG_MIN_ALT_ADMIN_KEY 0
1302 #define VXGE_HAL_LAG_MAX_ALT_ADMIN_KEY 65535
1303 #define VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY VXGE_HAL_USE_FLASH_DEFAULT
1306 #define VXGE_HAL_LAG_ALT_AGGR_0 0
1307 #define VXGE_HAL_LAG_ALT_AGGR_1 1
1308 #define VXGE_HAL_LAG_ALT_AGGR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1310 } vxge_hal_lag_ap_config_t;
1313 * struct vxge_hal_lag_sl_config_t - LAG Single Link configuration(For
1314 * privileged mode driver only)
1316 * @pref_indiv_port: For Single Link mode, this field indicates the preferred
1317 * active port number. It is used by the Selection logic whenever
1318 * both ports have become UNSELECTED and the Selection logic must
1319 * decide which to make SELECTED and which to keep UNSELECTED.
1320 * This field is only valid when the MODE field is set to
1323 * Link Aggregation Single Link Configuration
1325 typedef struct vxge_hal_lag_sl_config_t {
1326 u32 pref_indiv_port;
1327 #define VXGE_HAL_LAG_PREF_INDIV_PORT_0 0
1328 #define VXGE_HAL_LAG_PREF_INDIV_PORT_1 1
1329 #define VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1330 } vxge_hal_lag_sl_config_t;
1333 * struct vxge_hal_lag_lacp_config_t - LAG LACP configuration(For privileged
1336 * @lacp_en: Enables use of the on-chip LACP implementation.
1337 * @lacp_begin: Re-initializes the LACP protocol state machines.
1338 * @discard_lacp: If LACP is not enabled on the device, then all LACP frames
1339 * are passed to the host. However, when LACP is enabled,this field
1340 * determines whether the LACP frames are still passed to the host.
1341 * @liberal_len_chk: Controls the length checks that are performed on the
1342 * received LACPDU by the RX FSM. Normally, the received value of
1343 * the following length fields is a known constant and(as suggested
1344 * by IEEE 802.3-2005 43.4.12) the hardware validates them:
1345 * Actor_Information_Length, Partner_Information_Length,
1346 * Collector_Information_Length, and Terminator_Information_Length.
1347 * @marker_gen_recv_en: Enables marker generator/receiver. If this functionality
1348 * is disabled, then the host must assume responsibility for
1349 * ensuring that no frames pertaining to the conversations (that
1350 * are moving to a new port) are in flight, whenever the transmit
1351 * distribution algorithm is updated.
1352 * @marker_resp_en: Enables the transmission of Marker Response PDUs. Adapter
1353 * sends a Marker Response PDU in response to a received Marker PDU
1354 * @marker_resp_timeout: Timeout value for response to Marker frame - number
1355 * of milliseconds that the frame distribution logic will wait
1356 * before assuming that all frames transmitted on a particular
1357 * conversation have been successfully received. If a Marker
1358 * Response PDU comes back before the timer expires, then the
1359 * same assumption is made.
1360 * @slow_proto_mrkr_min_interval: Minimum interval (in milliseconds) between
1361 * Marker PDU transmissions. Includes both Marker PDUs and Marker
1362 * Response PDUs. According to IEEE 802.3-2005 Annex 43B.2, the
1363 * device should send no more than 10 frames in any one-second
1364 * period. Thus, waiting 100ms between successive transmission
1365 * of Slow Protocol frames for the Marker Protocol (i.e. those
1366 * that are sourced by our Marker Generator), guarantee that we
1367 * satisfy this requirement. To be overly conservative the default
1368 * value of this register allows for 200ms between frames.
1369 * @throttle_mrkr_resp: Permits the adapter to throttle the tranmission of
1370 * Marker Response PDUs to satisfy the Slow Protocols transmission
1371 * rate (see IEEE 802.3-2005 Annex 43B).
1372 * 0 - Transmission of Marker Response PDUs is not moderated.
1373 * A Marker Response PDU is sent in response to every received
1374 * Marker frame, regardless of whether the Marker frames are
1375 * being received at a rate below the Slow Protocols rate.
1376 * 1 - Limit the transmission of Marker Response PDUs to the Slow
1377 * Protocols transmission rate. If a remote host is generating
1378 * Marker frames too quickly, then some of these frames will
1379 * have no corresponding Marker Response PDU generated by the
1382 * Link Aggregation LACP Configuration
1384 typedef struct vxge_hal_lag_lacp_config_t {
1386 #define VXGE_HAL_LAG_LACP_EN_DISBALE 0
1387 #define VXGE_HAL_LAG_LACP_EN_ENABLE 1
1388 #define VXGE_HAL_LAG_LACP_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1391 #define VXGE_HAL_LAG_LACP_BEGIN_NORMAL 0
1392 #define VXGE_HAL_LAG_LACP_BEGIN_RESET 1
1393 #define VXGE_HAL_LAG_LACP_BEGIN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1396 #define VXGE_HAL_LAG_DISCARD_LACP_DISBALE 0
1397 #define VXGE_HAL_LAG_DISCARD_LACP_ENABLE 1
1398 #define VXGE_HAL_LAG_DISCARD_LACP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1400 u32 liberal_len_chk;
1401 #define VXGE_HAL_LAG_LIBERAL_LEN_CHK_DISBALE 0
1402 #define VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE 1
1403 #define VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1405 u32 marker_gen_recv_en;
1406 #define VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DISBALE 0
1407 #define VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE 1
1408 #define VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1411 #define VXGE_HAL_LAG_MARKER_RESP_EN_DISBALE 0
1412 #define VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE 1
1413 #define VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1415 u32 marker_resp_timeout;
1416 #define VXGE_HAL_LAG_MIN_MARKER_RESP_TIMEOUT 0
1417 #define VXGE_HAL_LAG_MAX_MARKER_RESP_TIMEOUT 65535
1418 #define VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT
1420 u32 slow_proto_mrkr_min_interval;
1421 #define VXGE_HAL_LAG_MIN_SLOW_PROTO_MRKR_MIN_INTERVAL 0
1422 #define VXGE_HAL_LAG_MAX_SLOW_PROTO_MRKR_MIN_INTERVAL 65535
1423 #define VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL \
1424 VXGE_HAL_USE_FLASH_DEFAULT
1426 u32 throttle_mrkr_resp;
1427 #define VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DISBALE 0
1428 #define VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE 1
1429 #define VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1431 } vxge_hal_lag_lacp_config_t;
1434 * struct vxge_hal_lag_config_t - LAG configuration(For privileged
1437 * @lag_en: Enables link aggregation
1438 * @lag_mode: Select the mode of operation for link aggregation. The options:
1439 * 00 - Link Aggregated
1440 * 01 - Active/Passive Failover
1442 * @la_mode_config: LAG Link Aggregator mode config
1443 * @ap_mode_config: LAG Active Passive Failover mode config
1444 * @sl_mode_config: LAG Single Link mode config
1445 * @lacp_config: LAG LACP config
1446 * @incr_tx_aggr_stats: Controls whether Tx aggregator stats are incremented
1447 * when Link Aggregation is disabled.
1448 * 0 - Don't increment
1450 * Note: When LAG is enabled, aggregator stats are always
1452 * @port_config: Lag Port configuration. See vxge_hal_lag_port_config_t {}
1453 * @aggr_config: Lag Aggregator configuration. See vxge_hal_lag_aggr_config_t {}
1454 * @sys_pri: The System Priority of the System. Numerically lower values have
1456 * @mac_addr: The MAC address assigned to the System. Should be non-zero.
1457 * @use_port_mac_addr: Indicates whether the Aggregator should use:
1458 * 0 - the address specified in this register.
1459 * 1 - the station address of one of the ports in the System
1460 * @mac_addr_sel: Indicates which port address to use, if USE_PORT_ADDR is set:
1461 * 0 - the station address of port 0
1462 * 1 - the station address of port 1.
1463 * @fast_per_time: Fast Periodic Time - number of seconds between periodic
1464 * transmissions of Short Timeouts.
1465 * @slow_per_time: Slow Periodic Time - number of seconds between periodic
1466 * transmissions of Long Timeouts.
1467 * @short_timeout: Short Timeout Time - number of seconds before
1468 * invalidating received LACPDU information using Short
1469 * Timeouts (3 x Fast Periodic Time).
1470 * @long_timeout: Long Timeout Time - number of seconds before invalidating
1471 * received LACPDU information using Long Timeouts
1472 * (3 x Slow Periodic Time).
1473 * @churn_det_time: Churn Detection Time - number of seconds that the
1474 * Actor and Partner Churn state machines wait for the Actor
1475 * or Partner Sync state to stabilize.
1476 * @aggr_wait_time: Aggregate Wait Time - number of seconds to delay
1477 * aggregation,to allow multiple links to aggregate simultaneously
1478 * @short_timer_scale: For simulation purposes, this field allows scaling of
1479 * link aggregation timers. Specifically, the included timers are
1480 * short (programmed with units of msec) and include 'Emptied Link
1481 * Timer', 'Slow Proto Timer for Marker PDU', 'Slow Proto Timer for
1482 * Marker Response PDU', and 'Cold Failover Timer'.
1484 * 0x1 - Scale by 10X (counter expires 10 times faster)
1485 * 0x2 - Scale by 100X
1486 * 0x3 - Scale by 1000X
1487 * @long_timer_scale: For simulation purposes, this field allows scaling of link
1488 * aggregation timers. Specifically, the included timers are long
1489 * (programmed with units of seconds) and include 'Current While
1490 * Timer', 'Periodic Timer', 'Wait While Timer', 'Transmit LACP
1491 * Timer', 'Actor Churn Timer', 'Partner Churn Timer',
1493 * 0x1 - Scale by 10X (counter expires 10 times faster)
1494 * 0x2 - Scale by 100X
1495 * 0x3 - Scale by 1000X
1496 * 0x4 - Scale by 10000X
1497 * 0x5 - Scale by 100000X
1498 * 0x6 - Scale by 1000000X
1500 * Link Aggregation Configuration
1502 typedef struct vxge_hal_lag_config_t {
1504 #define VXGE_HAL_LAG_LAG_EN_DISABLE 0
1505 #define VXGE_HAL_LAG_LAG_EN_ENABLE 1
1506 #define VXGE_HAL_LAG_LAG_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1509 #define VXGE_HAL_LAG_LAG_MODE_LAG 0
1510 #define VXGE_HAL_LAG_LAG_MODE_ACTIVE_PASSIVE_FAILOVER 1
1511 #define VXGE_HAL_LAG_LAG_MODE_SINGLE_LINK 2
1512 #define VXGE_HAL_LAG_LAG_MODE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1514 vxge_hal_lag_la_config_t la_mode_config;
1515 vxge_hal_lag_ap_config_t ap_mode_config;
1516 vxge_hal_lag_sl_config_t sl_mode_config;
1517 vxge_hal_lag_lacp_config_t lacp_config;
1519 u32 incr_tx_aggr_stats;
1520 #define VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DISBALE 0
1521 #define VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE 1
1522 #define VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1524 vxge_hal_lag_port_config_t port_config[VXGE_HAL_LAG_PORT_MAX_PORTS];
1525 vxge_hal_lag_aggr_config_t aggr_config[VXGE_HAL_LAG_AGGR_MAX_PORTS];
1528 #define VXGE_HAL_LAG_MIN_SYS_PRI 0
1529 #define VXGE_HAL_LAG_MAX_SYS_PRI 65535
1530 #define VXGE_HAL_LAG_DEF_SYS_PRI VXGE_HAL_USE_FLASH_DEFAULT
1534 u32 use_port_mac_addr;
1535 #define VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DISBALE 0
1536 #define VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE 1
1537 #define VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1540 #define VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_0 0
1541 #define VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1 1
1542 #define VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1545 #define VXGE_HAL_LAG_MIN_FAST_PER_TIME 0
1546 #define VXGE_HAL_LAG_MAX_FAST_PER_TIME 65535
1547 #define VXGE_HAL_LAG_DEF_FAST_PER_TIME VXGE_HAL_USE_FLASH_DEFAULT
1550 #define VXGE_HAL_LAG_MIN_SLOW_PER_TIME 0
1551 #define VXGE_HAL_LAG_MAX_SLOW_PER_TIME 65535
1552 #define VXGE_HAL_LAG_DEF_SLOW_PER_TIME VXGE_HAL_USE_FLASH_DEFAULT
1555 #define VXGE_HAL_LAG_MIN_SHORT_TIMEOUT 0
1556 #define VXGE_HAL_LAG_MAX_SHORT_TIMEOUT 65535
1557 #define VXGE_HAL_LAG_DEF_SHORT_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT
1560 #define VXGE_HAL_LAG_MIN_LONG_TIMEOUT 0
1561 #define VXGE_HAL_LAG_MAX_LONG_TIMEOUT 65535
1562 #define VXGE_HAL_LAG_DEF_LONG_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT
1565 #define VXGE_HAL_LAG_MIN_CHURN_DET_TIME 0
1566 #define VXGE_HAL_LAG_MAX_CHURN_DET_TIME 65535
1567 #define VXGE_HAL_LAG_DEF_CHURN_DET_TIME VXGE_HAL_USE_FLASH_DEFAULT
1570 #define VXGE_HAL_LAG_MIN_AGGR_WAIT_TIME 0
1571 #define VXGE_HAL_LAG_MAX_AGGR_WAIT_TIME 65535
1572 #define VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME VXGE_HAL_USE_FLASH_DEFAULT
1574 u32 short_timer_scale;
1575 #define VXGE_HAL_LAG_SHORT_TIMER_SCALE_1X 0
1576 #define VXGE_HAL_LAG_SHORT_TIMER_SCALE_10X 1
1577 #define VXGE_HAL_LAG_SHORT_TIMER_SCALE_100X 2
1578 #define VXGE_HAL_LAG_SHORT_TIMER_SCALE_1000X 3
1579 #define VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1581 u32 long_timer_scale;
1582 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_1X 0
1583 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_10X 1
1584 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_100X 2
1585 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_1000X 3
1586 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_10000X 4
1587 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_100000X 5
1588 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_1000000X 6
1589 #define VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1591 } vxge_hal_lag_config_t;
1594 * struct vxge_hal_vpath_qos_config_t - Vpath qos(For privileged
1596 * @priority: The priority of vpath
1597 * @min_bandwidth: Minimum Guaranteed bandwidth
1598 * @max_bandwidth: Maximum allowed bandwidth
1600 * This structure is vpath qos configuration for MRPCIM section of device
1602 typedef struct vxge_hal_vpath_qos_config_t {
1604 #define VXGE_HAL_VPATH_QOS_PRIORITY_MIN 0
1605 #define VXGE_HAL_VPATH_QOS_PRIORITY_MAX 16
1606 #define VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT 0
1609 #define VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MIN 0
1610 #define VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MAX 100
1611 #define VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT 0
1614 #define VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MIN 0
1615 #define VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MAX 100
1616 #define VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT 0
1618 } vxge_hal_vpath_qos_config_t;
1621 * struct vxge_hal_mrpcim_config_t - MRPCIM secion configuration(For privileged
1624 * @mac_config: MAC Port Config. See vxge_hal_mac_config_t {}
1625 * @lag_config: MAC Port Config. See vxge_hal_lag_config_t {}
1626 * @vp_qos: Vpath QOS
1627 * @vpath_to_wire_port_map_en: Mask to enable vpath to wire port mapping.
1628 * @vpath_to_wire_port_map: If LAG is not enabled or lag_distrib_dest is not set
1629 * then vpath_to_wire_port_map is used to assign independent ports
1632 * This structure is configuration for MRPCIM section of device
1634 typedef struct vxge_hal_mrpcim_config_t {
1635 vxge_hal_mac_config_t mac_config;
1636 vxge_hal_lag_config_t lag_config;
1637 u64 vpath_to_wire_port_map_en;
1638 #define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_DISABLE(vpid) 0
1639 #define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_ENABLE(vpid) mBIT(vpid)
1640 #define VXGE_HAL_VPATH_WIRE_PORTS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1641 u64 vpath_to_wire_port_map;
1642 #define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_PORT0(vpid) 0
1643 #define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_PORT1(vpid) mBIT(vpid)
1644 #define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1645 vxge_hal_vpath_qos_config_t vp_qos[VXGE_HAL_MAX_VIRTUAL_PATHS];
1646 } vxge_hal_mrpcim_config_t;
1649 * struct vxge_hal_tim_intr_config_t - X3100 Tim interrupt configuration.
1650 * @intr_enable: Set to 1, if interrupt is enabled.
1651 * @btimer_val: Boundary Timer Initialization value in units of 272 ns.
1652 * @timer_ac_en: Timer Automatic Cancel. 1 : Automatic Canceling Enable: when
1653 * asserted, other interrupt-generating entities will cancel the
1654 * scheduled timer interrupt.
1655 * @timer_ci_en: Timer Continuous Interrupt. 1 : Continuous Interrupting Enable:
1656 * When asserted, an interrupt will be generated every time the
1657 * boundary timer expires, even if no traffic has been transmitted
1658 * on this interrupt.
1659 * @timer_ri_en: Timer Consecutive (Re-) Interrupt 1 : Consecutive
1660 * (Re-) Interrupt Enable: When asserted, an interrupt will be
1661 * generated the next time the timer expires,even if no traffic has
1662 * been transmitted on this interrupt. (This will only happen once
1663 * each time that this value is written to the TIM.) This bit is
1664 * cleared by H/W at the end of the current-timer-interval when
1665 * the interrupt is triggered.
1666 * @rtimer_event_sf: Restriction Timer Event Scale Factor. A scale factor that
1667 * is to be applied to the current event count before it is added
1668 * to the restriction timer value when the the restriction timer
1670 * The scale factor is applied as a right or left shift to multiply
1671 * or divide by the event count. The programmable values are as
1673 * 0-disable restriction timer and use the base timer value.
1674 * 1-Multiply the event count by 2, shift left by 1.
1675 * 2-Multiply the event count by 4, shift left by 2.
1676 * 3-Multiply the event count by 8, shift left by 3.
1677 * 4-Multiply the event count by 16, shift left by 4.
1678 * 5-Multiply the event count by 32, shift left by 5.
1679 * 6-Multiply the event count by 64, shift left by 6.
1680 * 7-Multiply the event count by 128, shift left by 7.
1681 * 8-add the event count, no shifting.
1682 * 9-Divide the event count by 128, shift right by 7.
1683 * 10-Divide the event count by 64, shift right by 6.
1684 * 11-Divide the event count by 32, shift right by 5.
1685 * 12-Divide the event count by 16, shift right by 4.
1686 * 13-Divide the event count by 8, shift right by 3.
1687 * 14-Divide the event count by 4, shift right by 2.
1688 * 15-Divide the event count by 2, shift right by 1.
1689 * @rtimer_val: Restriction Timer Initialization value in units of 272 ns.
1690 * @util_sel: Utilization Selector. Selects which of the workload approximations
1691 * to use (e.g. legacy Tx utilization, Tx/Rx utilization, host
1692 * specified utilization etc.),selects one of the 17 host
1693 * configured values.
1697 * 16-Virtual Path 17
1698 * 17-Legacy Tx network utilization, provided by TPA
1699 * 18-Legacy Rx network utilization, provided by FAU
1700 * 19-Average of legacy Rx and Tx utilization calculated from link
1701 * utilization values.
1702 * 20-31-Invalid configurations
1703 * 32-Host utilization for Virtual Path 0
1704 * 33-Host utilization for Virtual Path 1
1706 * 48-Host utilization for Virtual Path 17
1707 * 49-Legacy Tx network utilization, provided by TPA
1708 * 50-Legacy Rx network utilization, provided by FAU
1709 * 51-Average of legacy Rx and Tx utilization calculated from
1710 * link utilization values.
1711 * 52-63-Invalid configurations
1712 * @ltimer_val: Latency Timer Initialization Value in units of 272 ns.
1713 * @txfrm_cnt_en: Transmit Frame Event Count Enable. This configuration bit
1714 * when set to 1 enables counting of transmit frame's(signalled by
1715 * SM), towards utilization event count values.
1716 * @txd_cnt_en: TxD Return Event Count Enable. This configuration bit when set
1717 * to 1 enables counting of TxD0 returns (signalled by PCC's),
1718 * towards utilization event count values.
1719 * @urange_a: Defines the upper limit (in percent) for this utilization range
1720 * to be active. This range is considered active
1721 * if 0 = UTIL = URNG_A and the UEC_A field (below) is non-zero.
1722 * @uec_a: Utilization Event Count A. If this range is active, the adapter will
1723 * wait until UEC_A events have occurred on the interrupt before
1724 * generating an interrupt.
1725 * @urange_b: Link utilization range B.
1726 * @uec_b: Utilization Event Count B.
1727 * @urange_c: Link utilization range C.
1728 * @uec_c: Utilization Event Count C.
1729 * @urange_d: Link utilization range D.
1730 * @uec_d: Utilization Event Count D.
1734 * @ufca_lbolt_period:
1736 * Traffic Interrupt Controller Module interrupt configuration.
1738 typedef struct vxge_hal_tim_intr_config_t {
1741 #define VXGE_HAL_TIM_INTR_ENABLE 1
1742 #define VXGE_HAL_TIM_INTR_DISABLE 0
1743 #define VXGE_HAL_TIM_INTR_DEFAULT 0
1746 #define VXGE_HAL_MIN_TIM_BTIMER_VAL 0
1747 #define VXGE_HAL_MAX_TIM_BTIMER_VAL 67108864
1748 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL VXGE_HAL_USE_FLASH_DEFAULT
1751 #define VXGE_HAL_TIM_TIMER_AC_ENABLE 1
1752 #define VXGE_HAL_TIM_TIMER_AC_DISABLE 0
1753 #define VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1756 #define VXGE_HAL_TIM_TIMER_CI_ENABLE 1
1757 #define VXGE_HAL_TIM_TIMER_CI_DISABLE 0
1758 #define VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1761 #define VXGE_HAL_TIM_TIMER_RI_ENABLE 1
1762 #define VXGE_HAL_TIM_TIMER_RI_DISABLE 0
1763 #define VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1765 u32 rtimer_event_sf;
1766 #define VXGE_HAL_MIN_TIM_RTIMER_EVENT_SF 0
1767 #define VXGE_HAL_MAX_TIM_RTIMER_EVENT_SF 15
1768 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF \
1769 VXGE_HAL_USE_FLASH_DEFAULT
1772 #define VXGE_HAL_MIN_TIM_RTIMER_VAL 0
1773 #define VXGE_HAL_MAX_TIM_RTIMER_VAL 67108864
1774 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL VXGE_HAL_USE_FLASH_DEFAULT
1777 #define VXGE_HAL_TIM_UTIL_SEL_VPATH(n) n
1778 #define VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL 17
1779 #define VXGE_HAL_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL 18
1780 #define VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL 19
1781 #define VXGE_HAL_TIM_UTIL_SEL_VPATH(n) n
1782 #define VXGE_HAL_TIM_UTIL_SEL_VPATH(n) n
1783 #define VXGE_HAL_TIM_UTIL_SEL_HOST_UTIL_VPATH(n) (32+n)
1784 #define VXGE_HAL_TIM_UTIL_SEL_TIM_UTIL_VPATH(n) 63
1785 #define VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1788 #define VXGE_HAL_MIN_TIM_LTIMER_VAL 0
1789 #define VXGE_HAL_MAX_TIM_LTIMER_VAL 67108864
1790 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL VXGE_HAL_USE_FLASH_DEFAULT
1792 /* Line utilization interrupts */
1794 #define VXGE_HAL_TXFRM_CNT_EN_ENABLE 1
1795 #define VXGE_HAL_TXFRM_CNT_EN_DISABLE 0
1796 #define VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1799 #define VXGE_HAL_TXD_CNT_EN_ENABLE 1
1800 #define VXGE_HAL_TXD_CNT_EN_DISABLE 0
1801 #define VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1804 #define VXGE_HAL_MIN_TIM_URANGE_A 0
1805 #define VXGE_HAL_MAX_TIM_URANGE_A 100
1806 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A VXGE_HAL_USE_FLASH_DEFAULT
1809 #define VXGE_HAL_MIN_TIM_UEC_A 0
1810 #define VXGE_HAL_MAX_TIM_UEC_A 65535
1811 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A VXGE_HAL_USE_FLASH_DEFAULT
1814 #define VXGE_HAL_MIN_TIM_URANGE_B 0
1815 #define VXGE_HAL_MAX_TIM_URANGE_B 100
1816 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B VXGE_HAL_USE_FLASH_DEFAULT
1819 #define VXGE_HAL_MIN_TIM_UEC_B 0
1820 #define VXGE_HAL_MAX_TIM_UEC_B 65535
1821 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B VXGE_HAL_USE_FLASH_DEFAULT
1824 #define VXGE_HAL_MIN_TIM_URANGE_C 0
1825 #define VXGE_HAL_MAX_TIM_URANGE_C 100
1826 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C VXGE_HAL_USE_FLASH_DEFAULT
1829 #define VXGE_HAL_MIN_TIM_UEC_C 0
1830 #define VXGE_HAL_MAX_TIM_UEC_C 65535
1831 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C VXGE_HAL_USE_FLASH_DEFAULT
1834 #define VXGE_HAL_MIN_TIM_UEC_D 0
1835 #define VXGE_HAL_MAX_TIM_UEC_D 65535
1836 #define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D VXGE_HAL_USE_FLASH_DEFAULT
1838 u32 ufca_intr_thres;
1839 #define VXGE_HAL_MIN_UFCA_INTR_THRES 1
1840 #define VXGE_HAL_MAX_UFCA_INTR_THRES 4096
1841 #define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES VXGE_HAL_USE_FLASH_DEFAULT
1844 #define VXGE_HAL_MIN_UFCA_LO_LIM 1
1845 #define VXGE_HAL_MAX_UFCA_LO_LIM 16
1846 #define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM VXGE_HAL_USE_FLASH_DEFAULT
1849 #define VXGE_HAL_MIN_UFCA_HI_LIM 1
1850 #define VXGE_HAL_MAX_UFCA_HI_LIM 256
1851 #define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM VXGE_HAL_USE_FLASH_DEFAULT
1853 u32 ufca_lbolt_period;
1854 #define VXGE_HAL_MIN_UFCA_LBOLT_PERIOD 1
1855 #define VXGE_HAL_MAX_UFCA_LBOLT_PERIOD 1024
1856 #define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD \
1857 VXGE_HAL_USE_FLASH_DEFAULT
1859 } vxge_hal_tim_intr_config_t;
1862 * struct vxge_hal_fifo_config_t - Configuration of fifo.
1863 * @enable: Is this fifo to be commissioned
1864 * @fifo_length: Numbers of TxDLs (that is, lists of Tx descriptors)per queue.
1865 * @max_frags: Max number of Tx buffers per TxDL (that is, per single
1866 * transmit operation).
1867 * No more than 256 transmit buffers can be specified.
1868 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
1869 * (e.g., to align on a cache line).
1870 * @max_aligned_frags: Number of fragments to be aligned out of
1871 * maximum fragments (see @max_frags).
1872 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL.
1874 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
1875 * which generally improves latency of the host bridge operation
1876 * (see PCI specification). For valid values please refer
1877 * to vxge_hal_fifo_config_t {} in the driver sources.
1878 * Configuration of all X3100 fifos.
1879 * Note: Valid (min, max) range for each attribute is specified in the body of
1880 * the vxge_hal_fifo_config_t {} structure.
1882 typedef struct vxge_hal_fifo_config_t {
1884 #define VXGE_HAL_FIFO_ENABLE 1
1885 #define VXGE_HAL_FIFO_DISABLE 0
1886 #define VXGE_HAL_FIFO_DEFAULT 1
1889 #define VXGE_HAL_MIN_FIFO_LENGTH 1
1890 #define VXGE_HAL_MAX_FIFO_LENGTH 12*1024
1891 #define VXGE_HAL_DEF_FIFO_LENGTH 512
1894 #define VXGE_HAL_MIN_FIFO_FRAGS 1
1895 #define VXGE_HAL_MAX_FIFO_FRAGS 256
1896 #define VXGE_HAL_DEF_FIFO_FRAGS 256
1899 #define VXGE_HAL_MIN_FIFO_ALIGNMENT_SIZE 0
1900 #define VXGE_HAL_MAX_FIFO_ALIGNMENT_SIZE 65536
1901 #define VXGE_HAL_DEF_FIFO_ALIGNMENT_SIZE __vxge_os_cacheline_size
1903 u32 max_aligned_frags;
1904 /* range: (1, @max_frags) */
1907 #define VXGE_HAL_FIFO_QUEUE_INTR_ENABLE 1
1908 #define VXGE_HAL_FIFO_QUEUE_INTR_DISABLE 0
1909 #define VXGE_HAL_FIFO_QUEUE_INTR_DEFAULT 0
1912 #define VXGE_HAL_FIFO_NO_SNOOP_DISABLED 0
1913 #define VXGE_HAL_FIFO_NO_SNOOP_TXD 1
1914 #define VXGE_HAL_FIFO_NO_SNOOP_FRM 2
1915 #define VXGE_HAL_FIFO_NO_SNOOP_ALL 3
1916 #define VXGE_HAL_FIFO_NO_SNOOP_DEFAULT 0
1918 } vxge_hal_fifo_config_t;
1921 * struct vxge_hal_ring_config_t - Ring configurations.
1922 * @enable: Is this ring to be commissioned
1923 * @ring_length: Numbers of RxDs in the ring
1924 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer
1925 * to X3100 User Guide.
1926 * @scatter_mode: X3100 supports two receive scatter modes: A and B.
1927 * For details please refer to X3100 User Guide.
1928 * @post_mode: The RxD post mode.
1929 * @max_frm_len: Maximum frame length that can be received on _that_ ring.
1930 * Setting this field to VXGE_HAL_USE_FLASH_DEFAULT ensures that
1931 * the ring will "accept"
1932 * MTU-size frames (note that MTU can be changed at runtime).
1933 * Any value other than (VXGE_HAL_USE_FLASH_DEFAULT) specifies a
1934 * certain "hard" limit on the receive frame sizes. The field can
1935 * be used to activate receive frame-length based steering.
1936 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
1937 * which generally improves latency of the host bridge operation
1938 * (see PCI specification). For valid values please refer
1939 * to vxge_hal_ring_config_t {} in the driver sources.
1940 * @rx_timer_val: The number of 32ns periods that would be counted between two
1942 * @greedy_return: If Set it forces the device to return absolutely all RxD
1943 * that are consumed and still on board when a timer interrupt
1944 * triggers. If Clear, then if the device has already returned
1945 * RxD before current timer interrupt trigerred and after the
1946 * previous timer interrupt triggered, then the device is not
1947 * forced to returned the rest of the consumed RxD that it has
1948 * on board which account for a byte count less than the one
1949 * programmed into PRC_CFG6.RXD_CRXDT field
1951 * @backoff_interval_us: Time (in microseconds), after which X3100
1952 * tries to download RxDs posted by the host.
1953 * Note that the "backoff" does not happen if host posts receive
1954 * descriptors in the timely fashion.
1955 * @indicate_max_pkts: Sets maximum number of received frames to be processed
1956 * within single interrupt.
1957 * @sw_lro_sessions: Number of LRO Sessions
1958 * @sw_lro_sg_size: Size of LROable segment
1959 * @sw_lro_frm_len: Length of LROable frame
1961 * Ring configuration.
1963 typedef struct vxge_hal_ring_config_t {
1965 #define VXGE_HAL_RING_ENABLE 1
1966 #define VXGE_HAL_RING_DISABLE 0
1967 #define VXGE_HAL_RING_DEFAULT 1
1970 #define VXGE_HAL_MIN_RING_LENGTH 1
1971 #define VXGE_HAL_MAX_RING_LENGTH 8096
1972 #define VXGE_HAL_DEF_RING_LENGTH 512
1975 #define VXGE_HAL_RING_RXD_BUFFER_MODE_1 1
1976 #define VXGE_HAL_RING_RXD_BUFFER_MODE_3 3
1977 #define VXGE_HAL_RING_RXD_BUFFER_MODE_5 5
1978 #define VXGE_HAL_RING_RXD_BUFFER_MODE_DEFAULT 1
1981 #define VXGE_HAL_RING_SCATTER_MODE_A 0
1982 #define VXGE_HAL_RING_SCATTER_MODE_B 1
1983 #define VXGE_HAL_RING_SCATTER_MODE_C 2
1984 #define VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT \
1985 VXGE_HAL_USE_FLASH_DEFAULT
1988 #define VXGE_HAL_RING_POST_MODE_LEGACY 0
1989 #define VXGE_HAL_RING_POST_MODE_DOORBELL 1
1990 #define VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
1993 #define VXGE_HAL_MIN_RING_MAX_FRM_LEN VXGE_HAL_MIN_MTU
1994 #define VXGE_HAL_MAX_RING_MAX_FRM_LEN VXGE_HAL_MAX_MTU
1995 #define VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU VXGE_HAL_USE_FLASH_DEFAULT
1998 #define VXGE_HAL_RING_NO_SNOOP_DISABLED 0
1999 #define VXGE_HAL_RING_NO_SNOOP_RXD 1
2000 #define VXGE_HAL_RING_NO_SNOOP_FRM 2
2001 #define VXGE_HAL_RING_NO_SNOOP_ALL 3
2002 #define VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
2005 #define VXGE_HAL_RING_MIN_RX_TIMER_VAL 0
2006 #define VXGE_HAL_RING_MAX_RX_TIMER_VAL 536870912
2007 #define VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL \
2008 VXGE_HAL_USE_FLASH_DEFAULT
2011 #define VXGE_HAL_RING_GREEDY_RETURN_ENABLE 1
2012 #define VXGE_HAL_RING_GREEDY_RETURN_DISABLE 0
2013 #define VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT \
2014 VXGE_HAL_USE_FLASH_DEFAULT
2017 #define VXGE_HAL_RING_RX_TIMER_CI_ENABLE 1
2018 #define VXGE_HAL_RING_RX_TIMER_CI_DISABLE 0
2019 #define VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
2021 u32 backoff_interval_us;
2022 #define VXGE_HAL_MIN_BACKOFF_INTERVAL_US 1
2023 #define VXGE_HAL_MAX_BACKOFF_INTERVAL_US 125000
2024 #define VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US \
2025 VXGE_HAL_USE_FLASH_DEFAULT
2027 u32 indicate_max_pkts;
2028 #define VXGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1
2029 #define VXGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536
2030 #define VXGE_HAL_DEF_RING_INDICATE_MAX_PKTS 65536
2033 } vxge_hal_ring_config_t;
2037 * struct vxge_hal_vp_config_t - Configuration of virtual path
2038 * @vp_id: Virtual Path Id
2039 * @wire_port: Wire port to be associated with the vpath
2040 * @bandwidth_limit: Desired bandwidth limit for this vpath.
2041 * 0 = Disable limit, 1 = 8192 kBps, 2 = 16384 kBps, ... ,
2043 * @no_snoop: Enable or disable no snoop for vpath
2044 * @ring: See vxge_hal_ring_config_t {}.
2045 * @fifo: See vxge_hal_fifo_config_t {}.
2046 * @dmq: See vxge_hal_dmq_config_t {};
2047 * @umq: See vxge_hal_umq_config_t {};
2048 * @lro: See vxge_hal_lro_config_t {};
2049 * @tti: Configuration of interrupt associated with Transmit.
2050 * see vxge_hal_tim_intr_config_t();
2051 * @rti: Configuration of interrupt associated with Receive.
2052 * see vxge_hal_tim_intr_config_t();
2053 * @mtu: mtu size used on this port.
2054 * @tpa_lsov2_en: LSOv2 Behaviour for IP ID roll-over
2055 * @tpa_ignore_frame_error: Ignore Frame Error. TPA may detect frame integrity
2056 * errors as it processes each frame. If this bit is set to '0',
2057 * the TPA will tag such frames as invalid and they will be dropped
2058 * by the transmit MAC. If the bit is set to '1',the frame will not
2059 * be tagged as "errored". Detectable errors include:
2060 * 1) early end-of-frame error, which occurs when the frame ends
2061 * before the number of bytes predicted by the IP "total length"
2062 * field have been received;
2063 * 2) IP version mismatches;
2064 * 3) IPv6 packets that include routing headers that are not type 0
2065 * 4) Frames which contain IP packets but have an illegal SNAP-OUI
2066 * or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL
2067 * are set (see below).
2068 * @tpa_ipv6_keep_searching: If unknown IPv6 header is found,
2069 * 0 - stop searching for TCP
2070 * 1 - keep searching for TCP
2071 * @tpa_l4_pshdr_present: If asserted true, indicates the host has provided a
2072 * valid pseudo header for TCP or UDP running over IPv4 or IPv6
2073 * @tpa_support_mobile_ipv6_hdrs: This register is somewhat equivalent to
2074 * asserting both Hercules register fields LSO_RT2_EN and
2075 * LSO_IPV6_HAO_EN. Enable/disable support for Type 2 Routing
2076 * Headers, and for Mobile-IPv6 Home Address Option (HAO),
2077 * as defined by mobile-ipv6.
2078 * @rpa_ipv4_tcp_incl_ph: Determines if the pseudo-header is included in the
2079 * calculation of the L4 checksum that is passed to the host. This
2080 * field applies to TCP/IPv4 packets only. This field affects both
2081 * non-offload and LRO traffic. Note that the RPA always includes
2082 * the pseudo-header in the "Checksum Ok" L4 checksum calculation
2083 * i.e. the checksum that decides whether a frame is a candidate to
2085 * 0 - Do not include the pseudo-header in L4 checksum calculation.
2086 * This setting should be used if the adapter is incorrectly
2087 * calculating the pseudo-header.
2088 * 1 - Include the pseudo-header in L4 checksum calculation
2089 * @rpa_ipv6_tcp_incl_ph: Determines whether the pseudo-header is included in
2090 * the calculation of the L4 checksum that is passed to the host.
2091 * This field applies to TCP/IPv6 packets only. This field affects
2092 * both non-offload and LRO traffic. Note that the RPA always
2093 * includes the pseudo-header in the "Checksum Ok" L4 checksum
2094 * calculation. i.e. the checksum that decides whether a frame
2095 * is a candidate to be offloaded.
2096 * 0 - Do not include the pseudo-header in L4 checksum calculation.
2097 * This setting should be used if the adapter is incorrectly
2098 * calculating the pseudo-header.
2099 * 1 - Include the pseudo-header in L4 checksum calculation
2100 * @rpa_ipv4_udp_incl_ph: Determines whether the pseudo-header is included in
2101 * the calculation of the L4 checksum that is passed to the host.
2102 * This field applies to UDP/IPv4 packets only. It only affects
2103 * non-offload traffic(since UDP frames are not candidates for LRO)
2104 * 0 - Do not include the pseudo-header in L4 checksum calculation.
2105 * This setting should be used if the adapter is incorrectly
2106 * calculating the pseudo-header.
2107 * 1 - Include the pseudo-header in L4 checksum calculation
2108 * @rpa_ipv6_udp_incl_ph: Determines if the pseudo-header is included in the
2109 * calculation of the L4 checksum that is passed to the host. This
2110 * field applies to UDP/IPv6 packets only. It only affects
2111 * non-offload traffic(since UDP frames are not candidates for LRO)
2112 * 0 - Do not include the pseudo-header in L4 checksum calculation.
2113 * This setting should be used if the adapter is incorrectly
2114 * calculating the pseudo-header.
2115 * 1 - Include the pseudo-header in L4 checksum calculation
2116 * @rpa_l4_incl_cf: Determines whether the checksum field (CF) of the received
2117 * frame is included in the calculation of the L4 checksum that is
2118 * passed to the host. This field affects both non-offload and LRO
2119 * traffic. Note that the RPA always includes the checksum field in
2120 * the "Checksum Ok" L4 checksum calculation -- i.e. the checksum
2121 * that decides whether a frame is a candidate to be offloaded.
2122 * 0 - Do not include the checksum field in L4 checksum calculation
2123 * 1 - Include the checksum field in L4 checksum calculation
2124 * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to
2125 * remove the VLAN tag from all received tagged frames that are not
2126 * replicated at the internal L2 switch.
2127 * 0 - Do not strip the VLAN tag.
2128 * 1 - Strip the VLAN tag. Regardless of this setting,VLAN tags are
2129 * always placed into the RxDMA descriptor.
2130 * @rpa_l4_comp_csum: Determines whether the calculated L4 checksum should be
2131 * complemented before it is passed to the host This field affects
2132 * both non-offload and LRO traffic.
2133 * 0 - Do not complement the calculated L4 checksum.
2134 * 1 - Complement the calculated L4 checksum
2135 * @rpa_l3_incl_cf: Determines whether the checksum field (CF) of the received
2136 * frame is included in the calculation of the L3 checksum that is
2137 * passed to the host. This field affects both non-offload and LRO
2138 * traffic. Note that the RPA always includes the checksum field in
2139 * the "Checksum Ok" L3 checksum calculation--i.e. the checksum
2140 * that decides whether a frame is a candidate to be offloaded.
2141 * 0 - Do not include the checksum field in L3 checksum calculation
2142 * 1 - Include the checksum field in L3 checksum calculation
2143 * @rpa_l3_comp_csum: Determines whether the calculated L3 checksum should be
2144 * complemented before it is passed to the host This field affects
2145 * both non-offload and LRO traffic.
2146 * 0 - Do not complement the calculated L3 checksum.
2147 * 1 - Complement the calculated L3 checksum
2148 * @rpa_ucast_all_addr_en: Enables frames with any unicast address (as its
2149 * destination address) to be passed to the host.
2150 * @rpa_mcast_all_addr_en: Enables frames with any multicast address (as its
2151 * destination address) to be passed to the host.
2152 * @rpa_bcast_en: Enables frames with any broadicast address (as its
2153 * destination address) to be passed to the host.
2154 * @rpa_all_vid_en: romiscuous mode, it overrides the value held in this field.
2157 * Note: RXMAC_GLOBAL_CFG.AUTHORIZE_VP_ALL_VID must be set to
2159 * @vp_queue_l2_flow: Allows per-VPATH receive queue from
2160 * contributing to L2 flow control. Has precedence over
2161 * RMAC_PAUSE_CFG_PORTn.LIMITER_EN.
2162 * 0 - Queue is not allowed to contribute to L2 flow control.
2163 * 1 - Queue is allowed to contribute to L2 flow control.
2165 * This structure is used by the driver to pass the configuration parameters to
2166 * configure Virtual Path.
2168 typedef struct vxge_hal_vp_config_t {
2172 #define VXGE_HAL_VPATH_USE_DEFAULT_PORT VXGE_HAL_FIFO_HOST_STEER_NORMAL
2173 #define VXGE_HAL_VPATH_USE_PORT0 VXGE_HAL_FIFO_HOST_STEER_PORT0
2174 #define VXGE_HAL_VPATH_USE_PORT1 VXGE_HAL_FIFO_HOST_STEER_PORT1
2175 #define VXGE_HAL_VPATH_USE_BOTH VXGE_HAL_FIFO_HOST_STEER_BOTH
2178 #define VXGE_HAL_VPATH_BW_LIMIT_MAX 10000
2179 #define VXGE_HAL_VPATH_BW_LIMIT_MIN 100
2180 #define VXGE_HAL_VPATH_BW_LIMIT_DEFAULT 0XFFFFFFFF
2181 #define VXGE_HAL_TX_BW_VPATH_LIMIT 8
2184 #define VXGE_HAL_VPATH_PRIORITY_MIN 0
2185 #define VXGE_HAL_VPATH_PRIORITY_MAX 3
2186 #define VXGE_HAL_VPATH_PRIORITY_DEFAULT 0XFFFFFFFF
2189 #define VXGE_HAL_VPATH_NO_SNOOP_ENABLE 1
2190 #define VXGE_HAL_VPATH_NO_SNOOP_DISABLE 0
2191 #define VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT \
2192 VXGE_HAL_USE_FLASH_DEFAULT
2194 vxge_hal_ring_config_t ring;
2195 vxge_hal_fifo_config_t fifo;
2197 vxge_hal_tim_intr_config_t tti;
2198 vxge_hal_tim_intr_config_t rti;
2201 #define VXGE_HAL_VPATH_MIN_INITIAL_MTU VXGE_HAL_MIN_MTU
2202 #define VXGE_HAL_VPATH_MAX_INITIAL_MTU VXGE_HAL_MAX_MTU
2203 #define VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU \
2204 VXGE_HAL_USE_FLASH_DEFAULT
2207 #define VXGE_HAL_VPATH_TPA_LSOV2_EN_ENABLE 1
2208 #define VXGE_HAL_VPATH_TPA_LSOV2_EN_DISABLE 0
2209 #define VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT \
2210 VXGE_HAL_USE_FLASH_DEFAULT
2212 u32 tpa_ignore_frame_error;
2213 #define VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_ENABLE 1
2214 #define VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_DISABLE 0
2215 #define VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT \
2216 VXGE_HAL_USE_FLASH_DEFAULT
2218 u32 tpa_ipv6_keep_searching;
2219 #define VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_ENABLE 1
2220 #define VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_DISABLE 0
2221 #define VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT \
2222 VXGE_HAL_USE_FLASH_DEFAULT
2224 u32 tpa_l4_pshdr_present;
2225 #define VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_ENABLE 1
2226 #define VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_DISABLE 0
2227 #define VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT \
2228 VXGE_HAL_USE_FLASH_DEFAULT
2230 u32 tpa_support_mobile_ipv6_hdrs;
2231 #define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_ENABLE 1
2232 #define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DISABLE 0
2233 #define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT \
2234 VXGE_HAL_USE_FLASH_DEFAULT
2235 #define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT \
2236 VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT
2238 u32 rpa_ipv4_tcp_incl_ph;
2239 #define VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_ENABLE 1
2240 #define VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_DISABLE 0
2241 #define VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT \
2242 VXGE_HAL_USE_FLASH_DEFAULT
2244 u32 rpa_ipv6_tcp_incl_ph;
2245 #define VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_ENABLE 1
2246 #define VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_DISABLE 0
2247 #define VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT \
2248 VXGE_HAL_USE_FLASH_DEFAULT
2250 u32 rpa_ipv4_udp_incl_ph;
2251 #define VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_ENABLE 1
2252 #define VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_DISABLE 0
2253 #define VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT \
2254 VXGE_HAL_USE_FLASH_DEFAULT
2256 u32 rpa_ipv6_udp_incl_ph;
2257 #define VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_ENABLE 1
2258 #define VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_DISABLE 0
2259 #define VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT \
2260 VXGE_HAL_USE_FLASH_DEFAULT
2263 #define VXGE_HAL_VPATH_RPA_L4_INCL_CF_ENABLE 1
2264 #define VXGE_HAL_VPATH_RPA_L4_INCL_CF_DISABLE 0
2265 #define VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT \
2266 VXGE_HAL_USE_FLASH_DEFAULT
2268 u32 rpa_strip_vlan_tag;
2269 #define VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE 1
2270 #define VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE 0
2271 #define VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT \
2272 VXGE_HAL_USE_FLASH_DEFAULT
2274 u32 rpa_l4_comp_csum;
2275 #define VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_ENABLE 1
2276 #define VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_DISABLE 0
2277 #define VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT \
2278 VXGE_HAL_USE_FLASH_DEFAULT
2281 #define VXGE_HAL_VPATH_RPA_L3_INCL_CF_ENABLE 1
2282 #define VXGE_HAL_VPATH_RPA_L3_INCL_CF_DISABLE 0
2283 #define VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT \
2284 VXGE_HAL_USE_FLASH_DEFAULT
2286 u32 rpa_l3_comp_csum;
2287 #define VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_ENABLE 1
2288 #define VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_DISABLE 0
2289 #define VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT \
2290 VXGE_HAL_USE_FLASH_DEFAULT
2292 u32 rpa_ucast_all_addr_en;
2293 #define VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE 1
2294 #define VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE 0
2295 #define VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT \
2296 VXGE_HAL_USE_FLASH_DEFAULT
2298 u32 rpa_mcast_all_addr_en;
2299 #define VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE 1
2300 #define VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE 0
2301 #define VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT \
2302 VXGE_HAL_USE_FLASH_DEFAULT
2305 #define VXGE_HAL_VPATH_RPA_BCAST_ENABLE 1
2306 #define VXGE_HAL_VPATH_RPA_BCAST_DISABLE 0
2307 #define VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
2310 #define VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE 1
2311 #define VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE 0
2312 #define VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT \
2313 VXGE_HAL_USE_FLASH_DEFAULT
2315 u32 vp_queue_l2_flow;
2316 #define VXGE_HAL_VPATH_VP_Q_L2_FLOW_ENABLE 1
2317 #define VXGE_HAL_VPATH_VP_Q_L2_FLOW_DISABLE 0
2318 #define VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT \
2319 VXGE_HAL_USE_FLASH_DEFAULT
2321 } vxge_hal_vp_config_t;
2324 * struct vxge_hal_device_config_t - Device configuration.
2325 * @dma_blockpool_min: Minimum blocks in the DMA pool
2326 * @dma_blockpool_initial: Initial size of DMA Pool
2327 * @dma_blockpool_incr: Number of blocks to request each time number of blocks
2328 * in the pool reaches dma_pool_min
2329 * @dma_blockpool_max: Maximum blocks in DMA pool
2330 * @mrpcim_config: MRPCIM section config. Used only for the privileged mode ULD
2332 * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx
2333 * completions. Used in vxge_hal_device_handle_irq().
2334 * @max_payload_size: Maximum TLP payload size for the device/fFunction.
2335 * As a Receiver, the Function/device must handle TLPs as large
2336 * as the set value; as . As a Transmitter, the Function/device
2337 * must not generate TLPs exceeding the set value. Permissible
2338 * values that can be programmed are indicated by the
2339 * Max_Payload_Size Supported in the Device Capabilities register
2340 * @mmrb_count: Maximum Memory Read Byte Count. Use (VXGE_HAL_USE_FLASH_DEFAULT)
2341 * to use default BIOS value.
2342 * @stats_refresh_time_sec: Sets the default interval for automatic stats
2343 * transfer to the host. This includes MAC stats as well as
2345 * @intr_mode: Line, or MSI-X interrupt.
2347 * @dump_on_unknown: Dump adapter state ("about", statistics, registers)
2349 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#.
2350 * @dump_on_critical: Dump adapter state ("about", statistics, registers)
2352 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on
2354 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table).
2355 * @rth_it_type: RTH IT table programming type
2356 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address
2359 * @vp_config: Configuration for virtual paths
2360 * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ
2361 * can own at any one time.
2362 * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that
2363 * this S-RQ can own at any one time.
2364 * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for
2365 * WQEs before generating a message or interrupt.
2366 * @refill_threshold_high:This field provides a hysteresis upper bound for
2367 * automatic adapter refill operations.
2368 * @refill_threshold_low:This field provides a hysteresis lower bound for
2369 * automatic adapter refill operations.
2370 * @eol_policy: This field sets the policy for handling the end of list
2372 * 2'b00 - When EOL is reached, poll until last block wrapper
2373 * size is no longer 0.
2374 * 2'b01 - Send UMQ message when EOL is reached.
2375 * 2'b1x - Poll until the poll_count_max is reached and
2376 * if still EOL, send UMQ message
2377 * @eol_poll_count_max:sets the maximum number of times the queue manager will
2378 * poll fora non-zero block wrapper before giving up and sending
2380 * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be
2381 * held by a session at any one time.
2382 * @poll_or_doorbell: TBD
2383 * @stats_read_method: Stats read method.(DMA or PIO)
2384 * @device_poll_millis: Specify the interval (in mulliseconds) to wait for
2386 * @debug_level: Debug logging level. see vxge_debug_level_e {}
2387 * @debug_mask: Module mask for debug logging level. for masks see vxge_debug.h
2388 * @lro_enable: SW LRO enable mask
2389 * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable.
2391 * X3100 configuration.
2392 * Contains per-device configuration parameters, including:
2393 * - latency timer (settable via PCI configuration space);
2394 * - maximum number of split transactions;
2395 * - maximum number of shared splits;
2396 * - stats sampling interval, etc.
2398 * In addition, vxge_hal_device_config_t {} includes "subordinate"
2399 * configurations, including:
2400 * - fifos and rings;
2401 * - MAC (done at firmware level).
2403 * See X3100 User Guide for more details.
2404 * Note: Valid (min, max) range for each attribute is specified in the body of
2405 * the vxge_hal_device_config_t {} structure. Please refer to the
2406 * corresponding include file.
2407 * See also: vxge_hal_tim_intr_config_t {}.
2409 typedef struct vxge_hal_device_config_t {
2410 u32 dma_blockpool_min;
2411 u32 dma_blockpool_initial;
2412 u32 dma_blockpool_incr;
2413 u32 dma_blockpool_max;
2414 #define VXGE_HAL_MIN_DMA_BLOCK_POOL_SIZE 0
2415 #define VXGE_HAL_INITIAL_DMA_BLOCK_POOL_SIZE 0
2416 #define VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE 4
2417 #define VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE 4096
2419 vxge_hal_mrpcim_config_t mrpcim_config;
2421 u32 isr_polling_cnt;
2422 #define VXGE_HAL_MIN_ISR_POLLING_CNT 0
2423 #define VXGE_HAL_MAX_ISR_POLLING_CNT 65536
2424 #define VXGE_HAL_DEF_ISR_POLLING_CNT 1
2426 u32 max_payload_size;
2427 #define VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE VXGE_HAL_USE_FLASH_DEFAULT
2428 #define VXGE_HAL_MAX_PAYLOAD_SIZE_128 0
2429 #define VXGE_HAL_MAX_PAYLOAD_SIZE_256 1
2430 #define VXGE_HAL_MAX_PAYLOAD_SIZE_512 2
2431 #define VXGE_HAL_MAX_PAYLOAD_SIZE_1024 3
2432 #define VXGE_HAL_MAX_PAYLOAD_SIZE_2048 4
2433 #define VXGE_HAL_MAX_PAYLOAD_SIZE_4096 5
2436 #define VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT VXGE_HAL_USE_FLASH_DEFAULT
2437 #define VXGE_HAL_MMRB_COUNT_128 0
2438 #define VXGE_HAL_MMRB_COUNT_256 1
2439 #define VXGE_HAL_MMRB_COUNT_512 2
2440 #define VXGE_HAL_MMRB_COUNT_1024 3
2441 #define VXGE_HAL_MMRB_COUNT_2048 4
2442 #define VXGE_HAL_MMRB_COUNT_4096 5
2444 u32 stats_refresh_time_sec;
2445 #define VXGE_HAL_STATS_REFRESH_DISABLE 0
2446 #define VXGE_HAL_MIN_STATS_REFRESH_TIME 1
2447 #define VXGE_HAL_MAX_STATS_REFRESH_TIME 300
2448 #define VXGE_HAL_USE_FLASH_DEFAULT_STATS_REFRESH_TIME 30
2451 #define VXGE_HAL_INTR_MODE_IRQLINE 0
2452 #define VXGE_HAL_INTR_MODE_MSIX 1
2453 #define VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT 2
2454 #define VXGE_HAL_INTR_MODE_EMULATED_INTA 3
2455 #define VXGE_HAL_INTR_MODE_DEF 0
2457 u32 dump_on_unknown;
2458 #define VXGE_HAL_DUMP_ON_UNKNOWN_DISABLE 0
2459 #define VXGE_HAL_DUMP_ON_UNKNOWN_ENABLE 1
2460 #define VXGE_HAL_DUMP_ON_UNKNOWN_DEFAULT 0
2463 #define VXGE_HAL_DUMP_ON_SERR_DISABLE 0
2464 #define VXGE_HAL_DUMP_ON_SERR_ENABLE 1
2465 #define VXGE_HAL_DUMP_ON_SERR_DEFAULT 0
2467 u32 dump_on_critical;
2468 #define VXGE_HAL_DUMP_ON_CRITICAL_DISABLE 0
2469 #define VXGE_HAL_DUMP_ON_CRITICAL_ENABLE 1
2470 #define VXGE_HAL_DUMP_ON_CRITICAL_DEFAULT 0
2473 #define VXGE_HAL_DUMP_ON_ECCERR_DISABLE 0
2474 #define VXGE_HAL_DUMP_ON_ECCERR_ENABLE 1
2475 #define VXGE_HAL_DUMP_ON_ECCERR_DEFAULT 0
2478 #define VXGE_HAL_RTH_DISABLE 0
2479 #define VXGE_HAL_RTH_ENABLE 1
2480 #define VXGE_HAL_RTH_DEFAULT 0
2483 #define VXGE_HAL_RTH_IT_TYPE_SOLO_IT 0
2484 #define VXGE_HAL_RTH_IT_TYPE_MULTI_IT 1
2485 #define VXGE_HAL_RTH_IT_TYPE_DEFAULT 0
2488 #define VXGE_HAL_RTS_MAC_DISABLE 0
2489 #define VXGE_HAL_RTS_MAC_ENABLE 1
2490 #define VXGE_HAL_RTS_MAC_DEFAULT 0
2493 #define VXGE_HAL_RTS_QOS_DISABLE 0
2494 #define VXGE_HAL_RTS_QOS_ENABLE 1
2495 #define VXGE_HAL_RTS_QOS_DEFAULT 0
2498 #define VXGE_HAL_RTS_PORT_DISABLE 0
2499 #define VXGE_HAL_RTS_PORT_ENABLE 1
2500 #define VXGE_HAL_RTS_PORT_DEFAULT 0
2502 vxge_hal_vp_config_t vp_config[VXGE_HAL_MAX_VIRTUAL_PATHS];
2505 #define VXGE_HAL_MIN_MAX_CQE_GROUPS 1
2506 #define VXGE_HAL_MAX_MAX_CQE_GROUPS 16
2507 #define VXGE_HAL_DEF_MAX_CQE_GROUPS 16
2509 u32 max_num_wqe_od_groups;
2510 #define VXGE_HAL_MIN_MAX_NUM_OD_GROUPS 1
2511 #define VXGE_HAL_MAX_MAX_NUM_OD_GROUPS 16
2512 #define VXGE_HAL_DEF_MAX_NUM_OD_GROUPS 16
2514 u32 no_wqe_threshold;
2515 #define VXGE_HAL_MIN_NO_WQE_THRESHOLD 1
2516 #define VXGE_HAL_MAX_NO_WQE_THRESHOLD 16
2517 #define VXGE_HAL_DEF_NO_WQE_THRESHOLD 16
2519 u32 refill_threshold_high;
2520 #define VXGE_HAL_MIN_REFILL_THRESHOLD_HIGH 1
2521 #define VXGE_HAL_MAX_REFILL_THRESHOLD_HIGH 16
2522 #define VXGE_HAL_DEF_REFILL_THRESHOLD_HIGH 16
2524 u32 refill_threshold_low;
2525 #define VXGE_HAL_MIN_REFILL_THRESHOLD_LOW 1
2526 #define VXGE_HAL_MAX_REFILL_THRESHOLD_LOW 16
2527 #define VXGE_HAL_DEF_REFILL_THRESHOLD_LOW 16
2530 #define VXGE_HAL_MIN_ACK_BLOCK_LIMIT 1
2531 #define VXGE_HAL_MAX_ACK_BLOCK_LIMIT 16
2532 #define VXGE_HAL_DEF_ACK_BLOCK_LIMIT 16
2534 u32 poll_or_doorbell;
2535 #define VXGE_HAL_POLL_OR_DOORBELL_POLL 1
2536 #define VXGE_HAL_POLL_OR_DOORBELL_DOORBELL 0
2537 #define VXGE_HAL_POLL_OR_DOORBELL_DEFAULT 1
2539 u32 stats_read_method;
2540 #define VXGE_HAL_STATS_READ_METHOD_DMA 1
2541 #define VXGE_HAL_STATS_READ_METHOD_PIO 0
2542 #define VXGE_HAL_STATS_READ_METHOD_DEFAULT 1
2544 u32 device_poll_millis;
2545 #define VXGE_HAL_MIN_DEVICE_POLL_MILLIS 1
2546 #define VXGE_HAL_MAX_DEVICE_POLL_MILLIS 100000
2547 #define VXGE_HAL_DEF_DEVICE_POLL_MILLIS 1000
2549 vxge_debug_level_e debug_level;
2554 #if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
2556 #define VXGE_HAL_MIN_CIRCULAR_ARR 4096
2557 #define VXGE_HAL_MAX_CIRCULAR_ARR 65536
2558 #define VXGE_HAL_DEF_CIRCULAR_ARR 16384
2560 } vxge_hal_device_config_t;
2564 #endif /* VXGE_HAL_CONFIG_H */