2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
101 #ifdef HAVE_KERNEL_OPTION_HEADERS
102 #include "opt_device_polling.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/module.h>
112 #include <sys/socket.h>
113 #include <sys/taskqueue.h>
116 #include <net/if_arp.h>
117 #include <net/ethernet.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/if_types.h>
124 #include <machine/bus.h>
125 #include <machine/resource.h>
127 #include <sys/rman.h>
129 #include <dev/mii/mii.h>
130 #include <dev/mii/miivar.h>
132 #include <dev/pci/pcireg.h>
133 #include <dev/pci/pcivar.h>
135 MODULE_DEPEND(xl, pci, 1, 1, 1);
136 MODULE_DEPEND(xl, ether, 1, 1, 1);
137 MODULE_DEPEND(xl, miibus, 1, 1, 1);
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
142 #include <dev/xl/if_xlreg.h>
145 * TX Checksumming is disabled by default for two reasons:
146 * - TX Checksumming will occasionally produce corrupt packets
147 * - TX Checksumming seems to reduce performance
149 * Only 905B/C cards were reported to have this problem, it is possible
150 * that later chips _may_ be immune.
152 #define XL905B_TXCSUM_BROKEN 1
154 #ifdef XL905B_TXCSUM_BROKEN
155 #define XL905B_CSUM_FEATURES 0
157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 * Various supported device vendors/types and their names.
163 static const struct xl_type xl_devs[] = {
164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
165 "3Com 3c900-TPO Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
167 "3Com 3c900-COMBO Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
169 "3Com 3c905-TX Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
171 "3Com 3c905-T4 Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
173 "3Com 3c900B-TPO Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
175 "3Com 3c900B-COMBO Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
177 "3Com 3c900B-TPC Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
179 "3Com 3c900B-FL Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
181 "3Com 3c905B-TX Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
183 "3Com 3c905B-T4 Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
185 "3Com 3c905B-FX/SC Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
187 "3Com 3c905B-COMBO Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
189 "3Com 3c905C-TX Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
195 "3Com 3c980 Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
197 "3Com 3c980C Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
199 "3Com 3cSOHO100-TX OfficeConnect" },
200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
201 "3Com 3c450-TX HomeConnect" },
202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
203 "3Com 3c555 Fast Etherlink XL" },
204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
205 "3Com 3c556 Fast Etherlink XL" },
206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
207 "3Com 3c556B Fast Etherlink XL" },
208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
209 "3Com 3c575TX Fast Etherlink XL" },
210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
211 "3Com 3c575B Fast Etherlink XL" },
212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
213 "3Com 3c575C Fast Etherlink XL" },
214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
215 "3Com 3c656 Fast Etherlink XL" },
216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
217 "3Com 3c656B Fast Etherlink XL" },
218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
219 "3Com 3c656C Fast Etherlink XL" },
223 static int xl_probe(device_t);
224 static int xl_attach(device_t);
225 static int xl_detach(device_t);
227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
228 static void xl_tick(void *);
229 static void xl_stats_update(struct xl_softc *);
230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
231 static int xl_rxeof(struct xl_softc *);
232 static void xl_rxeof_task(void *, int);
233 static int xl_rx_resync(struct xl_softc *);
234 static void xl_txeof(struct xl_softc *);
235 static void xl_txeof_90xB(struct xl_softc *);
236 static void xl_txeoc(struct xl_softc *);
237 static void xl_intr(void *);
238 static void xl_start(struct ifnet *);
239 static void xl_start_locked(struct ifnet *);
240 static void xl_start_90xB_locked(struct ifnet *);
241 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
242 static void xl_init(void *);
243 static void xl_init_locked(struct xl_softc *);
244 static void xl_stop(struct xl_softc *);
245 static int xl_watchdog(struct xl_softc *);
246 static int xl_shutdown(device_t);
247 static int xl_suspend(device_t);
248 static int xl_resume(device_t);
249 static void xl_setwol(struct xl_softc *);
251 #ifdef DEVICE_POLLING
252 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
253 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
256 static int xl_ifmedia_upd(struct ifnet *);
257 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
259 static int xl_eeprom_wait(struct xl_softc *);
260 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
261 static void xl_mii_sync(struct xl_softc *);
262 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
263 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
264 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
266 static void xl_rxfilter(struct xl_softc *);
267 static void xl_rxfilter_90x(struct xl_softc *);
268 static void xl_rxfilter_90xB(struct xl_softc *);
269 static void xl_setcfg(struct xl_softc *);
270 static void xl_setmode(struct xl_softc *, int);
271 static void xl_reset(struct xl_softc *);
272 static int xl_list_rx_init(struct xl_softc *);
273 static int xl_list_tx_init(struct xl_softc *);
274 static int xl_list_tx_init_90xB(struct xl_softc *);
275 static void xl_wait(struct xl_softc *);
276 static void xl_mediacheck(struct xl_softc *);
277 static void xl_choose_media(struct xl_softc *sc, int *media);
278 static void xl_choose_xcvr(struct xl_softc *, int);
279 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
281 static void xl_testpacket(struct xl_softc *);
284 static int xl_miibus_readreg(device_t, int, int);
285 static int xl_miibus_writereg(device_t, int, int, int);
286 static void xl_miibus_statchg(device_t);
287 static void xl_miibus_mediainit(device_t);
289 static device_method_t xl_methods[] = {
290 /* Device interface */
291 DEVMETHOD(device_probe, xl_probe),
292 DEVMETHOD(device_attach, xl_attach),
293 DEVMETHOD(device_detach, xl_detach),
294 DEVMETHOD(device_shutdown, xl_shutdown),
295 DEVMETHOD(device_suspend, xl_suspend),
296 DEVMETHOD(device_resume, xl_resume),
299 DEVMETHOD(bus_print_child, bus_generic_print_child),
300 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
303 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
304 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
305 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
306 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
311 static driver_t xl_driver = {
314 sizeof(struct xl_softc)
317 static devclass_t xl_devclass;
319 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
320 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
323 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
328 *paddr = segs->ds_addr;
332 * Murphy's law says that it's possible the chip can wedge and
333 * the 'command in progress' bit may never clear. Hence, we wait
334 * only a finite amount of time to avoid getting caught in an
335 * infinite loop. Normally this delay routine would be a macro,
336 * but it isn't called during normal operation so we can afford
337 * to make it a function. Suppress warning when card gone.
340 xl_wait(struct xl_softc *sc)
344 for (i = 0; i < XL_TIMEOUT; i++) {
345 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
349 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
350 device_printf(sc->xl_dev, "command never completed!\n");
354 * MII access routines are provided for adapters with external
355 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
356 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
357 * Note: if you don't perform the MDIO operations just right,
358 * it's possible to end up with code that works correctly with
359 * some chips/CPUs/processor speeds/bus speeds/etc but not
363 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
364 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
367 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
368 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
371 * Sync the PHYs by setting data bit and strobing the clock 32 times.
374 xl_mii_sync(struct xl_softc *sc)
379 MII_SET(XL_MII_DIR|XL_MII_DATA);
381 for (i = 0; i < 32; i++) {
383 MII_SET(XL_MII_DATA);
384 MII_SET(XL_MII_DATA);
386 MII_SET(XL_MII_DATA);
387 MII_SET(XL_MII_DATA);
392 * Clock a series of bits through the MII.
395 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
402 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
404 MII_SET(XL_MII_DATA);
406 MII_CLR(XL_MII_DATA);
414 * Read an PHY register through the MII.
417 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
421 /* Set up frame for RX. */
422 frame->mii_stdelim = XL_MII_STARTDELIM;
423 frame->mii_opcode = XL_MII_READOP;
424 frame->mii_turnaround = 0;
427 /* Select register window 4. */
430 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
431 /* Turn on data xmit. */
436 /* Send command/address info. */
437 xl_mii_send(sc, frame->mii_stdelim, 2);
438 xl_mii_send(sc, frame->mii_opcode, 2);
439 xl_mii_send(sc, frame->mii_phyaddr, 5);
440 xl_mii_send(sc, frame->mii_regaddr, 5);
443 MII_CLR((XL_MII_CLK|XL_MII_DATA));
451 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
455 * Now try reading data bits. If the ack failed, we still
456 * need to clock through 16 cycles to keep the PHY(s) in sync.
459 for (i = 0; i < 16; i++) {
466 for (i = 0x8000; i; i >>= 1) {
469 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
470 frame->mii_data |= i;
479 return (ack ? 1 : 0);
483 * Write to a PHY register through the MII.
486 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
489 /* Set up frame for TX. */
490 frame->mii_stdelim = XL_MII_STARTDELIM;
491 frame->mii_opcode = XL_MII_WRITEOP;
492 frame->mii_turnaround = XL_MII_TURNAROUND;
494 /* Select the window 4. */
497 /* Turn on data output. */
502 xl_mii_send(sc, frame->mii_stdelim, 2);
503 xl_mii_send(sc, frame->mii_opcode, 2);
504 xl_mii_send(sc, frame->mii_phyaddr, 5);
505 xl_mii_send(sc, frame->mii_regaddr, 5);
506 xl_mii_send(sc, frame->mii_turnaround, 2);
507 xl_mii_send(sc, frame->mii_data, 16);
520 xl_miibus_readreg(device_t dev, int phy, int reg)
523 struct xl_mii_frame frame;
525 sc = device_get_softc(dev);
527 bzero((char *)&frame, sizeof(frame));
528 frame.mii_phyaddr = phy;
529 frame.mii_regaddr = reg;
531 xl_mii_readreg(sc, &frame);
533 return (frame.mii_data);
537 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
540 struct xl_mii_frame frame;
542 sc = device_get_softc(dev);
544 bzero((char *)&frame, sizeof(frame));
545 frame.mii_phyaddr = phy;
546 frame.mii_regaddr = reg;
547 frame.mii_data = data;
549 xl_mii_writereg(sc, &frame);
555 xl_miibus_statchg(device_t dev)
558 struct mii_data *mii;
561 sc = device_get_softc(dev);
562 mii = device_get_softc(sc->xl_miibus);
566 /* Set ASIC's duplex mode to match the PHY. */
568 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
569 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
570 macctl |= XL_MACCTRL_DUPLEX;
571 if (sc->xl_type == XL_TYPE_905B) {
572 if ((IFM_OPTIONS(mii->mii_media_active) &
573 IFM_ETH_RXPAUSE) != 0)
574 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
576 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
579 macctl &= ~XL_MACCTRL_DUPLEX;
580 if (sc->xl_type == XL_TYPE_905B)
581 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
583 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
587 * Special support for the 3c905B-COMBO. This card has 10/100 support
588 * plus BNC and AUI ports. This means we will have both an miibus attached
589 * plus some non-MII media settings. In order to allow this, we have to
590 * add the extra media to the miibus's ifmedia struct, but we can't do
591 * that during xl_attach() because the miibus hasn't been attached yet.
592 * So instead, we wait until the miibus probe/attach is done, at which
593 * point we will get a callback telling is that it's safe to add our
597 xl_miibus_mediainit(device_t dev)
600 struct mii_data *mii;
603 sc = device_get_softc(dev);
604 mii = device_get_softc(sc->xl_miibus);
605 ifm = &mii->mii_media;
607 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
609 * Check for a 10baseFL board in disguise.
611 if (sc->xl_type == XL_TYPE_905B &&
612 sc->xl_media == XL_MEDIAOPT_10FL) {
614 device_printf(sc->xl_dev, "found 10baseFL\n");
615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
616 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
618 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
620 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
623 device_printf(sc->xl_dev, "found AUI\n");
624 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
628 if (sc->xl_media & XL_MEDIAOPT_BNC) {
630 device_printf(sc->xl_dev, "found BNC\n");
631 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
636 * The EEPROM is slow: give it time to come ready after issuing
640 xl_eeprom_wait(struct xl_softc *sc)
644 for (i = 0; i < 100; i++) {
645 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
652 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
660 * Read a sequence of words from the EEPROM. Note that ethernet address
661 * data is stored in the EEPROM in network byte order.
664 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
667 u_int16_t word = 0, *ptr;
669 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
670 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
672 * XXX: WARNING! DANGER!
673 * It's easy to accidentally overwrite the rom content!
674 * Note: the 3c575 uses 8bit EEPROM offsets.
678 if (xl_eeprom_wait(sc))
681 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
684 for (i = 0; i < cnt; i++) {
685 if (sc->xl_flags & XL_FLAG_8BITROM)
686 CSR_WRITE_2(sc, XL_W0_EE_CMD,
687 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
689 CSR_WRITE_2(sc, XL_W0_EE_CMD,
690 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
691 err = xl_eeprom_wait(sc);
694 word = CSR_READ_2(sc, XL_W0_EE_DATA);
695 ptr = (u_int16_t *)(dest + (i * 2));
702 return (err ? 1 : 0);
706 xl_rxfilter(struct xl_softc *sc)
709 if (sc->xl_type == XL_TYPE_905B)
710 xl_rxfilter_90xB(sc);
716 * NICs older than the 3c905B have only one multicast option, which
717 * is to enable reception of all multicast frames.
720 xl_rxfilter_90x(struct xl_softc *sc)
723 struct ifmultiaddr *ifma;
731 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
732 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
733 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
735 /* Set the individual bit to receive frames for this host only. */
736 rxfilt |= XL_RXFILTER_INDIVIDUAL;
737 /* Set capture broadcast bit to capture broadcast frames. */
738 if (ifp->if_flags & IFF_BROADCAST)
739 rxfilt |= XL_RXFILTER_BROADCAST;
741 /* If we want promiscuous mode, set the allframes bit. */
742 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
743 if (ifp->if_flags & IFF_PROMISC)
744 rxfilt |= XL_RXFILTER_ALLFRAMES;
745 if (ifp->if_flags & IFF_ALLMULTI)
746 rxfilt |= XL_RXFILTER_ALLMULTI;
749 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
750 if (ifma->ifma_addr->sa_family != AF_LINK)
752 rxfilt |= XL_RXFILTER_ALLMULTI;
755 if_maddr_runlock(ifp);
758 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
763 * 3c905B adapters have a hash filter that we can program.
766 xl_rxfilter_90xB(struct xl_softc *sc)
769 struct ifmultiaddr *ifma;
779 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
780 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
781 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
782 XL_RXFILTER_MULTIHASH);
784 /* Set the individual bit to receive frames for this host only. */
785 rxfilt |= XL_RXFILTER_INDIVIDUAL;
786 /* Set capture broadcast bit to capture broadcast frames. */
787 if (ifp->if_flags & IFF_BROADCAST)
788 rxfilt |= XL_RXFILTER_BROADCAST;
790 /* If we want promiscuous mode, set the allframes bit. */
791 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
792 if (ifp->if_flags & IFF_PROMISC)
793 rxfilt |= XL_RXFILTER_ALLFRAMES;
794 if (ifp->if_flags & IFF_ALLMULTI)
795 rxfilt |= XL_RXFILTER_ALLMULTI;
797 /* First, zot all the existing hash bits. */
798 for (i = 0; i < XL_HASHFILT_SIZE; i++)
799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
801 /* Now program new ones. */
804 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
805 if (ifma->ifma_addr->sa_family != AF_LINK)
808 * Note: the 3c905B currently only supports a 64-bit
809 * hash table, which means we really only need 6 bits,
810 * but the manual indicates that future chip revisions
811 * will have a 256-bit hash table, hence the routine
812 * is set up to calculate 8 bits of position info in
813 * case we need it some day.
814 * Note II, The Sequel: _CURRENT_ versions of the
815 * 3c905B have a 256 bit hash table. This means we have
816 * to use all 8 bits regardless. On older cards, the
817 * upper 2 bits will be ignored. Grrrr....
819 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
820 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
821 CSR_WRITE_2(sc, XL_COMMAND,
822 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
825 if_maddr_runlock(ifp);
827 rxfilt |= XL_RXFILTER_MULTIHASH;
830 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
835 xl_setcfg(struct xl_softc *sc)
839 /*XL_LOCK_ASSERT(sc);*/
842 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
843 icfg &= ~XL_ICFG_CONNECTOR_MASK;
844 if (sc->xl_media & XL_MEDIAOPT_MII ||
845 sc->xl_media & XL_MEDIAOPT_BT4)
846 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
847 if (sc->xl_media & XL_MEDIAOPT_BTX)
848 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
850 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
855 xl_setmode(struct xl_softc *sc, int media)
859 char *pmsg = "", *dmsg = "";
864 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
866 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
868 if (sc->xl_media & XL_MEDIAOPT_BT) {
869 if (IFM_SUBTYPE(media) == IFM_10_T) {
870 pmsg = "10baseT transceiver";
871 sc->xl_xcvr = XL_XCVR_10BT;
872 icfg &= ~XL_ICFG_CONNECTOR_MASK;
873 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
874 mediastat |= XL_MEDIASTAT_LINKBEAT |
875 XL_MEDIASTAT_JABGUARD;
876 mediastat &= ~XL_MEDIASTAT_SQEENB;
880 if (sc->xl_media & XL_MEDIAOPT_BFX) {
881 if (IFM_SUBTYPE(media) == IFM_100_FX) {
882 pmsg = "100baseFX port";
883 sc->xl_xcvr = XL_XCVR_100BFX;
884 icfg &= ~XL_ICFG_CONNECTOR_MASK;
885 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
886 mediastat |= XL_MEDIASTAT_LINKBEAT;
887 mediastat &= ~XL_MEDIASTAT_SQEENB;
891 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
892 if (IFM_SUBTYPE(media) == IFM_10_5) {
894 sc->xl_xcvr = XL_XCVR_AUI;
895 icfg &= ~XL_ICFG_CONNECTOR_MASK;
896 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
897 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
898 XL_MEDIASTAT_JABGUARD);
899 mediastat |= ~XL_MEDIASTAT_SQEENB;
901 if (IFM_SUBTYPE(media) == IFM_10_FL) {
902 pmsg = "10baseFL transceiver";
903 sc->xl_xcvr = XL_XCVR_AUI;
904 icfg &= ~XL_ICFG_CONNECTOR_MASK;
905 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
906 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
907 XL_MEDIASTAT_JABGUARD);
908 mediastat |= ~XL_MEDIASTAT_SQEENB;
912 if (sc->xl_media & XL_MEDIAOPT_BNC) {
913 if (IFM_SUBTYPE(media) == IFM_10_2) {
915 sc->xl_xcvr = XL_XCVR_COAX;
916 icfg &= ~XL_ICFG_CONNECTOR_MASK;
917 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
918 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
919 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
923 if ((media & IFM_GMASK) == IFM_FDX ||
924 IFM_SUBTYPE(media) == IFM_100_FX) {
927 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
931 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
932 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
935 if (IFM_SUBTYPE(media) == IFM_10_2)
936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
940 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
942 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
947 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
951 xl_reset(struct xl_softc *sc)
958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
959 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
960 XL_RESETOPT_DISADVFD:0));
963 * If we're using memory mapped register mode, pause briefly
964 * after issuing the reset command before trying to access any
965 * other registers. With my 3c575C CardBus card, failing to do
966 * this results in the system locking up while trying to poll
967 * the command busy bit in the status register.
969 if (sc->xl_flags & XL_FLAG_USE_MMIO)
972 for (i = 0; i < XL_TIMEOUT; i++) {
974 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
979 device_printf(sc->xl_dev, "reset didn't complete\n");
981 /* Reset TX and RX. */
982 /* Note: the RX reset takes an absurd amount of time
983 * on newer versions of the Tornado chips such as those
984 * on the 3c905CX and newer 3c908C cards. We wait an
985 * extra amount of time so that xl_wait() doesn't complain
986 * and annoy the users.
988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
991 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
994 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
995 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
997 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
998 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
999 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
1000 XL_RESETOPT_INVERT_LED : 0) |
1001 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
1002 XL_RESETOPT_INVERT_MII : 0));
1005 /* Wait a little while for the chip to get its brains in order. */
1010 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1011 * IDs against our list and return a device name if we find a match.
1014 xl_probe(device_t dev)
1016 const struct xl_type *t;
1020 while (t->xl_name != NULL) {
1021 if ((pci_get_vendor(dev) == t->xl_vid) &&
1022 (pci_get_device(dev) == t->xl_did)) {
1023 device_set_desc(dev, t->xl_name);
1024 return (BUS_PROBE_DEFAULT);
1033 * This routine is a kludge to work around possible hardware faults
1034 * or manufacturing defects that can cause the media options register
1035 * (or reset options register, as it's called for the first generation
1036 * 3c90x adapters) to return an incorrect result. I have encountered
1037 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1038 * which doesn't have any of the 'mediaopt' bits set. This screws up
1039 * the attach routine pretty badly because it doesn't know what media
1040 * to look for. If we find ourselves in this predicament, this routine
1041 * will try to guess the media options values and warn the user of a
1042 * possible manufacturing defect with his adapter/system/whatever.
1045 xl_mediacheck(struct xl_softc *sc)
1049 * If some of the media options bits are set, assume they are
1050 * correct. If not, try to figure it out down below.
1051 * XXX I should check for 10baseFL, but I don't have an adapter
1054 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1056 * Check the XCVR value. If it's not in the normal range
1057 * of values, we need to fake it up here.
1059 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1062 device_printf(sc->xl_dev,
1063 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1064 device_printf(sc->xl_dev,
1065 "choosing new default based on card type\n");
1068 if (sc->xl_type == XL_TYPE_905B &&
1069 sc->xl_media & XL_MEDIAOPT_10FL)
1071 device_printf(sc->xl_dev,
1072 "WARNING: no media options bits set in the media options register!!\n");
1073 device_printf(sc->xl_dev,
1074 "this could be a manufacturing defect in your adapter or system\n");
1075 device_printf(sc->xl_dev,
1076 "attempting to guess media type; you should probably consult your vendor\n");
1079 xl_choose_xcvr(sc, 1);
1083 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1088 * Read the device ID from the EEPROM.
1089 * This is what's loaded into the PCI device ID register, so it has
1090 * to be correct otherwise we wouldn't have gotten this far.
1092 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1095 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1096 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1097 sc->xl_media = XL_MEDIAOPT_BT;
1098 sc->xl_xcvr = XL_XCVR_10BT;
1100 device_printf(sc->xl_dev,
1101 "guessing 10BaseT transceiver\n");
1103 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1104 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1105 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1106 sc->xl_xcvr = XL_XCVR_10BT;
1108 device_printf(sc->xl_dev,
1109 "guessing COMBO (AUI/BNC/TP)\n");
1111 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1112 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1113 sc->xl_xcvr = XL_XCVR_10BT;
1115 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1117 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1118 sc->xl_media = XL_MEDIAOPT_10FL;
1119 sc->xl_xcvr = XL_XCVR_AUI;
1121 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1123 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1124 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1125 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1126 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1127 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1128 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1129 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1130 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1131 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1132 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1133 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1134 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1135 sc->xl_media = XL_MEDIAOPT_MII;
1136 sc->xl_xcvr = XL_XCVR_MII;
1138 device_printf(sc->xl_dev, "guessing MII\n");
1140 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1141 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1142 sc->xl_media = XL_MEDIAOPT_BT4;
1143 sc->xl_xcvr = XL_XCVR_MII;
1145 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1147 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1148 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1149 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1150 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1151 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1152 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1153 sc->xl_media = XL_MEDIAOPT_BTX;
1154 sc->xl_xcvr = XL_XCVR_AUTO;
1156 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1158 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1159 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1160 sc->xl_xcvr = XL_XCVR_AUTO;
1162 device_printf(sc->xl_dev,
1163 "guessing 10/100 plus BNC/AUI\n");
1166 device_printf(sc->xl_dev,
1167 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1168 sc->xl_media = XL_MEDIAOPT_BT;
1174 * Attach the interface. Allocate softc structures, do ifmedia
1175 * setup and ethernet/BPF attach.
1178 xl_attach(device_t dev)
1180 u_char eaddr[ETHER_ADDR_LEN];
1181 u_int16_t sinfo2, xcvr[2];
1182 struct xl_softc *sc;
1185 int error = 0, phy, rid, res, unit;
1188 sc = device_get_softc(dev);
1191 unit = device_get_unit(dev);
1193 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1195 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1197 did = pci_get_device(dev);
1200 if (did == TC_DEVICEID_HURRICANE_555)
1201 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1202 if (did == TC_DEVICEID_HURRICANE_556 ||
1203 did == TC_DEVICEID_HURRICANE_556B)
1204 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1205 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1206 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1207 if (did == TC_DEVICEID_HURRICANE_555 ||
1208 did == TC_DEVICEID_HURRICANE_556)
1209 sc->xl_flags |= XL_FLAG_8BITROM;
1210 if (did == TC_DEVICEID_HURRICANE_556B)
1211 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1213 if (did == TC_DEVICEID_HURRICANE_575B ||
1214 did == TC_DEVICEID_HURRICANE_575C ||
1215 did == TC_DEVICEID_HURRICANE_656B ||
1216 did == TC_DEVICEID_TORNADO_656C)
1217 sc->xl_flags |= XL_FLAG_FUNCREG;
1218 if (did == TC_DEVICEID_HURRICANE_575A ||
1219 did == TC_DEVICEID_HURRICANE_575B ||
1220 did == TC_DEVICEID_HURRICANE_575C ||
1221 did == TC_DEVICEID_HURRICANE_656B ||
1222 did == TC_DEVICEID_TORNADO_656C)
1223 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1225 if (did == TC_DEVICEID_HURRICANE_656)
1226 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1227 if (did == TC_DEVICEID_HURRICANE_575B)
1228 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1229 if (did == TC_DEVICEID_HURRICANE_575C)
1230 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1231 if (did == TC_DEVICEID_TORNADO_656C)
1232 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1233 if (did == TC_DEVICEID_HURRICANE_656 ||
1234 did == TC_DEVICEID_HURRICANE_656B)
1235 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1236 XL_FLAG_INVERT_LED_PWR;
1237 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1238 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1239 sc->xl_flags |= XL_FLAG_PHYOK;
1242 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1243 case TC_DEVICEID_HURRICANE_575A:
1244 case TC_DEVICEID_HURRICANE_575B:
1245 case TC_DEVICEID_HURRICANE_575C:
1246 sc->xl_flags |= XL_FLAG_NO_MMIO;
1253 * Map control/status registers.
1255 pci_enable_busmaster(dev);
1257 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1259 res = SYS_RES_MEMORY;
1261 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1264 if (sc->xl_res != NULL) {
1265 sc->xl_flags |= XL_FLAG_USE_MMIO;
1267 device_printf(dev, "using memory mapped I/O\n");
1270 res = SYS_RES_IOPORT;
1271 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1272 if (sc->xl_res == NULL) {
1273 device_printf(dev, "couldn't map ports/memory\n");
1278 device_printf(dev, "using port I/O\n");
1281 sc->xl_btag = rman_get_bustag(sc->xl_res);
1282 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1284 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1285 rid = XL_PCI_FUNCMEM;
1286 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1289 if (sc->xl_fres == NULL) {
1290 device_printf(dev, "couldn't map funcreg memory\n");
1295 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1296 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1299 /* Allocate interrupt */
1301 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1302 RF_SHAREABLE | RF_ACTIVE);
1303 if (sc->xl_irq == NULL) {
1304 device_printf(dev, "couldn't map interrupt\n");
1309 /* Initialize interface name. */
1310 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1312 device_printf(dev, "can not if_alloc()\n");
1317 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1319 /* Reset the adapter. */
1325 * Get station address from the EEPROM.
1327 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1328 device_printf(dev, "failed to read station address\n");
1333 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1334 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1337 * Now allocate a tag for the DMA descriptor lists and a chunk
1338 * of DMA-able memory based on the tag. Also obtain the DMA
1339 * addresses of the RX and TX ring, which we'll need later.
1340 * All of our lists are allocated as a contiguous block
1343 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1344 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1345 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1346 &sc->xl_ldata.xl_rx_tag);
1348 device_printf(dev, "failed to allocate rx dma tag\n");
1352 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1353 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1354 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1356 device_printf(dev, "no memory for rx list buffers!\n");
1357 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1358 sc->xl_ldata.xl_rx_tag = NULL;
1362 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1363 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1364 XL_RX_LIST_SZ, xl_dma_map_addr,
1365 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1367 device_printf(dev, "cannot get dma address of the rx ring!\n");
1368 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1369 sc->xl_ldata.xl_rx_dmamap);
1370 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1371 sc->xl_ldata.xl_rx_tag = NULL;
1375 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1376 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1377 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1378 &sc->xl_ldata.xl_tx_tag);
1380 device_printf(dev, "failed to allocate tx dma tag\n");
1384 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1385 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1386 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1388 device_printf(dev, "no memory for list buffers!\n");
1389 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1390 sc->xl_ldata.xl_tx_tag = NULL;
1394 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1395 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1396 XL_TX_LIST_SZ, xl_dma_map_addr,
1397 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1399 device_printf(dev, "cannot get dma address of the tx ring!\n");
1400 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1401 sc->xl_ldata.xl_tx_dmamap);
1402 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1403 sc->xl_ldata.xl_tx_tag = NULL;
1408 * Allocate a DMA tag for the mapping of mbufs.
1410 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1411 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1412 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1413 NULL, &sc->xl_mtag);
1415 device_printf(dev, "failed to allocate mbuf dma tag\n");
1419 /* We need a spare DMA map for the RX ring. */
1420 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1425 * Figure out the card type. 3c905B adapters have the
1426 * 'supportsNoTxLength' bit set in the capabilities
1427 * word in the EEPROM.
1428 * Note: my 3c575C CardBus card lies. It returns a value
1429 * of 0x1578 for its capabilities word, which is somewhat
1430 * nonsensical. Another way to distinguish a 3c90x chip
1431 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1432 * bit. This will only be set for 3c90x boomerage chips.
1434 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1435 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1436 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1437 sc->xl_type = XL_TYPE_905B;
1439 sc->xl_type = XL_TYPE_90X;
1441 /* Check availability of WOL. */
1442 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1443 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1444 sc->xl_pmcap = pmcap;
1445 sc->xl_flags |= XL_FLAG_WOL;
1447 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1448 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1450 "No auxiliary remote wakeup connector!\n");
1453 /* Set the TX start threshold for best performance. */
1454 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1456 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1457 ifp->if_ioctl = xl_ioctl;
1458 ifp->if_capabilities = IFCAP_VLAN_MTU;
1459 if (sc->xl_type == XL_TYPE_905B) {
1460 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1461 #ifdef XL905B_TXCSUM_BROKEN
1462 ifp->if_capabilities |= IFCAP_RXCSUM;
1464 ifp->if_capabilities |= IFCAP_HWCSUM;
1467 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1468 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1469 ifp->if_capenable = ifp->if_capabilities;
1470 #ifdef DEVICE_POLLING
1471 ifp->if_capabilities |= IFCAP_POLLING;
1473 ifp->if_start = xl_start;
1474 ifp->if_init = xl_init;
1475 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1476 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1477 IFQ_SET_READY(&ifp->if_snd);
1480 * Now we have to see what sort of media we have.
1481 * This includes probing for an MII interace and a
1485 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1487 device_printf(dev, "media options word: %x\n", sc->xl_media);
1489 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1490 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1491 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1492 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1496 if (sc->xl_media & XL_MEDIAOPT_MII ||
1497 sc->xl_media & XL_MEDIAOPT_BTX ||
1498 sc->xl_media & XL_MEDIAOPT_BT4) {
1500 device_printf(dev, "found MII/AUTO\n");
1503 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1504 * This is to guard against problems with certain 3Com ASIC
1505 * revisions that incorrectly map the internal transceiver
1506 * control registers at all MII addresses.
1509 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1511 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1512 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1513 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1515 device_printf(dev, "attaching PHYs failed\n");
1522 * Sanity check. If the user has selected "auto" and this isn't
1523 * a 10/100 card of some kind, we need to force the transceiver
1524 * type to something sane.
1526 if (sc->xl_xcvr == XL_XCVR_AUTO)
1527 xl_choose_xcvr(sc, bootverbose);
1532 if (sc->xl_media & XL_MEDIAOPT_BT) {
1534 device_printf(dev, "found 10baseT\n");
1535 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1536 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1537 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1538 ifmedia_add(&sc->ifmedia,
1539 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1542 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1544 * Check for a 10baseFL board in disguise.
1546 if (sc->xl_type == XL_TYPE_905B &&
1547 sc->xl_media == XL_MEDIAOPT_10FL) {
1549 device_printf(dev, "found 10baseFL\n");
1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1551 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1553 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1554 ifmedia_add(&sc->ifmedia,
1555 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1558 device_printf(dev, "found AUI\n");
1559 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1563 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1565 device_printf(dev, "found BNC\n");
1566 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1569 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1571 device_printf(dev, "found 100baseFX\n");
1572 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1575 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1576 xl_choose_media(sc, &media);
1578 if (sc->xl_miibus == NULL)
1579 ifmedia_set(&sc->ifmedia, media);
1582 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1584 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1588 * Call MI attach routine.
1590 ether_ifattach(ifp, eaddr);
1592 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1593 NULL, xl_intr, sc, &sc->xl_intrhand);
1595 device_printf(dev, "couldn't set up irq\n");
1596 ether_ifdetach(ifp);
1608 * Choose a default media.
1609 * XXX This is a leaf function only called by xl_attach() and
1610 * acquires/releases the non-recursible driver mutex to
1611 * satisfy lock assertions.
1614 xl_choose_media(struct xl_softc *sc, int *media)
1619 switch (sc->xl_xcvr) {
1621 *media = IFM_ETHER|IFM_10_T;
1622 xl_setmode(sc, *media);
1625 if (sc->xl_type == XL_TYPE_905B &&
1626 sc->xl_media == XL_MEDIAOPT_10FL) {
1627 *media = IFM_ETHER|IFM_10_FL;
1628 xl_setmode(sc, *media);
1630 *media = IFM_ETHER|IFM_10_5;
1631 xl_setmode(sc, *media);
1635 *media = IFM_ETHER|IFM_10_2;
1636 xl_setmode(sc, *media);
1639 case XL_XCVR_100BTX:
1641 /* Chosen by miibus */
1643 case XL_XCVR_100BFX:
1644 *media = IFM_ETHER|IFM_100_FX;
1647 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1650 * This will probably be wrong, but it prevents
1651 * the ifmedia code from panicking.
1653 *media = IFM_ETHER|IFM_10_T;
1661 * Shutdown hardware and free up resources. This can be called any
1662 * time after the mutex has been initialized. It is called in both
1663 * the error case in attach and the normal detach case so it needs
1664 * to be careful about only freeing resources that have actually been
1668 xl_detach(device_t dev)
1670 struct xl_softc *sc;
1674 sc = device_get_softc(dev);
1677 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1679 #ifdef DEVICE_POLLING
1680 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1681 ether_poll_deregister(ifp);
1684 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1686 res = SYS_RES_MEMORY;
1689 res = SYS_RES_IOPORT;
1692 /* These should only be active if attach succeeded */
1693 if (device_is_attached(dev)) {
1697 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1698 callout_drain(&sc->xl_tick_callout);
1699 ether_ifdetach(ifp);
1702 device_delete_child(dev, sc->xl_miibus);
1703 bus_generic_detach(dev);
1704 ifmedia_removeall(&sc->ifmedia);
1706 if (sc->xl_intrhand)
1707 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1709 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1710 if (sc->xl_fres != NULL)
1711 bus_release_resource(dev, SYS_RES_MEMORY,
1712 XL_PCI_FUNCMEM, sc->xl_fres);
1714 bus_release_resource(dev, res, rid, sc->xl_res);
1720 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1721 bus_dma_tag_destroy(sc->xl_mtag);
1723 if (sc->xl_ldata.xl_rx_tag) {
1724 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1725 sc->xl_ldata.xl_rx_dmamap);
1726 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1727 sc->xl_ldata.xl_rx_dmamap);
1728 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1730 if (sc->xl_ldata.xl_tx_tag) {
1731 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1732 sc->xl_ldata.xl_tx_dmamap);
1733 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1734 sc->xl_ldata.xl_tx_dmamap);
1735 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1738 mtx_destroy(&sc->xl_mtx);
1744 * Initialize the transmit descriptors.
1747 xl_list_tx_init(struct xl_softc *sc)
1749 struct xl_chain_data *cd;
1750 struct xl_list_data *ld;
1757 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1758 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1759 error = bus_dmamap_create(sc->xl_mtag, 0,
1760 &cd->xl_tx_chain[i].xl_map);
1763 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1764 i * sizeof(struct xl_list);
1765 if (i == (XL_TX_LIST_CNT - 1))
1766 cd->xl_tx_chain[i].xl_next = NULL;
1768 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1771 cd->xl_tx_free = &cd->xl_tx_chain[0];
1772 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1774 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1779 * Initialize the transmit descriptors.
1782 xl_list_tx_init_90xB(struct xl_softc *sc)
1784 struct xl_chain_data *cd;
1785 struct xl_list_data *ld;
1792 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1793 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1794 error = bus_dmamap_create(sc->xl_mtag, 0,
1795 &cd->xl_tx_chain[i].xl_map);
1798 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1799 i * sizeof(struct xl_list);
1800 if (i == (XL_TX_LIST_CNT - 1))
1801 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1803 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1805 cd->xl_tx_chain[i].xl_prev =
1806 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1808 cd->xl_tx_chain[i].xl_prev =
1809 &cd->xl_tx_chain[i - 1];
1812 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1813 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1819 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1824 * Initialize the RX descriptors and allocate mbufs for them. Note that
1825 * we arrange the descriptors in a closed ring, so that the last descriptor
1826 * points back to the first.
1829 xl_list_rx_init(struct xl_softc *sc)
1831 struct xl_chain_data *cd;
1832 struct xl_list_data *ld;
1841 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1842 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1843 error = bus_dmamap_create(sc->xl_mtag, 0,
1844 &cd->xl_rx_chain[i].xl_map);
1847 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1850 if (i == (XL_RX_LIST_CNT - 1))
1854 nextptr = ld->xl_rx_dmaaddr +
1855 next * sizeof(struct xl_list_onefrag);
1856 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1857 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1860 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1861 cd->xl_rx_head = &cd->xl_rx_chain[0];
1867 * Initialize an RX descriptor and attach an MBUF cluster.
1868 * If we fail to do so, we need to leave the old mbuf and
1869 * the old DMA map untouched so that it can be reused.
1872 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1874 struct mbuf *m_new = NULL;
1876 bus_dma_segment_t segs[1];
1881 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1885 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1887 /* Force longword alignment for packet payload. */
1888 m_adj(m_new, ETHER_ALIGN);
1890 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1891 segs, &nseg, BUS_DMA_NOWAIT);
1894 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1899 ("%s: too many DMA segments (%d)", __func__, nseg));
1901 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1903 c->xl_map = sc->xl_tmpmap;
1904 sc->xl_tmpmap = map;
1906 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1907 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1908 c->xl_ptr->xl_status = 0;
1909 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1914 xl_rx_resync(struct xl_softc *sc)
1916 struct xl_chain_onefrag *pos;
1921 pos = sc->xl_cdata.xl_rx_head;
1923 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1924 if (pos->xl_ptr->xl_status)
1929 if (i == XL_RX_LIST_CNT)
1932 sc->xl_cdata.xl_rx_head = pos;
1938 * A frame has been uploaded: pass the resulting mbuf chain up to
1939 * the higher level protocols.
1942 xl_rxeof(struct xl_softc *sc)
1945 struct ifnet *ifp = sc->xl_ifp;
1946 struct xl_chain_onefrag *cur_rx;
1953 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1954 BUS_DMASYNC_POSTREAD);
1955 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1956 #ifdef DEVICE_POLLING
1957 if (ifp->if_capenable & IFCAP_POLLING) {
1958 if (sc->rxcycles <= 0)
1963 cur_rx = sc->xl_cdata.xl_rx_head;
1964 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1965 total_len = rxstat & XL_RXSTAT_LENMASK;
1969 * Since we have told the chip to allow large frames,
1970 * we need to trap giant frame errors in software. We allow
1971 * a little more than the normal frame size to account for
1972 * frames with VLAN tags.
1974 if (total_len > XL_MAX_FRAMELEN)
1975 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1978 * If an error occurs, update stats, clear the
1979 * status word and leave the mbuf cluster in place:
1980 * it should simply get re-used next time this descriptor
1981 * comes up in the ring.
1983 if (rxstat & XL_RXSTAT_UP_ERROR) {
1985 cur_rx->xl_ptr->xl_status = 0;
1986 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1987 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1992 * If the error bit was not set, the upload complete
1993 * bit should be set which means we have a valid packet.
1994 * If not, something truly strange has happened.
1996 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1997 device_printf(sc->xl_dev,
1998 "bad receive status -- packet dropped\n");
2000 cur_rx->xl_ptr->xl_status = 0;
2001 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2002 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2006 /* No errors; receive the packet. */
2007 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2008 BUS_DMASYNC_POSTREAD);
2009 m = cur_rx->xl_mbuf;
2012 * Try to conjure up a new mbuf cluster. If that
2013 * fails, it means we have an out of memory condition and
2014 * should leave the buffer in place and continue. This will
2015 * result in a lost packet, but there's little else we
2016 * can do in this situation.
2018 if (xl_newbuf(sc, cur_rx)) {
2020 cur_rx->xl_ptr->xl_status = 0;
2021 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2022 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2025 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2026 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2029 m->m_pkthdr.rcvif = ifp;
2030 m->m_pkthdr.len = m->m_len = total_len;
2032 if (ifp->if_capenable & IFCAP_RXCSUM) {
2033 /* Do IP checksum checking. */
2034 if (rxstat & XL_RXSTAT_IPCKOK)
2035 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2036 if (!(rxstat & XL_RXSTAT_IPCKERR))
2037 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2038 if ((rxstat & XL_RXSTAT_TCPCOK &&
2039 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2040 (rxstat & XL_RXSTAT_UDPCKOK &&
2041 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2042 m->m_pkthdr.csum_flags |=
2043 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2044 m->m_pkthdr.csum_data = 0xffff;
2049 (*ifp->if_input)(ifp, m);
2053 * If we are running from the taskqueue, the interface
2054 * might have been stopped while we were passing the last
2055 * packet up the network stack.
2057 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2062 * Handle the 'end of channel' condition. When the upload
2063 * engine hits the end of the RX ring, it will stall. This
2064 * is our cue to flush the RX ring, reload the uplist pointer
2065 * register and unstall the engine.
2066 * XXX This is actually a little goofy. With the ThunderLAN
2067 * chip, you get an interrupt when the receiver hits the end
2068 * of the receive ring, which tells you exactly when you
2069 * you need to reload the ring pointer. Here we have to
2070 * fake it. I'm mad at myself for not being clever enough
2071 * to avoid the use of a goto here.
2073 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2074 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2075 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2077 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2078 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2079 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2086 * Taskqueue wrapper for xl_rxeof().
2089 xl_rxeof_task(void *arg, int pending)
2091 struct xl_softc *sc = (struct xl_softc *)arg;
2094 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
2100 * A frame was downloaded to the chip. It's safe for us to clean up
2104 xl_txeof(struct xl_softc *sc)
2106 struct xl_chain *cur_tx;
2107 struct ifnet *ifp = sc->xl_ifp;
2112 * Go through our tx list and free mbufs for those
2113 * frames that have been uploaded. Note: the 3c905B
2114 * sets a special bit in the status word to let us
2115 * know that a frame has been downloaded, but the
2116 * original 3c900/3c905 adapters don't do that.
2117 * Consequently, we have to use a different test if
2118 * xl_type != XL_TYPE_905B.
2120 while (sc->xl_cdata.xl_tx_head != NULL) {
2121 cur_tx = sc->xl_cdata.xl_tx_head;
2123 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2126 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2127 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2128 BUS_DMASYNC_POSTWRITE);
2129 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2130 m_freem(cur_tx->xl_mbuf);
2131 cur_tx->xl_mbuf = NULL;
2133 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2135 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2136 sc->xl_cdata.xl_tx_free = cur_tx;
2139 if (sc->xl_cdata.xl_tx_head == NULL) {
2140 sc->xl_wdog_timer = 0;
2141 sc->xl_cdata.xl_tx_tail = NULL;
2143 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2144 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2145 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2146 sc->xl_cdata.xl_tx_head->xl_phys);
2147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2153 xl_txeof_90xB(struct xl_softc *sc)
2155 struct xl_chain *cur_tx = NULL;
2156 struct ifnet *ifp = sc->xl_ifp;
2161 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2162 BUS_DMASYNC_POSTREAD);
2163 idx = sc->xl_cdata.xl_tx_cons;
2164 while (idx != sc->xl_cdata.xl_tx_prod) {
2165 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2167 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2168 XL_TXSTAT_DL_COMPLETE))
2171 if (cur_tx->xl_mbuf != NULL) {
2172 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2173 BUS_DMASYNC_POSTWRITE);
2174 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2175 m_freem(cur_tx->xl_mbuf);
2176 cur_tx->xl_mbuf = NULL;
2181 sc->xl_cdata.xl_tx_cnt--;
2182 XL_INC(idx, XL_TX_LIST_CNT);
2185 if (sc->xl_cdata.xl_tx_cnt == 0)
2186 sc->xl_wdog_timer = 0;
2187 sc->xl_cdata.xl_tx_cons = idx;
2190 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2194 * TX 'end of channel' interrupt handler. Actually, we should
2195 * only get a 'TX complete' interrupt if there's a transmit error,
2196 * so this is really TX error handler.
2199 xl_txeoc(struct xl_softc *sc)
2205 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2206 if (txstat & XL_TXSTATUS_UNDERRUN ||
2207 txstat & XL_TXSTATUS_JABBER ||
2208 txstat & XL_TXSTATUS_RECLAIM) {
2209 device_printf(sc->xl_dev,
2210 "transmission error: 0x%02x\n", txstat);
2211 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2213 if (sc->xl_type == XL_TYPE_905B) {
2214 if (sc->xl_cdata.xl_tx_cnt) {
2218 i = sc->xl_cdata.xl_tx_cons;
2219 c = &sc->xl_cdata.xl_tx_chain[i];
2220 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2222 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2223 sc->xl_wdog_timer = 5;
2226 if (sc->xl_cdata.xl_tx_head != NULL) {
2227 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2228 sc->xl_cdata.xl_tx_head->xl_phys);
2229 sc->xl_wdog_timer = 5;
2233 * Remember to set this for the
2234 * first generation 3c90X chips.
2236 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2237 if (txstat & XL_TXSTATUS_UNDERRUN &&
2238 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2239 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2240 device_printf(sc->xl_dev,
2241 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2243 CSR_WRITE_2(sc, XL_COMMAND,
2244 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2245 if (sc->xl_type == XL_TYPE_905B) {
2246 CSR_WRITE_2(sc, XL_COMMAND,
2247 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2249 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2250 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2252 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2253 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2256 * Write an arbitrary byte to the TX_STATUS register
2257 * to clear this interrupt/error and advance to the next.
2259 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2266 struct xl_softc *sc = arg;
2267 struct ifnet *ifp = sc->xl_ifp;
2272 #ifdef DEVICE_POLLING
2273 if (ifp->if_capenable & IFCAP_POLLING) {
2280 status = CSR_READ_2(sc, XL_STATUS);
2281 if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2283 CSR_WRITE_2(sc, XL_COMMAND,
2284 XL_CMD_INTR_ACK|(status & XL_INTRS));
2285 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2288 if (status & XL_STAT_UP_COMPLETE) {
2289 if (xl_rxeof(sc) == 0) {
2290 while (xl_rx_resync(sc))
2295 if (status & XL_STAT_DOWN_COMPLETE) {
2296 if (sc->xl_type == XL_TYPE_905B)
2302 if (status & XL_STAT_TX_COMPLETE) {
2307 if (status & XL_STAT_ADFAIL) {
2308 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2313 if (status & XL_STAT_STATSOFLOW)
2314 xl_stats_update(sc);
2317 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2318 ifp->if_drv_flags & IFF_DRV_RUNNING) {
2319 if (sc->xl_type == XL_TYPE_905B)
2320 xl_start_90xB_locked(ifp);
2322 xl_start_locked(ifp);
2328 #ifdef DEVICE_POLLING
2330 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2332 struct xl_softc *sc = ifp->if_softc;
2336 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2337 rx_npkts = xl_poll_locked(ifp, cmd, count);
2343 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2345 struct xl_softc *sc = ifp->if_softc;
2350 sc->rxcycles = count;
2351 rx_npkts = xl_rxeof(sc);
2352 if (sc->xl_type == XL_TYPE_905B)
2357 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2358 if (sc->xl_type == XL_TYPE_905B)
2359 xl_start_90xB_locked(ifp);
2361 xl_start_locked(ifp);
2364 if (cmd == POLL_AND_CHECK_STATUS) {
2367 status = CSR_READ_2(sc, XL_STATUS);
2368 if (status & XL_INTRS && status != 0xFFFF) {
2369 CSR_WRITE_2(sc, XL_COMMAND,
2370 XL_CMD_INTR_ACK|(status & XL_INTRS));
2372 if (status & XL_STAT_TX_COMPLETE) {
2377 if (status & XL_STAT_ADFAIL) {
2378 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2382 if (status & XL_STAT_STATSOFLOW)
2383 xl_stats_update(sc);
2388 #endif /* DEVICE_POLLING */
2393 struct xl_softc *sc = xsc;
2394 struct mii_data *mii;
2398 if (sc->xl_miibus != NULL) {
2399 mii = device_get_softc(sc->xl_miibus);
2403 xl_stats_update(sc);
2404 if (xl_watchdog(sc) == EJUSTRETURN)
2407 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2411 xl_stats_update(struct xl_softc *sc)
2413 struct ifnet *ifp = sc->xl_ifp;
2414 struct xl_stats xl_stats;
2420 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2422 p = (u_int8_t *)&xl_stats;
2424 /* Read all the stats registers. */
2427 for (i = 0; i < 16; i++)
2428 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2430 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2432 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2433 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2436 * Boomerang and cyclone chips have an extra stats counter
2437 * in window 4 (BadSSD). We have to read this too in order
2438 * to clear out all the stats registers and avoid a statsoflow
2442 CSR_READ_1(sc, XL_W4_BADSSD);
2447 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2448 * pointers to the fragment pointers.
2451 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2454 struct ifnet *ifp = sc->xl_ifp;
2455 int error, i, nseg, total_len;
2460 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2461 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2463 if (error && error != EFBIG) {
2464 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2469 * Handle special case: we used up all 63 fragments,
2470 * but we have more mbufs left in the chain. Copy the
2471 * data into an mbuf cluster. Note that we don't
2472 * bother clearing the values in the other fragment
2473 * pointers/counters; it wouldn't gain us anything,
2474 * and would waste cycles.
2477 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS);
2478 if (m_new == NULL) {
2485 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2486 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2490 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2495 KASSERT(nseg <= XL_MAXFRAGS,
2496 ("%s: too many DMA segments (%d)", __func__, nseg));
2502 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2505 for (i = 0; i < nseg; i++) {
2506 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2507 ("segment size too large"));
2508 c->xl_ptr->xl_frag[i].xl_addr =
2509 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2510 c->xl_ptr->xl_frag[i].xl_len =
2511 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2512 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2514 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2516 if (sc->xl_type == XL_TYPE_905B) {
2517 status = XL_TXSTAT_RND_DEFEAT;
2519 #ifndef XL905B_TXCSUM_BROKEN
2520 if ((*m_head)->m_pkthdr.csum_flags) {
2521 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2522 status |= XL_TXSTAT_IPCKSUM;
2523 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2524 status |= XL_TXSTAT_TCPCKSUM;
2525 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2526 status |= XL_TXSTAT_UDPCKSUM;
2531 c->xl_ptr->xl_status = htole32(status);
2532 c->xl_ptr->xl_next = 0;
2534 c->xl_mbuf = *m_head;
2539 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2540 * to the mbuf data regions directly in the transmit lists. We also save a
2541 * copy of the pointers since the transmit list fragment pointers are
2542 * physical addresses.
2546 xl_start(struct ifnet *ifp)
2548 struct xl_softc *sc = ifp->if_softc;
2552 if (sc->xl_type == XL_TYPE_905B)
2553 xl_start_90xB_locked(ifp);
2555 xl_start_locked(ifp);
2561 xl_start_locked(struct ifnet *ifp)
2563 struct xl_softc *sc = ifp->if_softc;
2564 struct mbuf *m_head;
2565 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2566 struct xl_chain *prev_tx;
2571 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2575 * Check for an available queue slot. If there are none,
2578 if (sc->xl_cdata.xl_tx_free == NULL) {
2581 if (sc->xl_cdata.xl_tx_free == NULL) {
2582 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2587 start_tx = sc->xl_cdata.xl_tx_free;
2589 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2590 sc->xl_cdata.xl_tx_free != NULL;) {
2591 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2595 /* Pick a descriptor off the free list. */
2597 cur_tx = sc->xl_cdata.xl_tx_free;
2599 /* Pack the data into the descriptor. */
2600 error = xl_encap(sc, cur_tx, &m_head);
2605 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2606 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2610 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2611 cur_tx->xl_next = NULL;
2613 /* Chain it together. */
2615 prev->xl_next = cur_tx;
2616 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2621 * If there's a BPF listener, bounce a copy of this frame
2624 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2628 * If there are no packets queued, bail.
2634 * Place the request for the upload interrupt
2635 * in the last descriptor in the chain. This way, if
2636 * we're chaining several packets at once, we'll only
2637 * get an interrupt once for the whole chain rather than
2638 * once for each packet.
2640 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2643 * Queue the packets. If the TX channel is clear, update
2644 * the downlist pointer register.
2646 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2649 if (sc->xl_cdata.xl_tx_head != NULL) {
2650 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2651 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2652 htole32(start_tx->xl_phys);
2653 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2654 htole32(~XL_TXSTAT_DL_INTR);
2655 sc->xl_cdata.xl_tx_tail = cur_tx;
2657 sc->xl_cdata.xl_tx_head = start_tx;
2658 sc->xl_cdata.xl_tx_tail = cur_tx;
2660 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2661 BUS_DMASYNC_PREWRITE);
2662 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2663 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2665 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2670 * Set a timeout in case the chip goes out to lunch.
2672 sc->xl_wdog_timer = 5;
2675 * XXX Under certain conditions, usually on slower machines
2676 * where interrupts may be dropped, it's possible for the
2677 * adapter to chew up all the buffers in the receive ring
2678 * and stall, without us being able to do anything about it.
2679 * To guard against this, we need to make a pass over the
2680 * RX queue to make sure there aren't any packets pending.
2681 * Doing it here means we can flush the receive ring at the
2682 * same time the chip is DMAing the transmit descriptors we
2685 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2686 * nature of their chips in all their marketing literature;
2687 * we may as well take advantage of it. :)
2689 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2693 xl_start_90xB_locked(struct ifnet *ifp)
2695 struct xl_softc *sc = ifp->if_softc;
2696 struct mbuf *m_head;
2697 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2698 struct xl_chain *prev_tx;
2703 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2707 idx = sc->xl_cdata.xl_tx_prod;
2708 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2710 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2711 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2712 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2713 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2717 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2722 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2724 /* Pack the data into the descriptor. */
2725 error = xl_encap(sc, cur_tx, &m_head);
2730 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2731 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2735 /* Chain it together. */
2737 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2741 * If there's a BPF listener, bounce a copy of this frame
2744 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2746 XL_INC(idx, XL_TX_LIST_CNT);
2747 sc->xl_cdata.xl_tx_cnt++;
2751 * If there are no packets queued, bail.
2757 * Place the request for the upload interrupt
2758 * in the last descriptor in the chain. This way, if
2759 * we're chaining several packets at once, we'll only
2760 * get an interrupt once for the whole chain rather than
2761 * once for each packet.
2763 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2765 /* Start transmission */
2766 sc->xl_cdata.xl_tx_prod = idx;
2767 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2768 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2769 BUS_DMASYNC_PREWRITE);
2772 * Set a timeout in case the chip goes out to lunch.
2774 sc->xl_wdog_timer = 5;
2780 struct xl_softc *sc = xsc;
2788 xl_init_locked(struct xl_softc *sc)
2790 struct ifnet *ifp = sc->xl_ifp;
2792 struct mii_data *mii = NULL;
2796 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2799 * Cancel pending I/O and free all RX/TX buffers.
2803 /* Reset the chip to a known state. */
2806 if (sc->xl_miibus == NULL) {
2807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2814 if (sc->xl_miibus != NULL)
2815 mii = device_get_softc(sc->xl_miibus);
2818 * Clear WOL status and disable all WOL feature as WOL
2819 * would interfere Rx operation under normal environments.
2821 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2823 CSR_READ_2(sc, XL_W7_BM_PME);
2824 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2826 /* Init our MAC address */
2828 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2829 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2830 IF_LLADDR(sc->xl_ifp)[i]);
2833 /* Clear the station mask. */
2834 for (i = 0; i < 3; i++)
2835 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2837 /* Reset TX and RX. */
2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2843 /* Init circular RX list. */
2844 error = xl_list_rx_init(sc);
2846 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2852 /* Init TX descriptors. */
2853 if (sc->xl_type == XL_TYPE_905B)
2854 error = xl_list_tx_init_90xB(sc);
2856 error = xl_list_tx_init(sc);
2858 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2865 * Set the TX freethresh value.
2866 * Note that this has no effect on 3c905B "cyclone"
2867 * cards but is required for 3c900/3c905 "boomerang"
2868 * cards in order to enable the download engine.
2870 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2872 /* Set the TX start threshold for best performance. */
2873 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2876 * If this is a 3c905B, also set the tx reclaim threshold.
2877 * This helps cut down on the number of tx reclaim errors
2878 * that could happen on a busy network. The chip multiplies
2879 * the register value by 16 to obtain the actual threshold
2880 * in bytes, so we divide by 16 when setting the value here.
2881 * The existing threshold value can be examined by reading
2882 * the register at offset 9 in window 5.
2884 if (sc->xl_type == XL_TYPE_905B) {
2885 CSR_WRITE_2(sc, XL_COMMAND,
2886 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2889 /* Set RX filter bits. */
2893 * Load the address of the RX list. We have to
2894 * stall the upload engine before we can manipulate
2895 * the uplist pointer register, then unstall it when
2896 * we're finished. We also have to wait for the
2897 * stall command to complete before proceeding.
2898 * Note that we have to do this after any RX resets
2899 * have completed since the uplist register is cleared
2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2904 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2908 if (sc->xl_type == XL_TYPE_905B) {
2909 /* Set polling interval */
2910 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2911 /* Load the address of the TX list */
2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2914 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2915 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2921 * If the coax transceiver is on, make sure to enable
2922 * the DC-DC converter.
2925 if (sc->xl_xcvr == XL_XCVR_COAX)
2926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2931 * increase packet size to allow reception of 802.1q or ISL packets.
2932 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2933 * control register. For 3c90xB/C chips, use the RX packet size
2937 if (sc->xl_type == XL_TYPE_905B)
2938 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2941 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2942 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2943 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2946 /* Clear out the stats counters. */
2947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2948 xl_stats_update(sc);
2950 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2951 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2954 * Enable interrupts.
2956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2958 #ifdef DEVICE_POLLING
2959 /* Disable interrupts if we are polling. */
2960 if (ifp->if_capenable & IFCAP_POLLING)
2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2965 if (sc->xl_flags & XL_FLAG_FUNCREG)
2966 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2968 /* Set the RX early threshold */
2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2970 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2972 /* Enable receiver and transmitter. */
2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2975 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2978 /* XXX Downcall to miibus. */
2982 /* Select window 7 for normal operations. */
2985 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2986 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2988 sc->xl_wdog_timer = 0;
2989 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2993 * Set media options.
2996 xl_ifmedia_upd(struct ifnet *ifp)
2998 struct xl_softc *sc = ifp->if_softc;
2999 struct ifmedia *ifm = NULL;
3000 struct mii_data *mii = NULL;
3004 if (sc->xl_miibus != NULL)
3005 mii = device_get_softc(sc->xl_miibus);
3009 ifm = &mii->mii_media;
3011 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3016 xl_setmode(sc, ifm->ifm_media);
3021 if (sc->xl_media & XL_MEDIAOPT_MII ||
3022 sc->xl_media & XL_MEDIAOPT_BTX ||
3023 sc->xl_media & XL_MEDIAOPT_BT4) {
3024 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3027 xl_setmode(sc, ifm->ifm_media);
3036 * Report current media status.
3039 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3041 struct xl_softc *sc = ifp->if_softc;
3043 u_int16_t status = 0;
3044 struct mii_data *mii = NULL;
3048 if (sc->xl_miibus != NULL)
3049 mii = device_get_softc(sc->xl_miibus);
3052 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3055 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3056 icfg >>= XL_ICFG_CONNECTOR_BITS;
3058 ifmr->ifm_active = IFM_ETHER;
3059 ifmr->ifm_status = IFM_AVALID;
3061 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3062 ifmr->ifm_status |= IFM_ACTIVE;
3066 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3067 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3068 ifmr->ifm_active |= IFM_FDX;
3070 ifmr->ifm_active |= IFM_HDX;
3073 if (sc->xl_type == XL_TYPE_905B &&
3074 sc->xl_media == XL_MEDIAOPT_10FL) {
3075 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3076 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3077 ifmr->ifm_active |= IFM_FDX;
3079 ifmr->ifm_active |= IFM_HDX;
3081 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3084 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3087 * XXX MII and BTX/AUTO should be separate cases.
3090 case XL_XCVR_100BTX:
3095 ifmr->ifm_active = mii->mii_media_active;
3096 ifmr->ifm_status = mii->mii_media_status;
3099 case XL_XCVR_100BFX:
3100 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3103 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3111 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3113 struct xl_softc *sc = ifp->if_softc;
3114 struct ifreq *ifr = (struct ifreq *) data;
3115 int error = 0, mask;
3116 struct mii_data *mii = NULL;
3121 if (ifp->if_flags & IFF_UP) {
3122 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3123 (ifp->if_flags ^ sc->xl_if_flags) &
3124 (IFF_PROMISC | IFF_ALLMULTI))
3129 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3132 sc->xl_if_flags = ifp->if_flags;
3137 /* XXX Downcall from if_addmulti() possibly with locks held. */
3139 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3145 if (sc->xl_miibus != NULL)
3146 mii = device_get_softc(sc->xl_miibus);
3148 error = ifmedia_ioctl(ifp, ifr,
3149 &sc->ifmedia, command);
3151 error = ifmedia_ioctl(ifp, ifr,
3152 &mii->mii_media, command);
3155 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3156 #ifdef DEVICE_POLLING
3157 if ((mask & IFCAP_POLLING) != 0 &&
3158 (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3159 ifp->if_capenable ^= IFCAP_POLLING;
3160 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3161 error = ether_poll_register(xl_poll, ifp);
3165 /* Disable interrupts */
3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3167 ifp->if_capenable |= IFCAP_POLLING;
3170 error = ether_poll_deregister(ifp);
3171 /* Enable interrupts. */
3173 CSR_WRITE_2(sc, XL_COMMAND,
3174 XL_CMD_INTR_ACK | 0xFF);
3175 CSR_WRITE_2(sc, XL_COMMAND,
3176 XL_CMD_INTR_ENB | XL_INTRS);
3177 if (sc->xl_flags & XL_FLAG_FUNCREG)
3178 bus_space_write_4(sc->xl_ftag,
3179 sc->xl_fhandle, 4, 0x8000);
3183 #endif /* DEVICE_POLLING */
3185 if ((mask & IFCAP_TXCSUM) != 0 &&
3186 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3187 ifp->if_capenable ^= IFCAP_TXCSUM;
3188 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3189 ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3191 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3193 if ((mask & IFCAP_RXCSUM) != 0 &&
3194 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3195 ifp->if_capenable ^= IFCAP_RXCSUM;
3196 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3197 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3198 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3202 error = ether_ioctl(ifp, command, data);
3210 xl_watchdog(struct xl_softc *sc)
3212 struct ifnet *ifp = sc->xl_ifp;
3213 u_int16_t status = 0;
3218 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3224 if (sc->xl_type == XL_TYPE_905B) {
3226 if (sc->xl_cdata.xl_tx_cnt == 0)
3230 if (sc->xl_cdata.xl_tx_head == NULL)
3234 device_printf(sc->xl_dev,
3235 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3241 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3242 device_printf(sc->xl_dev, "watchdog timeout\n");
3244 if (status & XL_MEDIASTAT_CARRIER)
3245 device_printf(sc->xl_dev,
3246 "no carrier - transceiver cable problem?\n");
3248 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3251 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3252 if (sc->xl_type == XL_TYPE_905B)
3253 xl_start_90xB_locked(ifp);
3255 xl_start_locked(ifp);
3258 return (EJUSTRETURN);
3262 * Stop the adapter and free any mbufs allocated to the
3266 xl_stop(struct xl_softc *sc)
3269 struct ifnet *ifp = sc->xl_ifp;
3273 sc->xl_wdog_timer = 0;
3275 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3276 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3277 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3280 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3281 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3285 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3291 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3293 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3294 if (sc->xl_flags & XL_FLAG_FUNCREG)
3295 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3297 /* Stop the stats updater. */
3298 callout_stop(&sc->xl_tick_callout);
3301 * Free data in the RX lists.
3303 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3304 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3305 bus_dmamap_unload(sc->xl_mtag,
3306 sc->xl_cdata.xl_rx_chain[i].xl_map);
3307 bus_dmamap_destroy(sc->xl_mtag,
3308 sc->xl_cdata.xl_rx_chain[i].xl_map);
3309 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3310 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3313 if (sc->xl_ldata.xl_rx_list != NULL)
3314 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3316 * Free the TX list buffers.
3318 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3319 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3320 bus_dmamap_unload(sc->xl_mtag,
3321 sc->xl_cdata.xl_tx_chain[i].xl_map);
3322 bus_dmamap_destroy(sc->xl_mtag,
3323 sc->xl_cdata.xl_tx_chain[i].xl_map);
3324 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3325 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3328 if (sc->xl_ldata.xl_tx_list != NULL)
3329 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3331 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3335 * Stop all chip I/O so that the kernel's probe routines don't
3336 * get confused by errant DMAs when rebooting.
3339 xl_shutdown(device_t dev)
3342 return (xl_suspend(dev));
3346 xl_suspend(device_t dev)
3348 struct xl_softc *sc;
3350 sc = device_get_softc(dev);
3361 xl_resume(device_t dev)
3363 struct xl_softc *sc;
3366 sc = device_get_softc(dev);
3371 if (ifp->if_flags & IFF_UP) {
3372 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3382 xl_setwol(struct xl_softc *sc)
3385 u_int16_t cfg, pmstat;
3387 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3392 /* Clear any pending PME events. */
3393 CSR_READ_2(sc, XL_W7_BM_PME);
3395 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3396 cfg |= XL_BM_PME_MAGIC;
3397 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3399 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3400 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3402 pmstat = pci_read_config(sc->xl_dev,
3403 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3404 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3405 pmstat |= PCIM_PSTAT_PMEENABLE;
3407 pmstat &= ~PCIM_PSTAT_PMEENABLE;
3408 pci_write_config(sc->xl_dev,
3409 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);