2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_auto_eoi.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
49 #include <machine/cpufunc.h>
50 #include <machine/frame.h>
51 #include <machine/intr_machdep.h>
52 #include <machine/md_var.h>
53 #include <machine/resource.h>
54 #include <machine/segments.h>
56 #include <dev/ic/i8259.h>
57 #include <i386/isa/icu.h>
59 #include <pc98/cbus/cbus.h>
61 #include <i386/isa/isa.h>
63 #include <isa/isavar.h>
69 * PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and
70 * PC-AT machines wire the slave PIC to pin 2 on the master PIC.
79 * Determine the base master and slave modes not including auto EOI support.
80 * All machines that FreeBSD supports use 8086 mode.
84 * PC-98 machines do not support auto EOI on the second PIC. Also, it
85 * seems that PC-98 machine PICs use buffered mode, and the master PIC
86 * uses special fully nested mode.
88 #define BASE_MASTER_MODE (ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
89 #define BASE_SLAVE_MODE (ICW4_BUF | ICW4_8086)
91 #define BASE_MASTER_MODE ICW4_8086
92 #define BASE_SLAVE_MODE ICW4_8086
95 /* Enable automatic EOI if requested. */
97 #define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
99 #define MASTER_MODE BASE_MASTER_MODE
102 #define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
104 #define SLAVE_MODE BASE_SLAVE_MODE
107 #define IRQ_MASK(irq) (1 << (irq))
108 #define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
110 #define NUM_ISA_IRQS 16
112 static void atpic_init(void *dummy);
114 unsigned int imen; /* XXX */
117 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
118 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
119 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
120 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
121 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
122 IDTVEC(atpic_intr15);
124 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
126 #define ATPIC(io, base, eoi, imenptr) \
127 { { atpic_enable_source, atpic_disable_source, (eoi), \
128 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
129 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
130 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
133 #define INTSRC(irq) \
134 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
145 struct atpic_intsrc {
146 struct intsrc at_intsrc;
148 int at_irq; /* Relative to PIC base. */
149 enum intr_trigger at_trigger;
151 u_long at_straycount;
154 static void atpic_enable_source(struct intsrc *isrc);
155 static void atpic_disable_source(struct intsrc *isrc, int eoi);
156 static void atpic_eoi_master(struct intsrc *isrc);
157 static void atpic_eoi_slave(struct intsrc *isrc);
158 static void atpic_enable_intr(struct intsrc *isrc);
159 static void atpic_disable_intr(struct intsrc *isrc);
160 static int atpic_vector(struct intsrc *isrc);
161 static void atpic_resume(struct pic *pic);
162 static int atpic_source_pending(struct intsrc *isrc);
163 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
164 enum intr_polarity pol);
165 static void atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
166 static void i8259_init(struct atpic *pic, int slave);
168 static struct atpic atpics[] = {
169 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
170 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
173 static struct atpic_intsrc atintrs[] = {
192 CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
195 _atpic_eoi_master(struct intsrc *isrc)
198 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
199 ("%s: mismatched pic", __func__));
201 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
206 * The data sheet says no auto-EOI on slave, but it sometimes works.
207 * So, if AUTO_EOI_2 is enabled, we use it.
210 _atpic_eoi_slave(struct intsrc *isrc)
213 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
214 ("%s: mismatched pic", __func__));
216 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
218 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
224 atpic_enable_source(struct intsrc *isrc)
226 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
227 struct atpic *ap = (struct atpic *)isrc->is_pic;
229 mtx_lock_spin(&icu_lock);
230 if (*ap->at_imen & IMEN_MASK(ai)) {
231 *ap->at_imen &= ~IMEN_MASK(ai);
232 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
234 mtx_unlock_spin(&icu_lock);
238 atpic_disable_source(struct intsrc *isrc, int eoi)
240 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
241 struct atpic *ap = (struct atpic *)isrc->is_pic;
243 mtx_lock_spin(&icu_lock);
244 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
245 *ap->at_imen |= IMEN_MASK(ai);
246 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
250 * Take care to call these functions directly instead of through
251 * a function pointer. All of the referenced variables should
252 * still be hot in the cache.
254 if (eoi == PIC_EOI) {
255 if (isrc->is_pic == &atpics[MASTER].at_pic)
256 _atpic_eoi_master(isrc);
258 _atpic_eoi_slave(isrc);
261 mtx_unlock_spin(&icu_lock);
265 atpic_eoi_master(struct intsrc *isrc)
268 mtx_lock_spin(&icu_lock);
269 _atpic_eoi_master(isrc);
270 mtx_unlock_spin(&icu_lock);
275 atpic_eoi_slave(struct intsrc *isrc)
278 mtx_lock_spin(&icu_lock);
279 _atpic_eoi_slave(isrc);
280 mtx_unlock_spin(&icu_lock);
285 atpic_enable_intr(struct intsrc *isrc)
290 atpic_disable_intr(struct intsrc *isrc)
296 atpic_vector(struct intsrc *isrc)
298 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
299 struct atpic *ap = (struct atpic *)isrc->is_pic;
301 return (IRQ(ap, ai));
305 atpic_source_pending(struct intsrc *isrc)
307 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
308 struct atpic *ap = (struct atpic *)isrc->is_pic;
310 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
314 atpic_resume(struct pic *pic)
316 struct atpic *ap = (struct atpic *)pic;
318 i8259_init(ap, ap == &atpics[SLAVE]);
320 if (ap == &atpics[SLAVE] && elcr_found)
326 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
327 enum intr_polarity pol)
329 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
332 /* Map conforming values to edge/hi and sanity check the values. */
333 if (trig == INTR_TRIGGER_CONFORM)
334 trig = INTR_TRIGGER_EDGE;
335 if (pol == INTR_POLARITY_CONFORM)
336 pol = INTR_POLARITY_HIGH;
337 vector = atpic_vector(isrc);
338 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
339 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
341 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
342 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
343 pol == INTR_POLARITY_HIGH ? "high" : "low");
347 /* If there is no change, just return. */
348 if (ai->at_trigger == trig)
352 if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) &&
353 trig == INTR_TRIGGER_LEVEL) {
356 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
363 * Certain IRQs can never be level/lo, so don't try to set them
364 * that way if asked. At least some ELCR registers ignore setting
365 * these bits as well.
367 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
368 trig == INTR_TRIGGER_LEVEL) {
371 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
377 printf("atpic: No ELCR to configure IRQ%u as %s\n",
378 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
383 printf("atpic: Programming IRQ%u as %s\n", vector,
384 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
385 mtx_lock_spin(&icu_lock);
386 elcr_write_trigger(atpic_vector(isrc), trig);
387 ai->at_trigger = trig;
388 mtx_unlock_spin(&icu_lock);
394 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
398 * 8259A's are only used in UP in which case all interrupts always
399 * go to the sole CPU and this function shouldn't even be called.
401 panic("%s: bad cookie", __func__);
405 i8259_init(struct atpic *pic, int slave)
409 /* Reset the PIC and program with next four bytes. */
410 mtx_lock_spin(&icu_lock);
412 /* MCA uses level triggered interrupts. */
414 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
417 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
418 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
421 outb(imr_addr, pic->at_intbase);
424 * Setup slave links. For the master pic, indicate what line
425 * the slave is configured on. For the slave indicate
426 * which line on the master we are connected to.
429 outb(imr_addr, ICU_SLAVEID);
431 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
435 outb(imr_addr, SLAVE_MODE);
437 outb(imr_addr, MASTER_MODE);
439 /* Set interrupt enable mask. */
440 outb(imr_addr, *pic->at_imen);
442 /* Reset is finished, default to IRR on read. */
443 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
446 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
448 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
450 mtx_unlock_spin(&icu_lock);
456 struct atpic_intsrc *ai;
459 /* Start off with all interrupts disabled. */
461 i8259_init(&atpics[MASTER], 0);
462 i8259_init(&atpics[SLAVE], 1);
463 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
465 /* Install low-level interrupt handlers for all of our IRQs. */
466 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
467 if (i == ICU_SLAVEID)
469 ai->at_intsrc.is_count = &ai->at_count;
470 ai->at_intsrc.is_straycount = &ai->at_straycount;
471 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
472 ai->at_irq, ai->at_intr, SDT_SYS386IGT, SEL_KPL,
473 GSEL(GCODE_SEL, SEL_KPL));
477 /* For MCA systems, all interrupts are level triggered. */
479 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
480 ai->at_trigger = INTR_TRIGGER_LEVEL;
485 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
491 ai->at_trigger = INTR_TRIGGER_EDGE;
494 ai->at_trigger = INTR_TRIGGER_LEVEL;
499 * Look for an ELCR. If we find one, update the trigger modes.
500 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
501 * edge triggered and that everything else is level triggered.
502 * We only use the trigger information to reprogram the ELCR if
503 * we have one and as an optimization to avoid masking edge
504 * triggered interrupts. For the case that we don't have an ELCR,
505 * it doesn't hurt to mask an edge triggered interrupt, so we
506 * assume level trigger for any interrupt that we aren't sure is
510 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
511 ai->at_trigger = elcr_read_trigger(i);
513 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
520 ai->at_trigger = INTR_TRIGGER_EDGE;
523 ai->at_trigger = INTR_TRIGGER_LEVEL;
531 atpic_init(void *dummy __unused)
533 struct atpic_intsrc *ai;
537 * Register our PICs, even if we aren't going to use any of their
538 * pins so that they are suspended and resumed.
540 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
541 intr_register_pic(&atpics[1].at_pic) != 0)
542 panic("Unable to register ATPICs");
545 * If any of the ISA IRQs have an interrupt source already, then
546 * assume that the APICs are being used and don't register any
547 * of our interrupt sources. This makes sure we don't accidentally
548 * use mixed mode. The "accidental" use could otherwise occur on
549 * machines that route the ACPI SCI interrupt to a different ISA
550 * IRQ (at least one machines routes it to IRQ 13) thus disabling
551 * that APIC ISA routing and allowing the ATPIC source for that IRQ
552 * to leak through. We used to depend on this feature for routing
553 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
555 for (i = 0; i < NUM_ISA_IRQS; i++)
556 if (intr_lookup_source(i) != NULL)
559 /* Loop through all interrupt sources and add them. */
560 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
561 if (i == ICU_SLAVEID)
563 intr_register_source(&ai->at_intsrc);
566 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL);
569 atpic_handle_intr(u_int vector, struct trapframe *frame)
573 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
574 isrc = &atintrs[vector].at_intsrc;
577 * If we don't have an event, see if this is a spurious
580 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
584 * Read the ISR register to see if IRQ 7/15 is really
585 * pending. Reset read register back to IRR when done.
587 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
588 mtx_lock_spin(&icu_lock);
589 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
591 outb(port, OCW3_SEL | OCW3_RR);
592 mtx_unlock_spin(&icu_lock);
593 if ((isr & IRQ_MASK(7)) == 0)
596 intr_execute_handlers(isrc, frame);
601 * Bus attachment for the ISA PIC.
603 static struct isa_pnp_id atpic_ids[] = {
604 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
609 atpic_probe(device_t dev)
613 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
620 * We might be granted IRQ 2, as this is typically consumed by chaining
621 * between the two PIC components. If we're using the APIC, however,
622 * this may not be the case, and as such we should free the resource.
625 * The generic ISA attachment code will handle allocating any other resources
626 * that we don't explicitly claim here.
629 atpic_attach(device_t dev)
631 struct resource *res;
634 /* Try to allocate our IRQ and then free it. */
636 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
638 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
642 static device_method_t atpic_methods[] = {
643 /* Device interface */
644 DEVMETHOD(device_probe, atpic_probe),
645 DEVMETHOD(device_attach, atpic_attach),
646 DEVMETHOD(device_detach, bus_generic_detach),
647 DEVMETHOD(device_shutdown, bus_generic_shutdown),
648 DEVMETHOD(device_suspend, bus_generic_suspend),
649 DEVMETHOD(device_resume, bus_generic_resume),
653 static driver_t atpic_driver = {
659 static devclass_t atpic_devclass;
661 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
663 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
667 * Return a bitmap of the current interrupt requests. This is 8259-specific
668 * and is only suitable for use at probe time.
671 isa_irq_pending(void)
678 return ((irr2 << 8) | irr1);