1 /***********************license start***************
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40 #ifndef _CVMX_CONFIG_H
41 #define _CVMX_CONFIG_H
45 #include <sys/types.h>
46 #include <sys/param.h>
47 #include <sys/systm.h>
53 #include <machine/pmap.h>
54 #include <machine/stdarg.h>
58 #define CVMX_DONT_INCLUDE_CONFIG
60 /* Define to enable the use of simple executive packet output functions.
61 ** For packet I/O setup enable the helper functions below.
63 #define CVMX_ENABLE_PKO_FUNCTIONS
65 /* Define to enable the use of simple executive helper functions. These
66 ** include many harware setup functions. See cvmx-helper.[ch] for
69 #define CVMX_ENABLE_HELPER_FUNCTIONS
71 /* CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve before
72 ** the beginning of the packet. If necessary, override the default
73 ** here. See the IPD section of the hardware manual for MBUFF SKIP
75 #define CVMX_HELPER_FIRST_MBUFF_SKIP 184
77 /* CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve in each
78 ** chained packet element. If necessary, override the default here */
79 #define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
81 /* CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is enabled
82 ** for all input ports. This controls if IPD sends backpressure to all ports if
83 ** Octeon's FPA pools don't have enough packet or work queue entries. Even when
84 ** this is off, it is still possible to get backpressure from individual
85 ** hardware ports. When configuring backpressure, also check
86 ** CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override the default
88 #define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
90 /* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
91 ** function. Once it is enabled the hardware starts accepting packets. You
92 ** might want to skip the IPD enable if configuration changes are need
93 ** from the default helper setup. If necessary, override the default here */
94 #define CVMX_HELPER_ENABLE_IPD 1
96 /* CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
97 ** to incoming packets. */
98 #define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
100 /* The following select which fields are used by the PIP to generate
104 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0
105 #define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0
106 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0
107 #define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0
108 #define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0
109 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0
110 #define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0
111 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0
112 #define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0
113 #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0
114 #define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1
116 /* Select skip mode for input ports */
117 #define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2
119 /* Define the number of queues per output port */
120 #define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0 1
121 #define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1 1
123 /* Configure PKO to use per-core queues (PKO lockless operation).
124 ** Please see the related SDK documentation for PKO that illustrates
125 ** how to enable and configure this option. */
126 //#define CVMX_ENABLE_PKO_LOCKLESS_OPERATION 1
127 //#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 8
128 //#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 8
130 /* Force backpressure to be disabled. This overrides all other
131 ** backpressure configuration */
132 #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 1
134 /* Disable the SPI4000's processing of backpressure packets and backpressure
135 ** generation. When this is 1, the SPI4000 will not stop sending packets when
136 ** receiving backpressure. It will also not generate backpressure packets when
137 ** its internal FIFOs are full. */
138 #define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE 1
140 /* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI initialization
141 ** routines wait for SPI training. You can override the value using
142 ** executive-config.h if necessary */
143 #define CVMX_HELPER_SPI_TIMEOUT 10
145 /* Select the number of low latency memory ports (interfaces) that
146 ** will be configured. Valid values are 1 and 2.
148 #define CVMX_LLM_CONFIG_NUM_PORTS 2
150 /* Enable the fix for PKI-100 errata ("Size field is 8 too large in WQE and next
151 ** pointers"). If CVMX_ENABLE_LEN_M8_FIX is set to 0, the fix for this errata will
153 ** 0: Fix is not enabled
154 ** 1: Fix is enabled, if supported by hardware
156 #define CVMX_ENABLE_LEN_M8_FIX 1
158 #if defined(CVMX_ENABLE_HELPER_FUNCTIONS) && !defined(CVMX_ENABLE_PKO_FUNCTIONS)
159 #define CVMX_ENABLE_PKO_FUNCTIONS
162 /* Enable debug and informational printfs */
163 #define CVMX_CONFIG_ENABLE_DEBUG_PRINTS 1
165 /************************* Config Specific Defines ************************/
166 #define CVMX_LLM_NUM_PORTS 1
167 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 /**< PKO queues per port for interface 0 (ports 0-15) */
168 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 /**< PKO queues per port for interface 1 (ports 16-31) */
169 #define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 /**< Limit on the number of PKO ports enabled for interface 0 */
170 #define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 /**< Limit on the number of PKO ports enabled for interface 1 */
171 #define CVMX_PKO_QUEUES_PER_PORT_PCI 1 /**< PKO queues per port for PCI (ports 32-35) */
172 #define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 /**< PKO queues per port for Loop devices (ports 36-39) */
174 /************************* FPA allocation *********************************/
175 /* Pool sizes in bytes, must be multiple of a cache line */
176 #define CVMX_FPA_POOL_0_SIZE (15 * CVMX_CACHE_LINE_SIZE)
177 #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
178 #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
179 #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
180 #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
181 #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
182 #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
183 #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
186 #define CVMX_FPA_PACKET_POOL (0) /**< Packet buffers */
187 #define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
188 #define CVMX_FPA_WQE_POOL (1) /**< Work queue entrys */
189 #define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
190 #define CVMX_FPA_OUTPUT_BUFFER_POOL (2) /**< PKO queue command buffers */
191 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
193 /************************* FAU allocation ********************************/
194 #define CVMX_FAU_REG_END 2048
196 #define CVMX_SCR_SCRATCH 0
198 #endif /* !_CVMX_CONFIG_H */