2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/completion.h>
36 #include <linux/pci.h>
37 #include <linux/errno.h>
38 #include <linux/sched.h>
40 #include <rdma/ib_mad.h>
42 #include "mthca_dev.h"
43 #include "mthca_config_reg.h"
44 #include "mthca_cmd.h"
45 #include "mthca_memfree.h"
47 #define CMD_POLL_TOKEN 0xffff
50 HCR_IN_PARAM_OFFSET = 0x00,
51 HCR_IN_MODIFIER_OFFSET = 0x08,
52 HCR_OUT_PARAM_OFFSET = 0x0c,
53 HCR_TOKEN_OFFSET = 0x14,
54 HCR_STATUS_OFFSET = 0x18,
62 /* initialization and general commands */
68 CMD_MOD_STAT_CFG = 0x34,
69 CMD_QUERY_DEV_LIM = 0x3,
71 CMD_ENABLE_LAM = 0xff8,
72 CMD_DISABLE_LAM = 0xff7,
74 CMD_QUERY_ADAPTER = 0x6,
81 CMD_ACCESS_DDR = 0x2e,
83 CMD_UNMAP_ICM = 0xff9,
84 CMD_MAP_ICM_AUX = 0xffc,
85 CMD_UNMAP_ICM_AUX = 0xffb,
86 CMD_SET_ICM_SIZE = 0xffd,
106 CMD_RESIZE_CQ = 0x2c,
109 CMD_SW2HW_SRQ = 0x35,
110 CMD_HW2SW_SRQ = 0x36,
111 CMD_QUERY_SRQ = 0x37,
115 CMD_RST2INIT_QPEE = 0x19,
116 CMD_INIT2RTR_QPEE = 0x1a,
117 CMD_RTR2RTS_QPEE = 0x1b,
118 CMD_RTS2RTS_QPEE = 0x1c,
119 CMD_SQERR2RTS_QPEE = 0x1d,
120 CMD_2ERR_QPEE = 0x1e,
121 CMD_RTS2SQD_QPEE = 0x1f,
122 CMD_SQD2SQD_QPEE = 0x38,
123 CMD_SQD2RTS_QPEE = 0x20,
124 CMD_ERR2RST_QPEE = 0x21,
125 CMD_QUERY_QPEE = 0x22,
126 CMD_INIT2INIT_QPEE = 0x2d,
127 CMD_SUSPEND_QPEE = 0x32,
128 CMD_UNSUSPEND_QPEE = 0x33,
129 /* special QPs and management commands */
130 CMD_CONF_SPECIAL_QP = 0x23,
133 /* multicast commands */
135 CMD_WRITE_MGM = 0x26,
136 CMD_MGID_HASH = 0x27,
138 /* miscellaneous commands */
139 CMD_DIAG_RPRT = 0x30,
143 CMD_QUERY_DEBUG_MSG = 0x2a,
144 CMD_SET_DEBUG_MSG = 0x2b,
148 * According to Mellanox code, FW may be starved and never complete
149 * commands. So we can't use strict timeouts described in PRM -- we
150 * just arbitrarily select 60 seconds for now.
154 * Round up and add 1 to make sure we get the full wait time (since we
155 * will be starting in the middle of a jiffy)
158 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
159 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
160 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
161 CMD_TIME_CLASS_D = 60 * HZ
164 #define CMD_TIME_CLASS_A (60 * HZ)
165 #define CMD_TIME_CLASS_B (60 * HZ)
166 #define CMD_TIME_CLASS_C (60 * HZ)
167 #define CMD_TIME_CLASS_D (60 * HZ)
170 #define GO_BIT_TIMEOUT (HZ * 10)
172 struct mthca_cmd_context {
173 struct completion done;
181 static int fw_cmd_doorbell = 0;
182 module_param(fw_cmd_doorbell, int, 0644);
183 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
184 "(and supported by FW)");
186 static inline int go_bit(struct mthca_dev *dev)
188 return readl(dev->hcr + HCR_STATUS_OFFSET) &
189 swab32(1 << HCR_GO_BIT);
192 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
200 void __iomem *ptr = dev->cmd.dbell_map;
201 u16 *offs = dev->cmd.dbell_offsets;
203 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
205 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
207 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
209 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
211 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
213 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
215 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
217 (op_modifier << HCR_OPMOD_SHIFT) |
220 __raw_writel((__force u32) 0, ptr + offs[7]);
224 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
234 unsigned long end = jiffies + GO_BIT_TIMEOUT;
236 while (go_bit(dev) && time_before(jiffies, end))
244 * We use writel (instead of something like memcpy_toio)
245 * because writes of less than 32 bits to the HCR don't work
246 * (and some architectures such as ia64 implement memcpy_toio
247 * in terms of writeb).
249 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
250 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
251 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
252 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
253 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
254 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
256 /* __raw_writel may not order writes. */
259 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
260 (event ? (1 << HCA_E_BIT) : 0) |
261 (op_modifier << HCR_OPMOD_SHIFT) |
262 op), dev->hcr + 6 * 4);
267 static int mthca_cmd_post(struct mthca_dev *dev,
278 mutex_lock(&dev->cmd.hcr_mutex);
280 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
281 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
282 op_modifier, op, token);
284 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
285 op_modifier, op, token, event);
288 * Make sure that our HCR writes don't get mixed in with
289 * writes from another CPU starting a FW command.
293 mutex_unlock(&dev->cmd.hcr_mutex);
297 static int mthca_cmd_poll(struct mthca_dev *dev,
304 unsigned long timeout,
310 down(&dev->cmd.poll_sem);
312 err = mthca_cmd_post(dev, in_param,
313 out_param ? *out_param : 0,
314 in_modifier, op_modifier,
315 op, CMD_POLL_TOKEN, 0);
319 end = timeout + jiffies;
320 while (go_bit(dev) && time_before(jiffies, end))
330 (u64) be32_to_cpu((__force __be32)
331 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
332 (u64) be32_to_cpu((__force __be32)
333 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
335 *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
338 up(&dev->cmd.poll_sem);
342 void mthca_cmd_event(struct mthca_dev *dev,
347 struct mthca_cmd_context *context =
348 &dev->cmd.context[token & dev->cmd.token_mask];
350 /* previously timed out command completing at long last */
351 if (token != context->token)
355 context->status = status;
356 context->out_param = out_param;
358 complete(&context->done);
361 static int mthca_cmd_wait(struct mthca_dev *dev,
368 unsigned long timeout,
372 struct mthca_cmd_context *context;
374 down(&dev->cmd.event_sem);
376 spin_lock(&dev->cmd.context_lock);
377 BUG_ON(dev->cmd.free_head < 0);
378 context = &dev->cmd.context[dev->cmd.free_head];
379 context->token += dev->cmd.token_mask + 1;
380 dev->cmd.free_head = context->next;
381 spin_unlock(&dev->cmd.context_lock);
383 init_completion(&context->done);
385 err = mthca_cmd_post(dev, in_param,
386 out_param ? *out_param : 0,
387 in_modifier, op_modifier,
388 op, context->token, 1);
392 if (!wait_for_completion_timeout(&context->done, timeout)) {
397 err = context->result;
401 *status = context->status;
403 mthca_dbg(dev, "Command %02x completed with status %02x\n",
407 *out_param = context->out_param;
410 spin_lock(&dev->cmd.context_lock);
411 context->next = dev->cmd.free_head;
412 dev->cmd.free_head = context - dev->cmd.context;
413 spin_unlock(&dev->cmd.context_lock);
415 up(&dev->cmd.event_sem);
419 /* Invoke a command with an output mailbox */
420 static int mthca_cmd_box(struct mthca_dev *dev,
426 unsigned long timeout,
429 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
430 return mthca_cmd_wait(dev, in_param, &out_param, 0,
431 in_modifier, op_modifier, op,
434 return mthca_cmd_poll(dev, in_param, &out_param, 0,
435 in_modifier, op_modifier, op,
439 /* Invoke a command with no output parameter */
440 static int mthca_cmd(struct mthca_dev *dev,
445 unsigned long timeout,
448 return mthca_cmd_box(dev, in_param, 0, in_modifier,
449 op_modifier, op, timeout, status);
453 * Invoke a command with an immediate output parameter (and copy the
454 * output into the caller's out_param pointer after the command
457 static int mthca_cmd_imm(struct mthca_dev *dev,
463 unsigned long timeout,
466 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
467 return mthca_cmd_wait(dev, in_param, out_param, 1,
468 in_modifier, op_modifier, op,
471 return mthca_cmd_poll(dev, in_param, out_param, 1,
472 in_modifier, op_modifier, op,
476 int mthca_cmd_init(struct mthca_dev *dev)
478 mutex_init(&dev->cmd.hcr_mutex);
479 sema_init(&dev->cmd.poll_sem, 1);
482 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
485 mthca_err(dev, "Couldn't map command register.");
489 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
491 MTHCA_MAILBOX_SIZE, 0);
492 if (!dev->cmd.pool) {
500 void mthca_cmd_cleanup(struct mthca_dev *dev)
502 pci_pool_destroy(dev->cmd.pool);
504 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
505 iounmap(dev->cmd.dbell_map);
509 * Switch to using events to issue FW commands (should be called after
510 * event queue to command events has been initialized).
512 int mthca_cmd_use_events(struct mthca_dev *dev)
516 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
517 sizeof (struct mthca_cmd_context),
519 if (!dev->cmd.context)
522 for (i = 0; i < dev->cmd.max_cmds; ++i) {
523 dev->cmd.context[i].token = i;
524 dev->cmd.context[i].next = i + 1;
527 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
528 dev->cmd.free_head = 0;
530 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
531 spin_lock_init(&dev->cmd.context_lock);
533 for (dev->cmd.token_mask = 1;
534 dev->cmd.token_mask < dev->cmd.max_cmds;
535 dev->cmd.token_mask <<= 1)
537 --dev->cmd.token_mask;
539 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
541 down(&dev->cmd.poll_sem);
547 * Switch back to polling (used when shutting down the device)
549 void mthca_cmd_use_polling(struct mthca_dev *dev)
553 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
555 for (i = 0; i < dev->cmd.max_cmds; ++i)
556 down(&dev->cmd.event_sem);
558 kfree(dev->cmd.context);
560 up(&dev->cmd.poll_sem);
563 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
566 struct mthca_mailbox *mailbox;
568 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
570 return ERR_PTR(-ENOMEM);
572 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
575 return ERR_PTR(-ENOMEM);
581 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
586 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
590 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
595 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D, status);
597 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
598 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
599 "sladdr=%d, SPD source=%s\n",
600 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
601 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
606 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
608 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
611 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
612 u64 virt, u8 *status)
614 struct mthca_mailbox *mailbox;
615 struct mthca_icm_iter iter;
623 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
625 return PTR_ERR(mailbox);
626 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
627 pages = mailbox->buf;
629 for (mthca_icm_first(icm, &iter);
630 !mthca_icm_last(&iter);
631 mthca_icm_next(&iter)) {
633 * We have to pass pages that are aligned to their
634 * size, so find the least significant 1 in the
635 * address or size and use that as our log2 size.
637 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
638 if (lg < MTHCA_ICM_PAGE_SHIFT) {
639 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
641 (unsigned long long) mthca_icm_addr(&iter),
642 mthca_icm_size(&iter));
646 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
648 pages[nent * 2] = cpu_to_be64(virt);
652 pages[nent * 2 + 1] =
653 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
654 (lg - MTHCA_ICM_PAGE_SHIFT));
655 ts += 1 << (lg - 10);
658 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
659 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
660 CMD_TIME_CLASS_B, status);
669 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
670 CMD_TIME_CLASS_B, status);
674 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
676 case CMD_MAP_ICM_AUX:
677 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
680 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
681 tc, ts, (unsigned long long) virt - (ts << 10));
686 mthca_free_mailbox(dev, mailbox);
690 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
692 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
695 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
697 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
700 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
702 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
705 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
711 for (i = 0; i < 8; ++i)
712 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
714 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
715 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
716 "length 0x%x crosses a page boundary\n",
717 (unsigned long long) base, max_off);
721 addr = pci_resource_start(dev->pdev, 2) +
722 ((pci_resource_len(dev->pdev, 2) - 1) & base);
723 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
724 if (!dev->cmd.dbell_map)
727 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
728 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
731 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
733 struct mthca_mailbox *mailbox;
741 #define QUERY_FW_OUT_SIZE 0x100
742 #define QUERY_FW_VER_OFFSET 0x00
743 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
744 #define QUERY_FW_ERR_START_OFFSET 0x30
745 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
747 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
748 #define QUERY_FW_CMD_DB_OFFSET 0x50
749 #define QUERY_FW_CMD_DB_BASE 0x60
751 #define QUERY_FW_START_OFFSET 0x20
752 #define QUERY_FW_END_OFFSET 0x28
754 #define QUERY_FW_SIZE_OFFSET 0x00
755 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
756 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
757 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
759 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
761 return PTR_ERR(mailbox);
762 outbox = mailbox->buf;
764 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
765 CMD_TIME_CLASS_A, status);
770 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
772 * FW subminor version is at more significant bits than minor
773 * version, so swap here.
775 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
776 ((dev->fw_ver & 0xffff0000ull) >> 16) |
777 ((dev->fw_ver & 0x0000ffffull) << 16);
779 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
780 dev->cmd.max_cmds = 1 << lg;
782 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
783 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
785 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
786 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
788 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
789 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
791 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
793 mthca_dbg(dev, "FW supports commands through doorbells\n");
795 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
796 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
797 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
798 QUERY_FW_CMD_DB_OFFSET + (i << 1));
800 mthca_setup_cmd_doorbells(dev, base);
803 if (mthca_is_memfree(dev)) {
804 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
805 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
806 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
807 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
808 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
811 * Round up number of system pages needed in case
812 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
814 dev->fw.arbel.fw_pages =
815 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
816 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
818 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
819 (unsigned long long) dev->fw.arbel.clr_int_base,
820 (unsigned long long) dev->fw.arbel.eq_arm_base,
821 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
823 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
824 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
826 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
827 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
828 (unsigned long long) dev->fw.tavor.fw_start,
829 (unsigned long long) dev->fw.tavor.fw_end);
833 mthca_free_mailbox(dev, mailbox);
837 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
839 struct mthca_mailbox *mailbox;
844 #define ENABLE_LAM_OUT_SIZE 0x100
845 #define ENABLE_LAM_START_OFFSET 0x00
846 #define ENABLE_LAM_END_OFFSET 0x08
847 #define ENABLE_LAM_INFO_OFFSET 0x13
849 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
850 #define ENABLE_LAM_INFO_ECC_MASK 0x3
852 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
854 return PTR_ERR(mailbox);
855 outbox = mailbox->buf;
857 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
858 CMD_TIME_CLASS_C, status);
863 if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
866 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
867 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
868 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
870 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
871 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
872 mthca_info(dev, "FW reports that HCA-attached memory "
873 "is %s hidden; does not match PCI config\n",
874 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
877 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
878 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
880 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
881 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
882 (unsigned long long) dev->ddr_start,
883 (unsigned long long) dev->ddr_end);
886 mthca_free_mailbox(dev, mailbox);
890 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
892 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
895 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
897 struct mthca_mailbox *mailbox;
902 #define QUERY_DDR_OUT_SIZE 0x100
903 #define QUERY_DDR_START_OFFSET 0x00
904 #define QUERY_DDR_END_OFFSET 0x08
905 #define QUERY_DDR_INFO_OFFSET 0x13
907 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
908 #define QUERY_DDR_INFO_ECC_MASK 0x3
910 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
912 return PTR_ERR(mailbox);
913 outbox = mailbox->buf;
915 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
916 CMD_TIME_CLASS_A, status);
921 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
922 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
923 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
925 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
926 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
927 mthca_info(dev, "FW reports that HCA-attached memory "
928 "is %s hidden; does not match PCI config\n",
929 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
932 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
933 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
935 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
936 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
937 (unsigned long long) dev->ddr_start,
938 (unsigned long long) dev->ddr_end);
941 mthca_free_mailbox(dev, mailbox);
945 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
946 struct mthca_dev_lim *dev_lim, u8 *status)
948 struct mthca_mailbox *mailbox;
955 #define QUERY_DEV_LIM_OUT_SIZE 0x100
956 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
957 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
958 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
959 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
960 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
961 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
962 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
963 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
964 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
965 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
966 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
967 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
968 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
969 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
970 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
971 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
972 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
973 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
974 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
975 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
976 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
977 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
978 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
979 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
980 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
981 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
982 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
983 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
984 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
985 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
986 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
987 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
988 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
989 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
990 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
991 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
992 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
993 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
994 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
995 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
996 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
997 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
998 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
999 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1000 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1001 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1002 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1003 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1004 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1005 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1006 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1007 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1008 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1009 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1010 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1011 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1012 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1013 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1014 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1016 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1017 if (IS_ERR(mailbox))
1018 return PTR_ERR(mailbox);
1019 outbox = mailbox->buf;
1021 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1022 CMD_TIME_CLASS_A, status);
1027 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1028 dev_lim->reserved_qps = 1 << (field & 0xf);
1029 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1030 dev_lim->max_qps = 1 << (field & 0x1f);
1031 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1032 dev_lim->reserved_srqs = 1 << (field >> 4);
1033 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1034 dev_lim->max_srqs = 1 << (field & 0x1f);
1035 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1036 dev_lim->reserved_eecs = 1 << (field & 0xf);
1037 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1038 dev_lim->max_eecs = 1 << (field & 0x1f);
1039 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1040 dev_lim->max_cq_sz = 1 << field;
1041 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1042 dev_lim->reserved_cqs = 1 << (field & 0xf);
1043 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1044 dev_lim->max_cqs = 1 << (field & 0x1f);
1045 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1046 dev_lim->max_mpts = 1 << (field & 0x3f);
1047 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1048 dev_lim->reserved_eqs = 1 << (field & 0xf);
1049 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1050 dev_lim->max_eqs = 1 << (field & 0x7);
1051 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1052 if (mthca_is_memfree(dev))
1053 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
1054 dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
1056 dev_lim->reserved_mtts = 1 << (field >> 4);
1057 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1058 dev_lim->max_mrw_sz = 1 << field;
1059 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1060 dev_lim->reserved_mrws = 1 << (field & 0xf);
1061 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1062 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1063 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1064 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1065 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1066 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1067 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1068 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1069 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1070 dev_lim->local_ca_ack_delay = field & 0x1f;
1071 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1072 dev_lim->max_mtu = field >> 4;
1073 dev_lim->max_port_width = field & 0xf;
1074 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1075 dev_lim->max_vl = field >> 4;
1076 dev_lim->num_ports = field & 0xf;
1077 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1078 dev_lim->max_gids = 1 << (field & 0xf);
1079 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1080 dev_lim->stat_rate_support = stat_rate;
1081 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1082 dev_lim->max_pkeys = 1 << (field & 0xf);
1083 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1084 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1085 dev_lim->reserved_uars = field >> 4;
1086 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1087 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1088 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1089 dev_lim->min_page_sz = 1 << field;
1090 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1091 dev_lim->max_sg = field;
1093 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1094 dev_lim->max_desc_sz = size;
1096 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1097 dev_lim->max_qp_per_mcg = 1 << field;
1098 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1099 dev_lim->reserved_mgms = field & 0xf;
1100 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1101 dev_lim->max_mcgs = 1 << field;
1102 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1103 dev_lim->reserved_pds = field >> 4;
1104 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1105 dev_lim->max_pds = 1 << (field & 0x3f);
1106 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1107 dev_lim->reserved_rdds = field >> 4;
1108 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1109 dev_lim->max_rdds = 1 << (field & 0x3f);
1111 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1112 dev_lim->eec_entry_sz = size;
1113 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1114 dev_lim->qpc_entry_sz = size;
1115 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1116 dev_lim->eeec_entry_sz = size;
1117 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1118 dev_lim->eqpc_entry_sz = size;
1119 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1120 dev_lim->eqc_entry_sz = size;
1121 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1122 dev_lim->cqc_entry_sz = size;
1123 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1124 dev_lim->srq_entry_sz = size;
1125 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1126 dev_lim->uar_scratch_entry_sz = size;
1128 if (mthca_is_memfree(dev)) {
1129 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1130 dev_lim->max_srq_sz = 1 << field;
1131 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1132 dev_lim->max_qp_sz = 1 << field;
1133 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1134 dev_lim->hca.arbel.resize_srq = field & 1;
1135 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1136 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1137 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1138 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1139 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1140 dev_lim->mpt_entry_sz = size;
1141 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1142 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1143 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1144 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1145 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1146 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1147 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1148 dev_lim->hca.arbel.lam_required = field & 1;
1149 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1150 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1152 if (dev_lim->hca.arbel.bmme_flags & 1)
1153 mthca_dbg(dev, "Base MM extensions: yes "
1154 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1155 dev_lim->hca.arbel.bmme_flags,
1156 dev_lim->hca.arbel.max_pbl_sz,
1157 dev_lim->hca.arbel.reserved_lkey);
1159 mthca_dbg(dev, "Base MM extensions: no\n");
1161 mthca_dbg(dev, "Max ICM size %lld MB\n",
1162 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1164 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1165 dev_lim->max_srq_sz = (1 << field) - 1;
1166 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1167 dev_lim->max_qp_sz = (1 << field) - 1;
1168 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1169 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1170 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1173 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1174 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1175 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1176 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1177 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1178 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1179 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1180 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1181 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1182 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1183 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1184 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1185 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1186 dev_lim->max_pds, dev_lim->reserved_mgms);
1187 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1188 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1190 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1193 mthca_free_mailbox(dev, mailbox);
1197 static void get_board_id(void *vsd, char *board_id)
1201 #define VSD_OFFSET_SIG1 0x00
1202 #define VSD_OFFSET_SIG2 0xde
1203 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1204 #define VSD_OFFSET_TS_BOARD_ID 0x20
1206 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1208 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1210 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1211 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1212 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1215 * The board ID is a string but the firmware byte
1216 * swaps each 4-byte word before passing it back to
1217 * us. Therefore we need to swab it before printing.
1219 for (i = 0; i < 4; ++i)
1220 ((u32 *) board_id)[i] =
1221 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1225 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1226 struct mthca_adapter *adapter, u8 *status)
1228 struct mthca_mailbox *mailbox;
1232 #define QUERY_ADAPTER_OUT_SIZE 0x100
1233 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1234 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1235 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1236 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1237 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1239 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1240 if (IS_ERR(mailbox))
1241 return PTR_ERR(mailbox);
1242 outbox = mailbox->buf;
1244 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1245 CMD_TIME_CLASS_A, status);
1250 if (!mthca_is_memfree(dev)) {
1251 MTHCA_GET(adapter->vendor_id, outbox,
1252 QUERY_ADAPTER_VENDOR_ID_OFFSET);
1253 MTHCA_GET(adapter->device_id, outbox,
1254 QUERY_ADAPTER_DEVICE_ID_OFFSET);
1255 MTHCA_GET(adapter->revision_id, outbox,
1256 QUERY_ADAPTER_REVISION_ID_OFFSET);
1258 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1260 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1264 mthca_free_mailbox(dev, mailbox);
1268 int mthca_INIT_HCA(struct mthca_dev *dev,
1269 struct mthca_init_hca_param *param,
1272 struct mthca_mailbox *mailbox;
1276 #define INIT_HCA_IN_SIZE 0x200
1277 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1278 #define INIT_HCA_FLAGS2_OFFSET 0x014
1279 #define INIT_HCA_QPC_OFFSET 0x020
1280 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1281 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1282 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1283 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1284 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1285 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1286 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1287 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1288 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1289 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1290 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1291 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1292 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1293 #define INIT_HCA_UDAV_OFFSET 0x0b0
1294 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1295 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1296 #define INIT_HCA_MCAST_OFFSET 0x0c0
1297 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1298 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1299 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1300 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1301 #define INIT_HCA_TPT_OFFSET 0x0f0
1302 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1303 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1304 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1305 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1306 #define INIT_HCA_UAR_OFFSET 0x120
1307 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1308 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1309 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1310 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1311 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1312 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1314 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1315 if (IS_ERR(mailbox))
1316 return PTR_ERR(mailbox);
1317 inbox = mailbox->buf;
1319 memset(inbox, 0, INIT_HCA_IN_SIZE);
1321 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1322 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1324 #if defined(__LITTLE_ENDIAN)
1325 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1326 #elif defined(__BIG_ENDIAN)
1327 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1329 #error Host endianness not defined
1331 /* Check port for UD address vector: */
1332 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1334 /* Enable IPoIB checksumming if we can: */
1335 if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1336 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1338 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1340 /* QPC/EEC/CQC/EQC/RDB attributes */
1342 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1343 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1344 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1345 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1346 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1347 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1348 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1349 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1350 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1351 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1352 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1353 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1354 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1356 /* UD AV attributes */
1358 /* multicast attributes */
1360 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1361 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1362 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1363 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1365 /* TPT attributes */
1367 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
1368 if (!mthca_is_memfree(dev))
1369 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1370 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1371 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1373 /* UAR attributes */
1375 u8 uar_page_sz = PAGE_SHIFT - 12;
1376 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1379 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1381 if (mthca_is_memfree(dev)) {
1382 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1383 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1384 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1387 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, CMD_TIME_CLASS_D, status);
1389 mthca_free_mailbox(dev, mailbox);
1393 int mthca_INIT_IB(struct mthca_dev *dev,
1394 struct mthca_init_ib_param *param,
1395 int port, u8 *status)
1397 struct mthca_mailbox *mailbox;
1402 #define INIT_IB_IN_SIZE 56
1403 #define INIT_IB_FLAGS_OFFSET 0x00
1404 #define INIT_IB_FLAG_SIG (1 << 18)
1405 #define INIT_IB_FLAG_NG (1 << 17)
1406 #define INIT_IB_FLAG_G0 (1 << 16)
1407 #define INIT_IB_VL_SHIFT 4
1408 #define INIT_IB_PORT_WIDTH_SHIFT 8
1409 #define INIT_IB_MTU_SHIFT 12
1410 #define INIT_IB_MAX_GID_OFFSET 0x06
1411 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1412 #define INIT_IB_GUID0_OFFSET 0x10
1413 #define INIT_IB_NODE_GUID_OFFSET 0x18
1414 #define INIT_IB_SI_GUID_OFFSET 0x20
1416 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1417 if (IS_ERR(mailbox))
1418 return PTR_ERR(mailbox);
1419 inbox = mailbox->buf;
1421 memset(inbox, 0, INIT_IB_IN_SIZE);
1424 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1425 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1426 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1427 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1428 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1429 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1430 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1432 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1433 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1434 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1435 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1436 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1438 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1439 CMD_TIME_CLASS_A, status);
1441 mthca_free_mailbox(dev, mailbox);
1445 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1447 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A, status);
1450 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1452 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C, status);
1455 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1456 int port, u8 *status)
1458 struct mthca_mailbox *mailbox;
1463 #define SET_IB_IN_SIZE 0x40
1464 #define SET_IB_FLAGS_OFFSET 0x00
1465 #define SET_IB_FLAG_SIG (1 << 18)
1466 #define SET_IB_FLAG_RQK (1 << 0)
1467 #define SET_IB_CAP_MASK_OFFSET 0x04
1468 #define SET_IB_SI_GUID_OFFSET 0x08
1470 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1471 if (IS_ERR(mailbox))
1472 return PTR_ERR(mailbox);
1473 inbox = mailbox->buf;
1475 memset(inbox, 0, SET_IB_IN_SIZE);
1477 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1478 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1479 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1481 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1482 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1484 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1485 CMD_TIME_CLASS_B, status);
1487 mthca_free_mailbox(dev, mailbox);
1491 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1493 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1496 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1498 struct mthca_mailbox *mailbox;
1502 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1503 if (IS_ERR(mailbox))
1504 return PTR_ERR(mailbox);
1505 inbox = mailbox->buf;
1507 inbox[0] = cpu_to_be64(virt);
1508 inbox[1] = cpu_to_be64(dma_addr);
1510 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1511 CMD_TIME_CLASS_B, status);
1513 mthca_free_mailbox(dev, mailbox);
1516 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1517 (unsigned long long) dma_addr, (unsigned long long) virt);
1522 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1524 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1525 page_count, (unsigned long long) virt);
1527 return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1530 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1532 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1535 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1537 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1540 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1543 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1544 CMD_TIME_CLASS_A, status);
1550 * Round up number of system pages needed in case
1551 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1553 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1554 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1559 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1560 int mpt_index, u8 *status)
1562 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1563 CMD_TIME_CLASS_B, status);
1566 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1567 int mpt_index, u8 *status)
1569 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1570 !mailbox, CMD_HW2SW_MPT,
1571 CMD_TIME_CLASS_B, status);
1574 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1575 int num_mtt, u8 *status)
1577 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1578 CMD_TIME_CLASS_B, status);
1581 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1583 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1586 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1587 int eq_num, u8 *status)
1589 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1590 unmap ? "Clearing" : "Setting",
1591 (unsigned long long) event_mask, eq_num);
1592 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1593 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1596 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1597 int eq_num, u8 *status)
1599 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1600 CMD_TIME_CLASS_A, status);
1603 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1604 int eq_num, u8 *status)
1606 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1608 CMD_TIME_CLASS_A, status);
1611 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1612 int cq_num, u8 *status)
1614 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1615 CMD_TIME_CLASS_A, status);
1618 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1619 int cq_num, u8 *status)
1621 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1623 CMD_TIME_CLASS_A, status);
1626 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
1629 struct mthca_mailbox *mailbox;
1633 #define RESIZE_CQ_IN_SIZE 0x40
1634 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1635 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1637 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1638 if (IS_ERR(mailbox))
1639 return PTR_ERR(mailbox);
1640 inbox = mailbox->buf;
1642 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1644 * Leave start address fields zeroed out -- mthca assumes that
1645 * MRs for CQs always start at virtual address 0.
1647 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1648 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1650 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1651 CMD_TIME_CLASS_B, status);
1653 mthca_free_mailbox(dev, mailbox);
1657 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1658 int srq_num, u8 *status)
1660 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1661 CMD_TIME_CLASS_A, status);
1664 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1665 int srq_num, u8 *status)
1667 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1669 CMD_TIME_CLASS_A, status);
1672 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1673 struct mthca_mailbox *mailbox, u8 *status)
1675 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1676 CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status);
1679 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1681 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1682 CMD_TIME_CLASS_B, status);
1685 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1686 enum ib_qp_state next, u32 num, int is_ee,
1687 struct mthca_mailbox *mailbox, u32 optmask,
1690 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1692 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1693 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1694 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1697 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1698 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1699 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1700 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1703 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1704 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1705 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1708 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1709 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1710 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1711 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1714 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1715 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1716 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1717 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1720 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1721 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1722 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1725 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1726 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1734 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1735 op_mod = 3; /* don't write outbox, any->reset */
1739 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1740 if (!IS_ERR(mailbox)) {
1742 op_mod = 2; /* write outbox, any->reset */
1747 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1748 (!!is_ee << 24) | num, op_mod,
1749 op[cur][next], CMD_TIME_CLASS_C, status);
1753 mthca_dbg(dev, "Dumping QP context:\n");
1754 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1755 for (i = 0; i < 0x100 / 4; ++i) {
1757 printk("[%02x] ", i * 4);
1759 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1760 if ((i + 1) % 8 == 0)
1766 mthca_free_mailbox(dev, mailbox);
1770 mthca_dbg(dev, "Dumping QP context:\n");
1771 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1772 for (i = 0; i < 0x100 / 4; ++i) {
1774 printk(" [%02x] ", i * 4);
1776 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1777 if ((i + 1) % 8 == 0)
1782 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1783 op_mod, op[cur][next], CMD_TIME_CLASS_C, status);
1789 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1790 struct mthca_mailbox *mailbox, u8 *status)
1792 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1793 CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1796 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1808 case IB_QPT_RAW_IPV6:
1811 case IB_QPT_RAW_ETY:
1818 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1819 CMD_TIME_CLASS_B, status);
1822 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1823 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1824 void *in_mad, void *response_mad, u8 *status)
1826 struct mthca_mailbox *inmailbox, *outmailbox;
1829 u32 in_modifier = port;
1832 #define MAD_IFC_BOX_SIZE 0x400
1833 #define MAD_IFC_MY_QPN_OFFSET 0x100
1834 #define MAD_IFC_RQPN_OFFSET 0x108
1835 #define MAD_IFC_SL_OFFSET 0x10c
1836 #define MAD_IFC_G_PATH_OFFSET 0x10d
1837 #define MAD_IFC_RLID_OFFSET 0x10e
1838 #define MAD_IFC_PKEY_OFFSET 0x112
1839 #define MAD_IFC_GRH_OFFSET 0x140
1841 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1842 if (IS_ERR(inmailbox))
1843 return PTR_ERR(inmailbox);
1844 inbox = inmailbox->buf;
1846 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1847 if (IS_ERR(outmailbox)) {
1848 mthca_free_mailbox(dev, inmailbox);
1849 return PTR_ERR(outmailbox);
1852 memcpy(inbox, in_mad, 256);
1855 * Key check traps can't be generated unless we have in_wc to
1856 * tell us where to send the trap.
1858 if (ignore_mkey || !in_wc)
1860 if (ignore_bkey || !in_wc)
1866 memset(inbox + 256, 0, 256);
1868 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
1869 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1871 val = in_wc->sl << 4;
1872 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1874 val = in_wc->dlid_path_bits |
1875 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1876 MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET);
1878 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
1879 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1882 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1886 in_modifier |= in_wc->slid << 16;
1889 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1890 in_modifier, op_modifier,
1891 CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1893 if (!err && !*status)
1894 memcpy(response_mad, outmailbox->buf, 256);
1896 mthca_free_mailbox(dev, inmailbox);
1897 mthca_free_mailbox(dev, outmailbox);
1901 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1902 struct mthca_mailbox *mailbox, u8 *status)
1904 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1905 CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1908 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1909 struct mthca_mailbox *mailbox, u8 *status)
1911 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1912 CMD_TIME_CLASS_A, status);
1915 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1916 u16 *hash, u8 *status)
1921 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1922 CMD_TIME_CLASS_A, status);
1928 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1930 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);