2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
100 * This driver is in the /sys/pci directory because it only supports
104 #ifdef HAVE_KERNEL_OPTION_HEADERS
105 #include "opt_device_polling.h"
108 #include <sys/param.h>
109 #include <sys/systm.h>
110 #include <sys/sockio.h>
111 #include <sys/endian.h>
112 #include <sys/mbuf.h>
113 #include <sys/kernel.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
119 #include <net/if_arp.h>
120 #include <net/ethernet.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/if_types.h>
127 #include <machine/bus.h>
128 #include <machine/resource.h>
130 #include <sys/rman.h>
132 #include <dev/mii/mii.h>
133 #include <dev/mii/miivar.h>
135 #include <dev/pci/pcireg.h>
136 #include <dev/pci/pcivar.h>
138 MODULE_DEPEND(xl, pci, 1, 1, 1);
139 MODULE_DEPEND(xl, ether, 1, 1, 1);
140 MODULE_DEPEND(xl, miibus, 1, 1, 1);
142 /* "device miibus" required. See GENERIC if you get errors here. */
143 #include "miibus_if.h"
145 #include <pci/if_xlreg.h>
148 * TX Checksumming is disabled by default for two reasons:
149 * - TX Checksumming will occasionally produce corrupt packets
150 * - TX Checksumming seems to reduce performance
152 * Only 905B/C cards were reported to have this problem, it is possible
153 * that later chips _may_ be immune.
155 #define XL905B_TXCSUM_BROKEN 1
157 #ifdef XL905B_TXCSUM_BROKEN
158 #define XL905B_CSUM_FEATURES 0
160 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
164 * Various supported device vendors/types and their names.
166 static const struct xl_type xl_devs[] = {
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
168 "3Com 3c900-TPO Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
170 "3Com 3c900-COMBO Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
172 "3Com 3c905-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
174 "3Com 3c905-T4 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
176 "3Com 3c900B-TPO Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
178 "3Com 3c900B-COMBO Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
180 "3Com 3c900B-TPC Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
182 "3Com 3c900B-FL Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
184 "3Com 3c905B-TX Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
186 "3Com 3c905B-T4 Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
188 "3Com 3c905B-FX/SC Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
190 "3Com 3c905B-COMBO Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
192 "3Com 3c905C-TX Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
198 "3Com 3c980 Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
200 "3Com 3c980C Fast Etherlink XL" },
201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
202 "3Com 3cSOHO100-TX OfficeConnect" },
203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
204 "3Com 3c450-TX HomeConnect" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
206 "3Com 3c555 Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
208 "3Com 3c556 Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
210 "3Com 3c556B Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
212 "3Com 3c575TX Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
214 "3Com 3c575B Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
216 "3Com 3c575C Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
218 "3Com 3c656 Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
220 "3Com 3c656B Fast Etherlink XL" },
221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
222 "3Com 3c656C Fast Etherlink XL" },
226 static int xl_probe(device_t);
227 static int xl_attach(device_t);
228 static int xl_detach(device_t);
230 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
231 static void xl_stats_update(void *);
232 static void xl_stats_update_locked(struct xl_softc *);
233 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
234 static void xl_rxeof(struct xl_softc *);
235 static void xl_rxeof_task(void *, int);
236 static int xl_rx_resync(struct xl_softc *);
237 static void xl_txeof(struct xl_softc *);
238 static void xl_txeof_90xB(struct xl_softc *);
239 static void xl_txeoc(struct xl_softc *);
240 static void xl_intr(void *);
241 static void xl_start(struct ifnet *);
242 static void xl_start_locked(struct ifnet *);
243 static void xl_start_90xB_locked(struct ifnet *);
244 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
245 static void xl_init(void *);
246 static void xl_init_locked(struct xl_softc *);
247 static void xl_stop(struct xl_softc *);
248 static int xl_watchdog(struct xl_softc *);
249 static int xl_shutdown(device_t);
250 static int xl_suspend(device_t);
251 static int xl_resume(device_t);
253 #ifdef DEVICE_POLLING
254 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
255 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_ifmedia_upd(struct ifnet *);
259 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
261 static int xl_eeprom_wait(struct xl_softc *);
262 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
263 static void xl_mii_sync(struct xl_softc *);
264 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
265 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
266 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
268 static void xl_setcfg(struct xl_softc *);
269 static void xl_setmode(struct xl_softc *, int);
270 static void xl_setmulti(struct xl_softc *);
271 static void xl_setmulti_hash(struct xl_softc *);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
282 static void xl_testpacket(struct xl_softc *);
285 static int xl_miibus_readreg(device_t, int, int);
286 static int xl_miibus_writereg(device_t, int, int, int);
287 static void xl_miibus_statchg(device_t);
288 static void xl_miibus_mediainit(device_t);
290 static device_method_t xl_methods[] = {
291 /* Device interface */
292 DEVMETHOD(device_probe, xl_probe),
293 DEVMETHOD(device_attach, xl_attach),
294 DEVMETHOD(device_detach, xl_detach),
295 DEVMETHOD(device_shutdown, xl_shutdown),
296 DEVMETHOD(device_suspend, xl_suspend),
297 DEVMETHOD(device_resume, xl_resume),
300 DEVMETHOD(bus_print_child, bus_generic_print_child),
301 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
304 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
305 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
306 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
307 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
312 static driver_t xl_driver = {
315 sizeof(struct xl_softc)
318 static devclass_t xl_devclass;
320 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0);
321 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
322 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
325 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
330 *paddr = segs->ds_addr;
334 * Murphy's law says that it's possible the chip can wedge and
335 * the 'command in progress' bit may never clear. Hence, we wait
336 * only a finite amount of time to avoid getting caught in an
337 * infinite loop. Normally this delay routine would be a macro,
338 * but it isn't called during normal operation so we can afford
339 * to make it a function.
342 xl_wait(struct xl_softc *sc)
346 for (i = 0; i < XL_TIMEOUT; i++) {
347 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
352 device_printf(sc->xl_dev, "command never completed!\n");
356 * MII access routines are provided for adapters with external
357 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
358 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
359 * Note: if you don't perform the MDIO operations just right,
360 * it's possible to end up with code that works correctly with
361 * some chips/CPUs/processor speeds/bus speeds/etc but not
365 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
366 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
369 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
370 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
373 * Sync the PHYs by setting data bit and strobing the clock 32 times.
376 xl_mii_sync(struct xl_softc *sc)
381 MII_SET(XL_MII_DIR|XL_MII_DATA);
383 for (i = 0; i < 32; i++) {
385 MII_SET(XL_MII_DATA);
386 MII_SET(XL_MII_DATA);
388 MII_SET(XL_MII_DATA);
389 MII_SET(XL_MII_DATA);
394 * Clock a series of bits through the MII.
397 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
404 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
406 MII_SET(XL_MII_DATA);
408 MII_CLR(XL_MII_DATA);
416 * Read an PHY register through the MII.
419 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
423 /* Set up frame for RX. */
424 frame->mii_stdelim = XL_MII_STARTDELIM;
425 frame->mii_opcode = XL_MII_READOP;
426 frame->mii_turnaround = 0;
429 /* Select register window 4. */
432 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
433 /* Turn on data xmit. */
438 /* Send command/address info. */
439 xl_mii_send(sc, frame->mii_stdelim, 2);
440 xl_mii_send(sc, frame->mii_opcode, 2);
441 xl_mii_send(sc, frame->mii_phyaddr, 5);
442 xl_mii_send(sc, frame->mii_regaddr, 5);
445 MII_CLR((XL_MII_CLK|XL_MII_DATA));
453 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
457 * Now try reading data bits. If the ack failed, we still
458 * need to clock through 16 cycles to keep the PHY(s) in sync.
461 for (i = 0; i < 16; i++) {
468 for (i = 0x8000; i; i >>= 1) {
471 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
472 frame->mii_data |= i;
481 return (ack ? 1 : 0);
485 * Write to a PHY register through the MII.
488 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
491 /* Set up frame for TX. */
492 frame->mii_stdelim = XL_MII_STARTDELIM;
493 frame->mii_opcode = XL_MII_WRITEOP;
494 frame->mii_turnaround = XL_MII_TURNAROUND;
496 /* Select the window 4. */
499 /* Turn on data output. */
504 xl_mii_send(sc, frame->mii_stdelim, 2);
505 xl_mii_send(sc, frame->mii_opcode, 2);
506 xl_mii_send(sc, frame->mii_phyaddr, 5);
507 xl_mii_send(sc, frame->mii_regaddr, 5);
508 xl_mii_send(sc, frame->mii_turnaround, 2);
509 xl_mii_send(sc, frame->mii_data, 16);
522 xl_miibus_readreg(device_t dev, int phy, int reg)
525 struct xl_mii_frame frame;
527 sc = device_get_softc(dev);
530 * Pretend that PHYs are only available at MII address 24.
531 * This is to guard against problems with certain 3Com ASIC
532 * revisions that incorrectly map the internal transceiver
533 * control registers at all MII addresses. This can cause
534 * the miibus code to attach the same PHY several times over.
536 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
539 bzero((char *)&frame, sizeof(frame));
540 frame.mii_phyaddr = phy;
541 frame.mii_regaddr = reg;
543 xl_mii_readreg(sc, &frame);
545 return (frame.mii_data);
549 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
552 struct xl_mii_frame frame;
554 sc = device_get_softc(dev);
556 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
559 bzero((char *)&frame, sizeof(frame));
560 frame.mii_phyaddr = phy;
561 frame.mii_regaddr = reg;
562 frame.mii_data = data;
564 xl_mii_writereg(sc, &frame);
570 xl_miibus_statchg(device_t dev)
573 struct mii_data *mii;
575 sc = device_get_softc(dev);
576 mii = device_get_softc(sc->xl_miibus);
580 /* Set ASIC's duplex mode to match the PHY. */
582 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
583 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
585 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
586 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
590 * Special support for the 3c905B-COMBO. This card has 10/100 support
591 * plus BNC and AUI ports. This means we will have both an miibus attached
592 * plus some non-MII media settings. In order to allow this, we have to
593 * add the extra media to the miibus's ifmedia struct, but we can't do
594 * that during xl_attach() because the miibus hasn't been attached yet.
595 * So instead, we wait until the miibus probe/attach is done, at which
596 * point we will get a callback telling is that it's safe to add our
600 xl_miibus_mediainit(device_t dev)
603 struct mii_data *mii;
606 sc = device_get_softc(dev);
607 mii = device_get_softc(sc->xl_miibus);
608 ifm = &mii->mii_media;
610 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
612 * Check for a 10baseFL board in disguise.
614 if (sc->xl_type == XL_TYPE_905B &&
615 sc->xl_media == XL_MEDIAOPT_10FL) {
617 device_printf(sc->xl_dev, "found 10baseFL\n");
618 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
619 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
621 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
623 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
626 device_printf(sc->xl_dev, "found AUI\n");
627 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
631 if (sc->xl_media & XL_MEDIAOPT_BNC) {
633 device_printf(sc->xl_dev, "found BNC\n");
634 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
639 * The EEPROM is slow: give it time to come ready after issuing
643 xl_eeprom_wait(struct xl_softc *sc)
647 for (i = 0; i < 100; i++) {
648 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
655 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
663 * Read a sequence of words from the EEPROM. Note that ethernet address
664 * data is stored in the EEPROM in network byte order.
667 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
670 u_int16_t word = 0, *ptr;
672 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
673 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
675 * XXX: WARNING! DANGER!
676 * It's easy to accidentally overwrite the rom content!
677 * Note: the 3c575 uses 8bit EEPROM offsets.
681 if (xl_eeprom_wait(sc))
684 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
687 for (i = 0; i < cnt; i++) {
688 if (sc->xl_flags & XL_FLAG_8BITROM)
689 CSR_WRITE_2(sc, XL_W0_EE_CMD,
690 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
692 CSR_WRITE_2(sc, XL_W0_EE_CMD,
693 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
694 err = xl_eeprom_wait(sc);
697 word = CSR_READ_2(sc, XL_W0_EE_DATA);
698 ptr = (u_int16_t *)(dest + (i * 2));
705 return (err ? 1 : 0);
709 * NICs older than the 3c905B have only one multicast option, which
710 * is to enable reception of all multicast frames.
713 xl_setmulti(struct xl_softc *sc)
715 struct ifnet *ifp = sc->xl_ifp;
716 struct ifmultiaddr *ifma;
723 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
725 if (ifp->if_flags & IFF_ALLMULTI) {
726 rxfilt |= XL_RXFILTER_ALLMULTI;
727 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
732 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
737 rxfilt |= XL_RXFILTER_ALLMULTI;
739 rxfilt &= ~XL_RXFILTER_ALLMULTI;
741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
745 * 3c905B adapters have a hash filter that we can program.
748 xl_setmulti_hash(struct xl_softc *sc)
750 struct ifnet *ifp = sc->xl_ifp;
752 struct ifmultiaddr *ifma;
759 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
761 if (ifp->if_flags & IFF_ALLMULTI) {
762 rxfilt |= XL_RXFILTER_ALLMULTI;
763 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
766 rxfilt &= ~XL_RXFILTER_ALLMULTI;
768 /* first, zot all the existing hash bits */
769 for (i = 0; i < XL_HASHFILT_SIZE; i++)
770 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
772 /* now program new ones */
774 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
775 if (ifma->ifma_addr->sa_family != AF_LINK)
778 * Note: the 3c905B currently only supports a 64-bit hash
779 * table, which means we really only need 6 bits, but the
780 * manual indicates that future chip revisions will have a
781 * 256-bit hash table, hence the routine is set up to
782 * calculate 8 bits of position info in case we need it some
784 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have
785 * a 256 bit hash table. This means we have to use all 8 bits
786 * regardless. On older cards, the upper 2 bits will be
789 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
790 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
791 CSR_WRITE_2(sc, XL_COMMAND,
792 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
798 rxfilt |= XL_RXFILTER_MULTIHASH;
800 rxfilt &= ~XL_RXFILTER_MULTIHASH;
802 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
807 xl_testpacket(struct xl_softc *sc)
810 struct ifnet *ifp = sc->xl_ifp;
812 MGETHDR(m, M_DONTWAIT, MT_DATA);
817 bcopy(IF_LLADDR(sc->xl_ifp),
818 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
819 bcopy(IF_LLADDR(sc->xl_ifp),
820 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
821 mtod(m, struct ether_header *)->ether_type = htons(3);
822 mtod(m, unsigned char *)[14] = 0;
823 mtod(m, unsigned char *)[15] = 0;
824 mtod(m, unsigned char *)[16] = 0xE3;
825 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
826 IFQ_ENQUEUE(&ifp->if_snd, m);
832 xl_setcfg(struct xl_softc *sc)
836 /*XL_LOCK_ASSERT(sc);*/
839 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
840 icfg &= ~XL_ICFG_CONNECTOR_MASK;
841 if (sc->xl_media & XL_MEDIAOPT_MII ||
842 sc->xl_media & XL_MEDIAOPT_BT4)
843 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
844 if (sc->xl_media & XL_MEDIAOPT_BTX)
845 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
847 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
852 xl_setmode(struct xl_softc *sc, int media)
856 char *pmsg = "", *dmsg = "";
861 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
863 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
865 if (sc->xl_media & XL_MEDIAOPT_BT) {
866 if (IFM_SUBTYPE(media) == IFM_10_T) {
867 pmsg = "10baseT transceiver";
868 sc->xl_xcvr = XL_XCVR_10BT;
869 icfg &= ~XL_ICFG_CONNECTOR_MASK;
870 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
871 mediastat |= XL_MEDIASTAT_LINKBEAT |
872 XL_MEDIASTAT_JABGUARD;
873 mediastat &= ~XL_MEDIASTAT_SQEENB;
877 if (sc->xl_media & XL_MEDIAOPT_BFX) {
878 if (IFM_SUBTYPE(media) == IFM_100_FX) {
879 pmsg = "100baseFX port";
880 sc->xl_xcvr = XL_XCVR_100BFX;
881 icfg &= ~XL_ICFG_CONNECTOR_MASK;
882 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
883 mediastat |= XL_MEDIASTAT_LINKBEAT;
884 mediastat &= ~XL_MEDIASTAT_SQEENB;
888 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
889 if (IFM_SUBTYPE(media) == IFM_10_5) {
891 sc->xl_xcvr = XL_XCVR_AUI;
892 icfg &= ~XL_ICFG_CONNECTOR_MASK;
893 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
894 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
895 XL_MEDIASTAT_JABGUARD);
896 mediastat |= ~XL_MEDIASTAT_SQEENB;
898 if (IFM_SUBTYPE(media) == IFM_10_FL) {
899 pmsg = "10baseFL transceiver";
900 sc->xl_xcvr = XL_XCVR_AUI;
901 icfg &= ~XL_ICFG_CONNECTOR_MASK;
902 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
903 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
904 XL_MEDIASTAT_JABGUARD);
905 mediastat |= ~XL_MEDIASTAT_SQEENB;
909 if (sc->xl_media & XL_MEDIAOPT_BNC) {
910 if (IFM_SUBTYPE(media) == IFM_10_2) {
912 sc->xl_xcvr = XL_XCVR_COAX;
913 icfg &= ~XL_ICFG_CONNECTOR_MASK;
914 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
915 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
916 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
920 if ((media & IFM_GMASK) == IFM_FDX ||
921 IFM_SUBTYPE(media) == IFM_100_FX) {
924 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
928 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
929 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
932 if (IFM_SUBTYPE(media) == IFM_10_2)
933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
937 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
939 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
944 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
948 xl_reset(struct xl_softc *sc)
955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
956 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
957 XL_RESETOPT_DISADVFD:0));
960 * If we're using memory mapped register mode, pause briefly
961 * after issuing the reset command before trying to access any
962 * other registers. With my 3c575C cardbus card, failing to do
963 * this results in the system locking up while trying to poll
964 * the command busy bit in the status register.
966 if (sc->xl_flags & XL_FLAG_USE_MMIO)
969 for (i = 0; i < XL_TIMEOUT; i++) {
971 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
976 device_printf(sc->xl_dev, "reset didn't complete\n");
978 /* Reset TX and RX. */
979 /* Note: the RX reset takes an absurd amount of time
980 * on newer versions of the Tornado chips such as those
981 * on the 3c905CX and newer 3c908C cards. We wait an
982 * extra amount of time so that xl_wait() doesn't complain
983 * and annoy the users.
985 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
991 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
992 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
994 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
995 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
996 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
997 XL_RESETOPT_INVERT_LED : 0) |
998 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
999 XL_RESETOPT_INVERT_MII : 0));
1002 /* Wait a little while for the chip to get its brains in order. */
1007 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1008 * IDs against our list and return a device name if we find a match.
1011 xl_probe(device_t dev)
1013 const struct xl_type *t;
1017 while (t->xl_name != NULL) {
1018 if ((pci_get_vendor(dev) == t->xl_vid) &&
1019 (pci_get_device(dev) == t->xl_did)) {
1020 device_set_desc(dev, t->xl_name);
1021 return (BUS_PROBE_DEFAULT);
1030 * This routine is a kludge to work around possible hardware faults
1031 * or manufacturing defects that can cause the media options register
1032 * (or reset options register, as it's called for the first generation
1033 * 3c90x adapters) to return an incorrect result. I have encountered
1034 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1035 * which doesn't have any of the 'mediaopt' bits set. This screws up
1036 * the attach routine pretty badly because it doesn't know what media
1037 * to look for. If we find ourselves in this predicament, this routine
1038 * will try to guess the media options values and warn the user of a
1039 * possible manufacturing defect with his adapter/system/whatever.
1042 xl_mediacheck(struct xl_softc *sc)
1046 * If some of the media options bits are set, assume they are
1047 * correct. If not, try to figure it out down below.
1048 * XXX I should check for 10baseFL, but I don't have an adapter
1051 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1053 * Check the XCVR value. If it's not in the normal range
1054 * of values, we need to fake it up here.
1056 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1059 device_printf(sc->xl_dev,
1060 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1061 device_printf(sc->xl_dev,
1062 "choosing new default based on card type\n");
1065 if (sc->xl_type == XL_TYPE_905B &&
1066 sc->xl_media & XL_MEDIAOPT_10FL)
1068 device_printf(sc->xl_dev,
1069 "WARNING: no media options bits set in the media options register!!\n");
1070 device_printf(sc->xl_dev,
1071 "this could be a manufacturing defect in your adapter or system\n");
1072 device_printf(sc->xl_dev,
1073 "attempting to guess media type; you should probably consult your vendor\n");
1076 xl_choose_xcvr(sc, 1);
1080 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1085 * Read the device ID from the EEPROM.
1086 * This is what's loaded into the PCI device ID register, so it has
1087 * to be correct otherwise we wouldn't have gotten this far.
1089 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1092 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1093 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1094 sc->xl_media = XL_MEDIAOPT_BT;
1095 sc->xl_xcvr = XL_XCVR_10BT;
1097 device_printf(sc->xl_dev,
1098 "guessing 10BaseT transceiver\n");
1100 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1101 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1102 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1103 sc->xl_xcvr = XL_XCVR_10BT;
1105 device_printf(sc->xl_dev,
1106 "guessing COMBO (AUI/BNC/TP)\n");
1108 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1109 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1110 sc->xl_xcvr = XL_XCVR_10BT;
1112 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1114 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1115 sc->xl_media = XL_MEDIAOPT_10FL;
1116 sc->xl_xcvr = XL_XCVR_AUI;
1118 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1120 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1121 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1122 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1123 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1124 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1125 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1126 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1127 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1128 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1129 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1130 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1131 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1132 sc->xl_media = XL_MEDIAOPT_MII;
1133 sc->xl_xcvr = XL_XCVR_MII;
1135 device_printf(sc->xl_dev, "guessing MII\n");
1137 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1138 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1139 sc->xl_media = XL_MEDIAOPT_BT4;
1140 sc->xl_xcvr = XL_XCVR_MII;
1142 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1144 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1145 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1146 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1147 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1148 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1149 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1150 sc->xl_media = XL_MEDIAOPT_BTX;
1151 sc->xl_xcvr = XL_XCVR_AUTO;
1153 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1155 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1156 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1157 sc->xl_xcvr = XL_XCVR_AUTO;
1159 device_printf(sc->xl_dev,
1160 "guessing 10/100 plus BNC/AUI\n");
1163 device_printf(sc->xl_dev,
1164 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1165 sc->xl_media = XL_MEDIAOPT_BT;
1171 * Attach the interface. Allocate softc structures, do ifmedia
1172 * setup and ethernet/BPF attach.
1175 xl_attach(device_t dev)
1177 u_char eaddr[ETHER_ADDR_LEN];
1179 struct xl_softc *sc;
1182 int unit, error = 0, rid, res;
1185 sc = device_get_softc(dev);
1188 unit = device_get_unit(dev);
1190 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1192 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1194 did = pci_get_device(dev);
1197 if (did == TC_DEVICEID_HURRICANE_555)
1198 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1199 if (did == TC_DEVICEID_HURRICANE_556 ||
1200 did == TC_DEVICEID_HURRICANE_556B)
1201 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1202 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1203 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1204 if (did == TC_DEVICEID_HURRICANE_555 ||
1205 did == TC_DEVICEID_HURRICANE_556)
1206 sc->xl_flags |= XL_FLAG_8BITROM;
1207 if (did == TC_DEVICEID_HURRICANE_556B)
1208 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1210 if (did == TC_DEVICEID_HURRICANE_575B ||
1211 did == TC_DEVICEID_HURRICANE_575C ||
1212 did == TC_DEVICEID_HURRICANE_656B ||
1213 did == TC_DEVICEID_TORNADO_656C)
1214 sc->xl_flags |= XL_FLAG_FUNCREG;
1215 if (did == TC_DEVICEID_HURRICANE_575A ||
1216 did == TC_DEVICEID_HURRICANE_575B ||
1217 did == TC_DEVICEID_HURRICANE_575C ||
1218 did == TC_DEVICEID_HURRICANE_656B ||
1219 did == TC_DEVICEID_TORNADO_656C)
1220 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1222 if (did == TC_DEVICEID_HURRICANE_656)
1223 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1224 if (did == TC_DEVICEID_HURRICANE_575B)
1225 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1226 if (did == TC_DEVICEID_HURRICANE_575C)
1227 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1228 if (did == TC_DEVICEID_TORNADO_656C)
1229 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1230 if (did == TC_DEVICEID_HURRICANE_656 ||
1231 did == TC_DEVICEID_HURRICANE_656B)
1232 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1233 XL_FLAG_INVERT_LED_PWR;
1234 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1235 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1236 sc->xl_flags |= XL_FLAG_PHYOK;
1239 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1240 case TC_DEVICEID_HURRICANE_575A:
1241 case TC_DEVICEID_HURRICANE_575B:
1242 case TC_DEVICEID_HURRICANE_575C:
1243 sc->xl_flags |= XL_FLAG_NO_MMIO;
1250 * Map control/status registers.
1252 pci_enable_busmaster(dev);
1254 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1256 res = SYS_RES_MEMORY;
1258 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1261 if (sc->xl_res != NULL) {
1262 sc->xl_flags |= XL_FLAG_USE_MMIO;
1264 device_printf(dev, "using memory mapped I/O\n");
1267 res = SYS_RES_IOPORT;
1268 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1269 if (sc->xl_res == NULL) {
1270 device_printf(dev, "couldn't map ports/memory\n");
1275 device_printf(dev, "using port I/O\n");
1278 sc->xl_btag = rman_get_bustag(sc->xl_res);
1279 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1281 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1282 rid = XL_PCI_FUNCMEM;
1283 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1286 if (sc->xl_fres == NULL) {
1287 device_printf(dev, "couldn't map funcreg memory\n");
1292 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1293 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1296 /* Allocate interrupt */
1298 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1299 RF_SHAREABLE | RF_ACTIVE);
1300 if (sc->xl_irq == NULL) {
1301 device_printf(dev, "couldn't map interrupt\n");
1306 /* Initialize interface name. */
1307 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1309 device_printf(dev, "can not if_alloc()\n");
1314 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1316 /* Reset the adapter. */
1322 * Get station address from the EEPROM.
1324 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1325 device_printf(dev, "failed to read station address\n");
1331 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0);
1332 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1335 * Now allocate a tag for the DMA descriptor lists and a chunk
1336 * of DMA-able memory based on the tag. Also obtain the DMA
1337 * addresses of the RX and TX ring, which we'll need later.
1338 * All of our lists are allocated as a contiguous block
1341 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1342 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1343 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1344 &sc->xl_ldata.xl_rx_tag);
1346 device_printf(dev, "failed to allocate rx dma tag\n");
1350 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1351 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1352 &sc->xl_ldata.xl_rx_dmamap);
1354 device_printf(dev, "no memory for rx list buffers!\n");
1355 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1356 sc->xl_ldata.xl_rx_tag = NULL;
1360 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1361 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1362 XL_RX_LIST_SZ, xl_dma_map_addr,
1363 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1365 device_printf(dev, "cannot get dma address of the rx ring!\n");
1366 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1367 sc->xl_ldata.xl_rx_dmamap);
1368 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1369 sc->xl_ldata.xl_rx_tag = NULL;
1373 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1374 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1375 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1376 &sc->xl_ldata.xl_tx_tag);
1378 device_printf(dev, "failed to allocate tx dma tag\n");
1382 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1383 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1384 &sc->xl_ldata.xl_tx_dmamap);
1386 device_printf(dev, "no memory for list buffers!\n");
1387 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1388 sc->xl_ldata.xl_tx_tag = NULL;
1392 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1393 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1394 XL_TX_LIST_SZ, xl_dma_map_addr,
1395 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1397 device_printf(dev, "cannot get dma address of the tx ring!\n");
1398 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1399 sc->xl_ldata.xl_tx_dmamap);
1400 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1401 sc->xl_ldata.xl_tx_tag = NULL;
1406 * Allocate a DMA tag for the mapping of mbufs.
1408 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1409 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1410 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1411 NULL, &sc->xl_mtag);
1413 device_printf(dev, "failed to allocate mbuf dma tag\n");
1417 /* We need a spare DMA map for the RX ring. */
1418 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1423 * Figure out the card type. 3c905B adapters have the
1424 * 'supportsNoTxLength' bit set in the capabilities
1425 * word in the EEPROM.
1426 * Note: my 3c575C cardbus card lies. It returns a value
1427 * of 0x1578 for its capabilities word, which is somewhat
1428 * nonsensical. Another way to distinguish a 3c90x chip
1429 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1430 * bit. This will only be set for 3c90x boomerage chips.
1432 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1433 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1434 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1435 sc->xl_type = XL_TYPE_905B;
1437 sc->xl_type = XL_TYPE_90X;
1439 /* Set the TX start threshold for best performance. */
1440 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1442 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1443 ifp->if_ioctl = xl_ioctl;
1444 ifp->if_capabilities = IFCAP_VLAN_MTU;
1445 if (sc->xl_type == XL_TYPE_905B) {
1446 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1447 #ifdef XL905B_TXCSUM_BROKEN
1448 ifp->if_capabilities |= IFCAP_RXCSUM;
1450 ifp->if_capabilities |= IFCAP_HWCSUM;
1453 ifp->if_capenable = ifp->if_capabilities;
1454 #ifdef DEVICE_POLLING
1455 ifp->if_capabilities |= IFCAP_POLLING;
1457 ifp->if_start = xl_start;
1458 ifp->if_init = xl_init;
1459 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1460 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1461 IFQ_SET_READY(&ifp->if_snd);
1464 * Now we have to see what sort of media we have.
1465 * This includes probing for an MII interace and a
1469 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1471 device_printf(dev, "media options word: %x\n", sc->xl_media);
1473 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1474 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1475 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1476 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1480 if (sc->xl_media & XL_MEDIAOPT_MII ||
1481 sc->xl_media & XL_MEDIAOPT_BTX ||
1482 sc->xl_media & XL_MEDIAOPT_BT4) {
1484 device_printf(dev, "found MII/AUTO\n");
1486 if (mii_phy_probe(dev, &sc->xl_miibus,
1487 xl_ifmedia_upd, xl_ifmedia_sts)) {
1488 device_printf(dev, "no PHY found!\n");
1496 * Sanity check. If the user has selected "auto" and this isn't
1497 * a 10/100 card of some kind, we need to force the transceiver
1498 * type to something sane.
1500 if (sc->xl_xcvr == XL_XCVR_AUTO)
1501 xl_choose_xcvr(sc, bootverbose);
1506 if (sc->xl_media & XL_MEDIAOPT_BT) {
1508 device_printf(dev, "found 10baseT\n");
1509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1510 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1511 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1512 ifmedia_add(&sc->ifmedia,
1513 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1516 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1518 * Check for a 10baseFL board in disguise.
1520 if (sc->xl_type == XL_TYPE_905B &&
1521 sc->xl_media == XL_MEDIAOPT_10FL) {
1523 device_printf(dev, "found 10baseFL\n");
1524 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1525 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1527 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1528 ifmedia_add(&sc->ifmedia,
1529 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1532 device_printf(dev, "found AUI\n");
1533 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1537 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1539 device_printf(dev, "found BNC\n");
1540 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1543 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1545 device_printf(dev, "found 100baseFX\n");
1546 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1549 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1550 xl_choose_media(sc, &media);
1552 if (sc->xl_miibus == NULL)
1553 ifmedia_set(&sc->ifmedia, media);
1556 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1558 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1562 * Call MI attach routine.
1564 ether_ifattach(ifp, eaddr);
1566 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1567 NULL, xl_intr, sc, &sc->xl_intrhand);
1569 device_printf(dev, "couldn't set up irq\n");
1570 ether_ifdetach(ifp);
1582 * Choose a default media.
1583 * XXX This is a leaf function only called by xl_attach() and
1584 * acquires/releases the non-recursible driver mutex to
1585 * satisfy lock assertions.
1588 xl_choose_media(struct xl_softc *sc, int *media)
1593 switch (sc->xl_xcvr) {
1595 *media = IFM_ETHER|IFM_10_T;
1596 xl_setmode(sc, *media);
1599 if (sc->xl_type == XL_TYPE_905B &&
1600 sc->xl_media == XL_MEDIAOPT_10FL) {
1601 *media = IFM_ETHER|IFM_10_FL;
1602 xl_setmode(sc, *media);
1604 *media = IFM_ETHER|IFM_10_5;
1605 xl_setmode(sc, *media);
1609 *media = IFM_ETHER|IFM_10_2;
1610 xl_setmode(sc, *media);
1613 case XL_XCVR_100BTX:
1615 /* Chosen by miibus */
1617 case XL_XCVR_100BFX:
1618 *media = IFM_ETHER|IFM_100_FX;
1621 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1624 * This will probably be wrong, but it prevents
1625 * the ifmedia code from panicking.
1627 *media = IFM_ETHER|IFM_10_T;
1635 * Shutdown hardware and free up resources. This can be called any
1636 * time after the mutex has been initialized. It is called in both
1637 * the error case in attach and the normal detach case so it needs
1638 * to be careful about only freeing resources that have actually been
1642 xl_detach(device_t dev)
1644 struct xl_softc *sc;
1648 sc = device_get_softc(dev);
1651 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1653 #ifdef DEVICE_POLLING
1654 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1655 ether_poll_deregister(ifp);
1658 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1660 res = SYS_RES_MEMORY;
1663 res = SYS_RES_IOPORT;
1666 /* These should only be active if attach succeeded */
1667 if (device_is_attached(dev)) {
1672 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1673 callout_drain(&sc->xl_stat_callout);
1674 ether_ifdetach(ifp);
1677 device_delete_child(dev, sc->xl_miibus);
1678 bus_generic_detach(dev);
1679 ifmedia_removeall(&sc->ifmedia);
1681 if (sc->xl_intrhand)
1682 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1685 if (sc->xl_fres != NULL)
1686 bus_release_resource(dev, SYS_RES_MEMORY,
1687 XL_PCI_FUNCMEM, sc->xl_fres);
1689 bus_release_resource(dev, res, rid, sc->xl_res);
1695 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1696 bus_dma_tag_destroy(sc->xl_mtag);
1698 if (sc->xl_ldata.xl_rx_tag) {
1699 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1700 sc->xl_ldata.xl_rx_dmamap);
1701 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1702 sc->xl_ldata.xl_rx_dmamap);
1703 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1705 if (sc->xl_ldata.xl_tx_tag) {
1706 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1707 sc->xl_ldata.xl_tx_dmamap);
1708 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1709 sc->xl_ldata.xl_tx_dmamap);
1710 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1713 mtx_destroy(&sc->xl_mtx);
1719 * Initialize the transmit descriptors.
1722 xl_list_tx_init(struct xl_softc *sc)
1724 struct xl_chain_data *cd;
1725 struct xl_list_data *ld;
1732 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1733 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1734 error = bus_dmamap_create(sc->xl_mtag, 0,
1735 &cd->xl_tx_chain[i].xl_map);
1738 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1739 i * sizeof(struct xl_list);
1740 if (i == (XL_TX_LIST_CNT - 1))
1741 cd->xl_tx_chain[i].xl_next = NULL;
1743 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1746 cd->xl_tx_free = &cd->xl_tx_chain[0];
1747 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1749 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1754 * Initialize the transmit descriptors.
1757 xl_list_tx_init_90xB(struct xl_softc *sc)
1759 struct xl_chain_data *cd;
1760 struct xl_list_data *ld;
1767 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1768 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1769 error = bus_dmamap_create(sc->xl_mtag, 0,
1770 &cd->xl_tx_chain[i].xl_map);
1773 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1774 i * sizeof(struct xl_list);
1775 if (i == (XL_TX_LIST_CNT - 1))
1776 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1778 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1780 cd->xl_tx_chain[i].xl_prev =
1781 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1783 cd->xl_tx_chain[i].xl_prev =
1784 &cd->xl_tx_chain[i - 1];
1787 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1788 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1794 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1799 * Initialize the RX descriptors and allocate mbufs for them. Note that
1800 * we arrange the descriptors in a closed ring, so that the last descriptor
1801 * points back to the first.
1804 xl_list_rx_init(struct xl_softc *sc)
1806 struct xl_chain_data *cd;
1807 struct xl_list_data *ld;
1816 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1817 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1818 error = bus_dmamap_create(sc->xl_mtag, 0,
1819 &cd->xl_rx_chain[i].xl_map);
1822 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1825 if (i == (XL_RX_LIST_CNT - 1))
1829 nextptr = ld->xl_rx_dmaaddr +
1830 next * sizeof(struct xl_list_onefrag);
1831 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1832 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1835 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1836 cd->xl_rx_head = &cd->xl_rx_chain[0];
1842 * Initialize an RX descriptor and attach an MBUF cluster.
1843 * If we fail to do so, we need to leave the old mbuf and
1844 * the old DMA map untouched so that it can be reused.
1847 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1849 struct mbuf *m_new = NULL;
1851 bus_dma_segment_t segs[1];
1856 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1860 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1862 /* Force longword alignment for packet payload. */
1863 m_adj(m_new, ETHER_ALIGN);
1865 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1866 segs, &nseg, BUS_DMA_NOWAIT);
1869 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1874 ("%s: too many DMA segments (%d)", __func__, nseg));
1876 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1878 c->xl_map = sc->xl_tmpmap;
1879 sc->xl_tmpmap = map;
1881 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1882 c->xl_ptr->xl_status = 0;
1883 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1884 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1889 xl_rx_resync(struct xl_softc *sc)
1891 struct xl_chain_onefrag *pos;
1896 pos = sc->xl_cdata.xl_rx_head;
1898 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1899 if (pos->xl_ptr->xl_status)
1904 if (i == XL_RX_LIST_CNT)
1907 sc->xl_cdata.xl_rx_head = pos;
1913 * A frame has been uploaded: pass the resulting mbuf chain up to
1914 * the higher level protocols.
1917 xl_rxeof(struct xl_softc *sc)
1920 struct ifnet *ifp = sc->xl_ifp;
1921 struct xl_chain_onefrag *cur_rx;
1927 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1928 BUS_DMASYNC_POSTREAD);
1929 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1930 #ifdef DEVICE_POLLING
1931 if (ifp->if_capenable & IFCAP_POLLING) {
1932 if (sc->rxcycles <= 0)
1937 cur_rx = sc->xl_cdata.xl_rx_head;
1938 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1939 total_len = rxstat & XL_RXSTAT_LENMASK;
1942 * Since we have told the chip to allow large frames,
1943 * we need to trap giant frame errors in software. We allow
1944 * a little more than the normal frame size to account for
1945 * frames with VLAN tags.
1947 if (total_len > XL_MAX_FRAMELEN)
1948 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1951 * If an error occurs, update stats, clear the
1952 * status word and leave the mbuf cluster in place:
1953 * it should simply get re-used next time this descriptor
1954 * comes up in the ring.
1956 if (rxstat & XL_RXSTAT_UP_ERROR) {
1958 cur_rx->xl_ptr->xl_status = 0;
1959 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1960 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1965 * If the error bit was not set, the upload complete
1966 * bit should be set which means we have a valid packet.
1967 * If not, something truly strange has happened.
1969 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1970 device_printf(sc->xl_dev,
1971 "bad receive status -- packet dropped\n");
1973 cur_rx->xl_ptr->xl_status = 0;
1974 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1975 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1979 /* No errors; receive the packet. */
1980 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1981 BUS_DMASYNC_POSTREAD);
1982 m = cur_rx->xl_mbuf;
1985 * Try to conjure up a new mbuf cluster. If that
1986 * fails, it means we have an out of memory condition and
1987 * should leave the buffer in place and continue. This will
1988 * result in a lost packet, but there's little else we
1989 * can do in this situation.
1991 if (xl_newbuf(sc, cur_rx)) {
1993 cur_rx->xl_ptr->xl_status = 0;
1994 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1995 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1998 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1999 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2002 m->m_pkthdr.rcvif = ifp;
2003 m->m_pkthdr.len = m->m_len = total_len;
2005 if (ifp->if_capenable & IFCAP_RXCSUM) {
2006 /* Do IP checksum checking. */
2007 if (rxstat & XL_RXSTAT_IPCKOK)
2008 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2009 if (!(rxstat & XL_RXSTAT_IPCKERR))
2010 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2011 if ((rxstat & XL_RXSTAT_TCPCOK &&
2012 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2013 (rxstat & XL_RXSTAT_UDPCKOK &&
2014 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2015 m->m_pkthdr.csum_flags |=
2016 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2017 m->m_pkthdr.csum_data = 0xffff;
2022 (*ifp->if_input)(ifp, m);
2026 * If we are running from the taskqueue, the interface
2027 * might have been stopped while we were passing the last
2028 * packet up the network stack.
2030 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2035 * Handle the 'end of channel' condition. When the upload
2036 * engine hits the end of the RX ring, it will stall. This
2037 * is our cue to flush the RX ring, reload the uplist pointer
2038 * register and unstall the engine.
2039 * XXX This is actually a little goofy. With the ThunderLAN
2040 * chip, you get an interrupt when the receiver hits the end
2041 * of the receive ring, which tells you exactly when you
2042 * you need to reload the ring pointer. Here we have to
2043 * fake it. I'm mad at myself for not being clever enough
2044 * to avoid the use of a goto here.
2046 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2047 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2048 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2050 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2051 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2052 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2058 * Taskqueue wrapper for xl_rxeof().
2061 xl_rxeof_task(void *arg, int pending)
2063 struct xl_softc *sc = (struct xl_softc *)arg;
2066 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
2072 * A frame was downloaded to the chip. It's safe for us to clean up
2076 xl_txeof(struct xl_softc *sc)
2078 struct xl_chain *cur_tx;
2079 struct ifnet *ifp = sc->xl_ifp;
2084 * Go through our tx list and free mbufs for those
2085 * frames that have been uploaded. Note: the 3c905B
2086 * sets a special bit in the status word to let us
2087 * know that a frame has been downloaded, but the
2088 * original 3c900/3c905 adapters don't do that.
2089 * Consequently, we have to use a different test if
2090 * xl_type != XL_TYPE_905B.
2092 while (sc->xl_cdata.xl_tx_head != NULL) {
2093 cur_tx = sc->xl_cdata.xl_tx_head;
2095 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2098 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2099 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2100 BUS_DMASYNC_POSTWRITE);
2101 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2102 m_freem(cur_tx->xl_mbuf);
2103 cur_tx->xl_mbuf = NULL;
2106 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2107 sc->xl_cdata.xl_tx_free = cur_tx;
2110 if (sc->xl_cdata.xl_tx_head == NULL) {
2111 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2112 sc->xl_wdog_timer = 0;
2113 sc->xl_cdata.xl_tx_tail = NULL;
2115 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2116 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2117 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2118 sc->xl_cdata.xl_tx_head->xl_phys);
2119 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2125 xl_txeof_90xB(struct xl_softc *sc)
2127 struct xl_chain *cur_tx = NULL;
2128 struct ifnet *ifp = sc->xl_ifp;
2133 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2134 BUS_DMASYNC_POSTREAD);
2135 idx = sc->xl_cdata.xl_tx_cons;
2136 while (idx != sc->xl_cdata.xl_tx_prod) {
2137 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2139 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2140 XL_TXSTAT_DL_COMPLETE))
2143 if (cur_tx->xl_mbuf != NULL) {
2144 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2145 BUS_DMASYNC_POSTWRITE);
2146 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2147 m_freem(cur_tx->xl_mbuf);
2148 cur_tx->xl_mbuf = NULL;
2153 sc->xl_cdata.xl_tx_cnt--;
2154 XL_INC(idx, XL_TX_LIST_CNT);
2157 if (sc->xl_cdata.xl_tx_cnt == 0)
2158 sc->xl_wdog_timer = 0;
2159 sc->xl_cdata.xl_tx_cons = idx;
2162 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2166 * TX 'end of channel' interrupt handler. Actually, we should
2167 * only get a 'TX complete' interrupt if there's a transmit error,
2168 * so this is really TX error handler.
2171 xl_txeoc(struct xl_softc *sc)
2177 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2178 if (txstat & XL_TXSTATUS_UNDERRUN ||
2179 txstat & XL_TXSTATUS_JABBER ||
2180 txstat & XL_TXSTATUS_RECLAIM) {
2181 device_printf(sc->xl_dev,
2182 "transmission error: %x\n", txstat);
2183 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2185 if (sc->xl_type == XL_TYPE_905B) {
2186 if (sc->xl_cdata.xl_tx_cnt) {
2190 i = sc->xl_cdata.xl_tx_cons;
2191 c = &sc->xl_cdata.xl_tx_chain[i];
2192 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2194 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2197 if (sc->xl_cdata.xl_tx_head != NULL)
2198 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2199 sc->xl_cdata.xl_tx_head->xl_phys);
2202 * Remember to set this for the
2203 * first generation 3c90X chips.
2205 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2206 if (txstat & XL_TXSTATUS_UNDERRUN &&
2207 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2208 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2209 device_printf(sc->xl_dev,
2210 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2212 CSR_WRITE_2(sc, XL_COMMAND,
2213 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2214 if (sc->xl_type == XL_TYPE_905B) {
2215 CSR_WRITE_2(sc, XL_COMMAND,
2216 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2218 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2219 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2221 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2222 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2225 * Write an arbitrary byte to the TX_STATUS register
2226 * to clear this interrupt/error and advance to the next.
2228 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2235 struct xl_softc *sc = arg;
2236 struct ifnet *ifp = sc->xl_ifp;
2241 #ifdef DEVICE_POLLING
2242 if (ifp->if_capenable & IFCAP_POLLING) {
2248 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS &&
2250 CSR_WRITE_2(sc, XL_COMMAND,
2251 XL_CMD_INTR_ACK|(status & XL_INTRS));
2253 if (status & XL_STAT_UP_COMPLETE) {
2256 curpkts = ifp->if_ipackets;
2258 if (curpkts == ifp->if_ipackets) {
2259 while (xl_rx_resync(sc))
2264 if (status & XL_STAT_DOWN_COMPLETE) {
2265 if (sc->xl_type == XL_TYPE_905B)
2271 if (status & XL_STAT_TX_COMPLETE) {
2276 if (status & XL_STAT_ADFAIL) {
2281 if (status & XL_STAT_STATSOFLOW) {
2282 sc->xl_stats_no_timeout = 1;
2283 xl_stats_update_locked(sc);
2284 sc->xl_stats_no_timeout = 0;
2288 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2289 if (sc->xl_type == XL_TYPE_905B)
2290 xl_start_90xB_locked(ifp);
2292 xl_start_locked(ifp);
2298 #ifdef DEVICE_POLLING
2300 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2302 struct xl_softc *sc = ifp->if_softc;
2305 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2306 xl_poll_locked(ifp, cmd, count);
2311 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2313 struct xl_softc *sc = ifp->if_softc;
2317 sc->rxcycles = count;
2319 if (sc->xl_type == XL_TYPE_905B)
2324 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2325 if (sc->xl_type == XL_TYPE_905B)
2326 xl_start_90xB_locked(ifp);
2328 xl_start_locked(ifp);
2331 if (cmd == POLL_AND_CHECK_STATUS) {
2334 status = CSR_READ_2(sc, XL_STATUS);
2335 if (status & XL_INTRS && status != 0xFFFF) {
2336 CSR_WRITE_2(sc, XL_COMMAND,
2337 XL_CMD_INTR_ACK|(status & XL_INTRS));
2339 if (status & XL_STAT_TX_COMPLETE) {
2344 if (status & XL_STAT_ADFAIL) {
2349 if (status & XL_STAT_STATSOFLOW) {
2350 sc->xl_stats_no_timeout = 1;
2351 xl_stats_update_locked(sc);
2352 sc->xl_stats_no_timeout = 0;
2357 #endif /* DEVICE_POLLING */
2360 * XXX: This is an entry point for callout which needs to take the lock.
2363 xl_stats_update(void *xsc)
2365 struct xl_softc *sc = xsc;
2369 if (xl_watchdog(sc) == EJUSTRETURN)
2372 xl_stats_update_locked(sc);
2376 xl_stats_update_locked(struct xl_softc *sc)
2378 struct ifnet *ifp = sc->xl_ifp;
2379 struct xl_stats xl_stats;
2382 struct mii_data *mii = NULL;
2386 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2388 if (sc->xl_miibus != NULL)
2389 mii = device_get_softc(sc->xl_miibus);
2391 p = (u_int8_t *)&xl_stats;
2393 /* Read all the stats registers. */
2396 for (i = 0; i < 16; i++)
2397 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2399 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2401 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2402 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2405 * Boomerang and cyclone chips have an extra stats counter
2406 * in window 4 (BadSSD). We have to read this too in order
2407 * to clear out all the stats registers and avoid a statsoflow
2411 CSR_READ_1(sc, XL_W4_BADSSD);
2413 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2418 if (!sc->xl_stats_no_timeout)
2419 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2423 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2424 * pointers to the fragment pointers.
2427 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2430 struct ifnet *ifp = sc->xl_ifp;
2431 int error, i, nseg, total_len;
2436 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2437 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2439 if (error && error != EFBIG) {
2440 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2445 * Handle special case: we used up all 63 fragments,
2446 * but we have more mbufs left in the chain. Copy the
2447 * data into an mbuf cluster. Note that we don't
2448 * bother clearing the values in the other fragment
2449 * pointers/counters; it wouldn't gain us anything,
2450 * and would waste cycles.
2453 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS);
2454 if (m_new == NULL) {
2461 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2462 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2466 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2471 KASSERT(nseg <= XL_MAXFRAGS,
2472 ("%s: too many DMA segments (%d)", __func__, nseg));
2480 for (i = 0; i < nseg; i++) {
2481 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2482 ("segment size too large"));
2483 c->xl_ptr->xl_frag[i].xl_addr =
2484 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2485 c->xl_ptr->xl_frag[i].xl_len =
2486 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2487 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2489 c->xl_ptr->xl_frag[nseg - 1].xl_len =
2490 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG);
2491 c->xl_ptr->xl_status = htole32(total_len);
2492 c->xl_ptr->xl_next = 0;
2494 if (sc->xl_type == XL_TYPE_905B) {
2495 status = XL_TXSTAT_RND_DEFEAT;
2497 #ifndef XL905B_TXCSUM_BROKEN
2498 if (m_head->m_pkthdr.csum_flags) {
2499 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2500 status |= XL_TXSTAT_IPCKSUM;
2501 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2502 status |= XL_TXSTAT_TCPCKSUM;
2503 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2504 status |= XL_TXSTAT_UDPCKSUM;
2507 c->xl_ptr->xl_status = htole32(status);
2510 c->xl_mbuf = *m_head;
2511 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2516 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2517 * to the mbuf data regions directly in the transmit lists. We also save a
2518 * copy of the pointers since the transmit list fragment pointers are
2519 * physical addresses.
2523 xl_start(struct ifnet *ifp)
2525 struct xl_softc *sc = ifp->if_softc;
2529 if (sc->xl_type == XL_TYPE_905B)
2530 xl_start_90xB_locked(ifp);
2532 xl_start_locked(ifp);
2538 xl_start_locked(struct ifnet *ifp)
2540 struct xl_softc *sc = ifp->if_softc;
2541 struct mbuf *m_head = NULL;
2542 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2549 * Check for an available queue slot. If there are none,
2552 if (sc->xl_cdata.xl_tx_free == NULL) {
2555 if (sc->xl_cdata.xl_tx_free == NULL) {
2556 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2561 start_tx = sc->xl_cdata.xl_tx_free;
2563 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2564 sc->xl_cdata.xl_tx_free != NULL;) {
2565 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2569 /* Pick a descriptor off the free list. */
2570 cur_tx = sc->xl_cdata.xl_tx_free;
2572 /* Pack the data into the descriptor. */
2573 error = xl_encap(sc, cur_tx, &m_head);
2577 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2578 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2582 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2583 cur_tx->xl_next = NULL;
2585 /* Chain it together. */
2587 prev->xl_next = cur_tx;
2588 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2593 * If there's a BPF listener, bounce a copy of this frame
2596 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2600 * If there are no packets queued, bail.
2606 * Place the request for the upload interrupt
2607 * in the last descriptor in the chain. This way, if
2608 * we're chaining several packets at once, we'll only
2609 * get an interrupt once for the whole chain rather than
2610 * once for each packet.
2612 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2614 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2615 BUS_DMASYNC_PREWRITE);
2618 * Queue the packets. If the TX channel is clear, update
2619 * the downlist pointer register.
2621 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2624 if (sc->xl_cdata.xl_tx_head != NULL) {
2625 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2626 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2627 htole32(start_tx->xl_phys);
2628 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2629 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2630 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2631 sc->xl_cdata.xl_tx_tail = cur_tx;
2633 sc->xl_cdata.xl_tx_head = start_tx;
2634 sc->xl_cdata.xl_tx_tail = cur_tx;
2636 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2637 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2639 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2644 * Set a timeout in case the chip goes out to lunch.
2646 sc->xl_wdog_timer = 5;
2649 * XXX Under certain conditions, usually on slower machines
2650 * where interrupts may be dropped, it's possible for the
2651 * adapter to chew up all the buffers in the receive ring
2652 * and stall, without us being able to do anything about it.
2653 * To guard against this, we need to make a pass over the
2654 * RX queue to make sure there aren't any packets pending.
2655 * Doing it here means we can flush the receive ring at the
2656 * same time the chip is DMAing the transmit descriptors we
2659 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2660 * nature of their chips in all their marketing literature;
2661 * we may as well take advantage of it. :)
2663 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2667 xl_start_90xB_locked(struct ifnet *ifp)
2669 struct xl_softc *sc = ifp->if_softc;
2670 struct mbuf *m_head = NULL;
2671 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2676 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
2679 idx = sc->xl_cdata.xl_tx_prod;
2680 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2682 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2683 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2684 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2685 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2689 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2693 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2695 /* Pack the data into the descriptor. */
2696 error = xl_encap(sc, cur_tx, &m_head);
2700 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2701 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2705 /* Chain it together. */
2707 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2711 * If there's a BPF listener, bounce a copy of this frame
2714 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2716 XL_INC(idx, XL_TX_LIST_CNT);
2717 sc->xl_cdata.xl_tx_cnt++;
2721 * If there are no packets queued, bail.
2727 * Place the request for the upload interrupt
2728 * in the last descriptor in the chain. This way, if
2729 * we're chaining several packets at once, we'll only
2730 * get an interrupt once for the whole chain rather than
2731 * once for each packet.
2733 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2735 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2736 BUS_DMASYNC_PREWRITE);
2738 /* Start transmission */
2739 sc->xl_cdata.xl_tx_prod = idx;
2740 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2743 * Set a timeout in case the chip goes out to lunch.
2745 sc->xl_wdog_timer = 5;
2751 struct xl_softc *sc = xsc;
2759 xl_init_locked(struct xl_softc *sc)
2761 struct ifnet *ifp = sc->xl_ifp;
2763 u_int16_t rxfilt = 0;
2764 struct mii_data *mii = NULL;
2769 * Cancel pending I/O and free all RX/TX buffers.
2773 if (sc->xl_miibus == NULL) {
2774 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2777 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2781 if (sc->xl_miibus != NULL)
2782 mii = device_get_softc(sc->xl_miibus);
2784 /* Init our MAC address */
2786 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2787 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2788 IF_LLADDR(sc->xl_ifp)[i]);
2791 /* Clear the station mask. */
2792 for (i = 0; i < 3; i++)
2793 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2795 /* Reset TX and RX. */
2796 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2801 /* Init circular RX list. */
2802 error = xl_list_rx_init(sc);
2804 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2810 /* Init TX descriptors. */
2811 if (sc->xl_type == XL_TYPE_905B)
2812 error = xl_list_tx_init_90xB(sc);
2814 error = xl_list_tx_init(sc);
2816 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2823 * Set the TX freethresh value.
2824 * Note that this has no effect on 3c905B "cyclone"
2825 * cards but is required for 3c900/3c905 "boomerang"
2826 * cards in order to enable the download engine.
2828 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2830 /* Set the TX start threshold for best performance. */
2831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2834 * If this is a 3c905B, also set the tx reclaim threshold.
2835 * This helps cut down on the number of tx reclaim errors
2836 * that could happen on a busy network. The chip multiplies
2837 * the register value by 16 to obtain the actual threshold
2838 * in bytes, so we divide by 16 when setting the value here.
2839 * The existing threshold value can be examined by reading
2840 * the register at offset 9 in window 5.
2842 if (sc->xl_type == XL_TYPE_905B) {
2843 CSR_WRITE_2(sc, XL_COMMAND,
2844 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2847 /* Set RX filter bits. */
2849 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2851 /* Set the individual bit to receive frames for this host only. */
2852 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2854 /* If we want promiscuous mode, set the allframes bit. */
2855 if (ifp->if_flags & IFF_PROMISC) {
2856 rxfilt |= XL_RXFILTER_ALLFRAMES;
2857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2859 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2864 * Set capture broadcast bit to capture broadcast frames.
2866 if (ifp->if_flags & IFF_BROADCAST) {
2867 rxfilt |= XL_RXFILTER_BROADCAST;
2868 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2870 rxfilt &= ~XL_RXFILTER_BROADCAST;
2871 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2875 * Program the multicast filter, if necessary.
2877 if (sc->xl_type == XL_TYPE_905B)
2878 xl_setmulti_hash(sc);
2883 * Load the address of the RX list. We have to
2884 * stall the upload engine before we can manipulate
2885 * the uplist pointer register, then unstall it when
2886 * we're finished. We also have to wait for the
2887 * stall command to complete before proceeding.
2888 * Note that we have to do this after any RX resets
2889 * have completed since the uplist register is cleared
2892 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2894 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2898 if (sc->xl_type == XL_TYPE_905B) {
2899 /* Set polling interval */
2900 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2901 /* Load the address of the TX list */
2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2904 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2905 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2911 * If the coax transceiver is on, make sure to enable
2912 * the DC-DC converter.
2915 if (sc->xl_xcvr == XL_XCVR_COAX)
2916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2921 * increase packet size to allow reception of 802.1q or ISL packets.
2922 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2923 * control register. For 3c90xB/C chips, use the RX packet size
2927 if (sc->xl_type == XL_TYPE_905B)
2928 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2931 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2932 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2933 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2936 /* Clear out the stats counters. */
2937 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2938 sc->xl_stats_no_timeout = 1;
2939 xl_stats_update_locked(sc);
2940 sc->xl_stats_no_timeout = 0;
2942 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2943 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2946 * Enable interrupts.
2948 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2949 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2950 #ifdef DEVICE_POLLING
2951 /* Disable interrupts if we are polling. */
2952 if (ifp->if_capenable & IFCAP_POLLING)
2953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2957 if (sc->xl_flags & XL_FLAG_FUNCREG)
2958 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2960 /* Set the RX early threshold */
2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2962 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2964 /* Enable receiver and transmitter. */
2965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2970 /* XXX Downcall to miibus. */
2974 /* Select window 7 for normal operations. */
2977 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2978 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2980 sc->xl_wdog_timer = 0;
2981 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2985 * Set media options.
2988 xl_ifmedia_upd(struct ifnet *ifp)
2990 struct xl_softc *sc = ifp->if_softc;
2991 struct ifmedia *ifm = NULL;
2992 struct mii_data *mii = NULL;
2996 if (sc->xl_miibus != NULL)
2997 mii = device_get_softc(sc->xl_miibus);
3001 ifm = &mii->mii_media;
3003 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3008 xl_setmode(sc, ifm->ifm_media);
3013 if (sc->xl_media & XL_MEDIAOPT_MII ||
3014 sc->xl_media & XL_MEDIAOPT_BTX ||
3015 sc->xl_media & XL_MEDIAOPT_BT4) {
3018 xl_setmode(sc, ifm->ifm_media);
3027 * Report current media status.
3030 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3032 struct xl_softc *sc = ifp->if_softc;
3034 u_int16_t status = 0;
3035 struct mii_data *mii = NULL;
3039 if (sc->xl_miibus != NULL)
3040 mii = device_get_softc(sc->xl_miibus);
3043 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3046 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3047 icfg >>= XL_ICFG_CONNECTOR_BITS;
3049 ifmr->ifm_active = IFM_ETHER;
3050 ifmr->ifm_status = IFM_AVALID;
3052 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3053 ifmr->ifm_status |= IFM_ACTIVE;
3057 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3058 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3059 ifmr->ifm_active |= IFM_FDX;
3061 ifmr->ifm_active |= IFM_HDX;
3064 if (sc->xl_type == XL_TYPE_905B &&
3065 sc->xl_media == XL_MEDIAOPT_10FL) {
3066 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3067 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3068 ifmr->ifm_active |= IFM_FDX;
3070 ifmr->ifm_active |= IFM_HDX;
3072 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3075 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3078 * XXX MII and BTX/AUTO should be separate cases.
3081 case XL_XCVR_100BTX:
3086 ifmr->ifm_active = mii->mii_media_active;
3087 ifmr->ifm_status = mii->mii_media_status;
3090 case XL_XCVR_100BFX:
3091 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3094 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3102 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3104 struct xl_softc *sc = ifp->if_softc;
3105 struct ifreq *ifr = (struct ifreq *) data;
3107 struct mii_data *mii = NULL;
3115 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3116 if (ifp->if_flags & IFF_UP) {
3117 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3118 ifp->if_flags & IFF_PROMISC &&
3119 !(sc->xl_if_flags & IFF_PROMISC)) {
3120 rxfilt |= XL_RXFILTER_ALLFRAMES;
3121 CSR_WRITE_2(sc, XL_COMMAND,
3122 XL_CMD_RX_SET_FILT|rxfilt);
3124 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3125 !(ifp->if_flags & IFF_PROMISC) &&
3126 sc->xl_if_flags & IFF_PROMISC) {
3127 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3128 CSR_WRITE_2(sc, XL_COMMAND,
3129 XL_CMD_RX_SET_FILT|rxfilt);
3132 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3136 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3139 sc->xl_if_flags = ifp->if_flags;
3145 /* XXX Downcall from if_addmulti() possibly with locks held. */
3147 if (sc->xl_type == XL_TYPE_905B)
3148 xl_setmulti_hash(sc);
3156 if (sc->xl_miibus != NULL)
3157 mii = device_get_softc(sc->xl_miibus);
3159 error = ifmedia_ioctl(ifp, ifr,
3160 &sc->ifmedia, command);
3162 error = ifmedia_ioctl(ifp, ifr,
3163 &mii->mii_media, command);
3166 #ifdef DEVICE_POLLING
3167 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3168 !(ifp->if_capenable & IFCAP_POLLING)) {
3169 error = ether_poll_register(xl_poll, ifp);
3173 /* Disable interrupts */
3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3175 ifp->if_capenable |= IFCAP_POLLING;
3179 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3180 ifp->if_capenable & IFCAP_POLLING) {
3181 error = ether_poll_deregister(ifp);
3182 /* Enable interrupts. */
3184 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
3185 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
3186 if (sc->xl_flags & XL_FLAG_FUNCREG)
3187 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
3189 ifp->if_capenable &= ~IFCAP_POLLING;
3193 #endif /* DEVICE_POLLING */
3195 ifp->if_capenable = ifr->ifr_reqcap;
3196 if (ifp->if_capenable & IFCAP_TXCSUM)
3197 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3199 ifp->if_hwassist = 0;
3203 error = ether_ioctl(ifp, command, data);
3211 xl_watchdog(struct xl_softc *sc)
3213 struct ifnet *ifp = sc->xl_ifp;
3214 u_int16_t status = 0;
3218 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3223 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3224 device_printf(sc->xl_dev, "watchdog timeout\n");
3226 if (status & XL_MEDIASTAT_CARRIER)
3227 device_printf(sc->xl_dev,
3228 "no carrier - transceiver cable problem?\n");
3236 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3237 if (sc->xl_type == XL_TYPE_905B)
3238 xl_start_90xB_locked(ifp);
3240 xl_start_locked(ifp);
3243 return (EJUSTRETURN);
3247 * Stop the adapter and free any mbufs allocated to the
3251 xl_stop(struct xl_softc *sc)
3254 struct ifnet *ifp = sc->xl_ifp;
3258 sc->xl_wdog_timer = 0;
3260 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3263 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3265 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3266 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3270 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3272 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3276 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3277 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3279 if (sc->xl_flags & XL_FLAG_FUNCREG)
3280 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3282 /* Stop the stats updater. */
3283 callout_stop(&sc->xl_stat_callout);
3286 * Free data in the RX lists.
3288 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3289 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3290 bus_dmamap_unload(sc->xl_mtag,
3291 sc->xl_cdata.xl_rx_chain[i].xl_map);
3292 bus_dmamap_destroy(sc->xl_mtag,
3293 sc->xl_cdata.xl_rx_chain[i].xl_map);
3294 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3295 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3298 if (sc->xl_ldata.xl_rx_list != NULL)
3299 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3301 * Free the TX list buffers.
3303 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3304 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3305 bus_dmamap_unload(sc->xl_mtag,
3306 sc->xl_cdata.xl_tx_chain[i].xl_map);
3307 bus_dmamap_destroy(sc->xl_mtag,
3308 sc->xl_cdata.xl_tx_chain[i].xl_map);
3309 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3310 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3313 if (sc->xl_ldata.xl_tx_list != NULL)
3314 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3316 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3320 * Stop all chip I/O so that the kernel's probe routines don't
3321 * get confused by errant DMAs when rebooting.
3324 xl_shutdown(device_t dev)
3326 struct xl_softc *sc;
3328 sc = device_get_softc(dev);
3339 xl_suspend(device_t dev)
3341 struct xl_softc *sc;
3343 sc = device_get_softc(dev);
3353 xl_resume(device_t dev)
3355 struct xl_softc *sc;
3358 sc = device_get_softc(dev);
3364 if (ifp->if_flags & IFF_UP)