2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/msgbuf.h>
124 #include <sys/mutex.h>
125 #include <sys/proc.h>
126 #include <sys/sysctl.h>
127 #include <sys/systm.h>
128 #include <sys/vmmeter.h>
132 #include <dev/ofw/openfirm.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
145 #include <machine/cpu.h>
146 #include <machine/platform.h>
147 #include <machine/frame.h>
148 #include <machine/md_var.h>
149 #include <machine/psl.h>
150 #include <machine/bat.h>
151 #include <machine/pte.h>
152 #include <machine/sr.h>
153 #include <machine/trap.h>
154 #include <machine/mmuvar.h>
160 #define TODO panic("%s: not implemented", __func__);
162 static __inline u_int32_t
163 cntlzw(volatile u_int32_t a) {
165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a));
169 static __inline uint64_t
170 va_to_vsid(pmap_t pm, vm_offset_t va)
172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
175 #define PTESYNC() __asm __volatile("ptesync");
176 #define TLBSYNC() __asm __volatile("tlbsync; ptesync");
177 #define SYNC() __asm __volatile("sync");
178 #define EIEIO() __asm __volatile("eieio");
181 * The tlbie instruction must be executed in 64-bit mode
182 * so we have to twiddle MSR[SF] around every invocation.
183 * Just to add to the fun, exceptions must be off as well
184 * so that we can't trap in 64-bit mode. What a pain.
186 struct mtx tlbie_mutex;
189 TLBIE(pmap_t pmap, vm_offset_t va) {
191 register_t vpn_hi, vpn_lo;
195 vpn = (uint64_t)(va & ADDR_PIDX);
197 vpn |= (va_to_vsid(pmap,va) << 28);
198 vpn &= ~(0xffffULL << 48);
200 vpn_hi = (uint32_t)(vpn >> 32);
201 vpn_lo = (uint32_t)vpn;
203 mtx_lock_spin(&tlbie_mutex);
219 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1)
221 mtx_unlock_spin(&tlbie_mutex);
224 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync()
225 #define ENABLE_TRANS(msr) mtmsr(msr); isync()
227 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
228 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
229 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
230 #define VSID_HASH_MASK 0x0000007fffffffffULL
232 #define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */
233 #define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */
234 #define PVO_WIRED 0x010UL /* PVO entry is wired */
235 #define PVO_MANAGED 0x020UL /* PVO entry is managed */
236 #define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during
238 #define PVO_FAKE 0x100UL /* fictitious phys page */
239 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF)
240 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE)
241 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
242 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
243 #define PVO_PTEGIDX_CLR(pvo) \
244 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
245 #define PVO_PTEGIDX_SET(pvo, i) \
246 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
248 #define MOEA_PVO_CHECK(pvo)
250 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex)
251 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex);
252 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED)
257 vm_offset_t om_pa_hi;
258 vm_offset_t om_pa_lo;
263 * Map of physical memory regions.
265 static struct mem_region *regions;
266 static struct mem_region *pregions;
267 extern u_int phys_avail_count;
268 extern int regions_sz, pregions_sz;
269 extern int ofw_real_mode;
271 extern struct pmap ofw_pmap;
273 extern void bs_remap_earlyboot(void);
277 * Lock for the pteg and pvo tables.
279 struct mtx moea64_table_mutex;
280 struct mtx moea64_slb_mutex;
285 static struct lpteg *moea64_pteg_table;
286 u_int moea64_pteg_count;
287 u_int moea64_pteg_mask;
292 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */
293 struct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */
294 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged);
296 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
297 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */
299 #define BPVO_POOL_SIZE 327680
300 static struct pvo_entry *moea64_bpvo_pool;
301 static int moea64_bpvo_pool_index = 0;
303 #define VSID_NBPW (sizeof(u_int32_t) * 8)
304 static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW];
306 static boolean_t moea64_initialized = FALSE;
311 u_int moea64_pte_valid = 0;
312 u_int moea64_pte_overflow = 0;
313 u_int moea64_pvo_entries = 0;
314 u_int moea64_pvo_enter_calls = 0;
315 u_int moea64_pvo_remove_calls = 0;
316 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
317 &moea64_pte_valid, 0, "");
318 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
319 &moea64_pte_overflow, 0, "");
320 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
321 &moea64_pvo_entries, 0, "");
322 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
323 &moea64_pvo_enter_calls, 0, "");
324 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
325 &moea64_pvo_remove_calls, 0, "");
327 vm_offset_t moea64_scratchpage_va[2];
328 struct lpte *moea64_scratchpage_pte[2];
329 struct mtx moea64_scratchpage_mtx;
332 * Allocate physical memory for use in moea64_bootstrap.
334 static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int);
339 static int moea64_pte_insert(u_int, struct lpte *);
344 static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
345 vm_offset_t, vm_offset_t, uint64_t, int);
346 static void moea64_pvo_remove(struct pvo_entry *, int);
347 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *);
348 static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int);
353 static void moea64_bridge_bootstrap(mmu_t mmup,
354 vm_offset_t kernelstart, vm_offset_t kernelend);
355 static void moea64_bridge_cpu_bootstrap(mmu_t, int ap);
356 static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t,
357 vm_prot_t, boolean_t);
358 static boolean_t moea64_query_bit(vm_page_t, u_int64_t);
359 static u_int moea64_clear_bit(vm_page_t, u_int64_t, u_int64_t *);
360 static void moea64_kremove(mmu_t, vm_offset_t);
361 static void moea64_syncicache(pmap_t pmap, vm_offset_t va,
362 vm_offset_t pa, vm_size_t sz);
363 static void tlbia(void);
366 * Kernel MMU interface
368 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
369 void moea64_clear_modify(mmu_t, vm_page_t);
370 void moea64_clear_reference(mmu_t, vm_page_t);
371 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
372 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
373 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
375 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
376 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
377 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
378 void moea64_init(mmu_t);
379 boolean_t moea64_is_modified(mmu_t, vm_page_t);
380 boolean_t moea64_ts_referenced(mmu_t, vm_page_t);
381 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
382 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
383 int moea64_page_wired_mappings(mmu_t, vm_page_t);
384 void moea64_pinit(mmu_t, pmap_t);
385 void moea64_pinit0(mmu_t, pmap_t);
386 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
387 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
388 void moea64_qremove(mmu_t, vm_offset_t, int);
389 void moea64_release(mmu_t, pmap_t);
390 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
391 void moea64_remove_all(mmu_t, vm_page_t);
392 void moea64_remove_write(mmu_t, vm_page_t);
393 void moea64_zero_page(mmu_t, vm_page_t);
394 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
395 void moea64_zero_page_idle(mmu_t, vm_page_t);
396 void moea64_activate(mmu_t, struct thread *);
397 void moea64_deactivate(mmu_t, struct thread *);
398 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t);
399 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
400 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
401 vm_offset_t moea64_kextract(mmu_t, vm_offset_t);
402 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
403 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
404 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t);
405 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
406 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
408 static mmu_method_t moea64_bridge_methods[] = {
409 MMUMETHOD(mmu_change_wiring, moea64_change_wiring),
410 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
411 MMUMETHOD(mmu_clear_reference, moea64_clear_reference),
412 MMUMETHOD(mmu_copy_page, moea64_copy_page),
413 MMUMETHOD(mmu_enter, moea64_enter),
414 MMUMETHOD(mmu_enter_object, moea64_enter_object),
415 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
416 MMUMETHOD(mmu_extract, moea64_extract),
417 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
418 MMUMETHOD(mmu_init, moea64_init),
419 MMUMETHOD(mmu_is_modified, moea64_is_modified),
420 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
421 MMUMETHOD(mmu_map, moea64_map),
422 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
423 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
424 MMUMETHOD(mmu_pinit, moea64_pinit),
425 MMUMETHOD(mmu_pinit0, moea64_pinit0),
426 MMUMETHOD(mmu_protect, moea64_protect),
427 MMUMETHOD(mmu_qenter, moea64_qenter),
428 MMUMETHOD(mmu_qremove, moea64_qremove),
429 MMUMETHOD(mmu_release, moea64_release),
430 MMUMETHOD(mmu_remove, moea64_remove),
431 MMUMETHOD(mmu_remove_all, moea64_remove_all),
432 MMUMETHOD(mmu_remove_write, moea64_remove_write),
433 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
434 MMUMETHOD(mmu_zero_page, moea64_zero_page),
435 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
436 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle),
437 MMUMETHOD(mmu_activate, moea64_activate),
438 MMUMETHOD(mmu_deactivate, moea64_deactivate),
439 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
441 /* Internal interfaces */
442 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap),
443 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap),
444 MMUMETHOD(mmu_mapdev, moea64_mapdev),
445 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
446 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
447 MMUMETHOD(mmu_kextract, moea64_kextract),
448 MMUMETHOD(mmu_kenter, moea64_kenter),
449 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
450 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
455 static mmu_def_t oea64_bridge_mmu = {
457 moea64_bridge_methods,
460 MMU_DEF(oea64_bridge_mmu);
462 static __inline u_int
463 va_to_pteg(uint64_t vsid, vm_offset_t addr)
467 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
469 return (hash & moea64_pteg_mask);
472 static __inline struct pvo_head *
473 vm_page_to_pvoh(vm_page_t m)
476 return (&m->md.mdpg_pvoh);
480 moea64_attr_clear(vm_page_t m, u_int64_t ptebit)
483 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
484 m->md.mdpg_attrs &= ~ptebit;
487 static __inline u_int64_t
488 moea64_attr_fetch(vm_page_t m)
491 return (m->md.mdpg_attrs);
495 moea64_attr_save(vm_page_t m, u_int64_t ptebit)
498 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
499 m->md.mdpg_attrs |= ptebit;
503 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
509 * Construct a PTE. Default to IMB initially. Valid bit only gets
510 * set when the real pte is set in memory.
512 * Note: Don't set the valid bit for correct operation of tlb update.
514 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
515 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
521 moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt)
526 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG);
530 moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit)
535 * As shown in Section 7.6.3.2.3
537 pt->pte_lo &= ~ptebit;
542 moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt)
546 pvo_pt->pte_hi |= LPTE_VALID;
549 * Update the PTE as defined in section 7.6.3.1.
550 * Note that the REF/CHG bits are from pvo_pt and thus should have
551 * been saved so this routine can restore them (if desired).
553 pt->pte_lo = pvo_pt->pte_lo;
555 pt->pte_hi = pvo_pt->pte_hi;
561 moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va)
564 pvo_pt->pte_hi &= ~LPTE_VALID;
567 * Force the reg & chg bits back into the PTEs.
572 * Invalidate the pte.
574 pt->pte_hi &= ~LPTE_VALID;
578 * Save the reg & chg bits.
580 moea64_pte_synch(pt, pvo_pt);
585 moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va)
591 moea64_pte_unset(pt, pvo_pt, pmap, va);
592 moea64_pte_set(pt, pvo_pt);
593 if (pmap == kernel_pmap)
597 static __inline uint64_t
598 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
603 if (ma != VM_MEMATTR_DEFAULT) {
605 case VM_MEMATTR_UNCACHEABLE:
606 return (LPTE_I | LPTE_G);
607 case VM_MEMATTR_WRITE_COMBINING:
608 case VM_MEMATTR_WRITE_BACK:
609 case VM_MEMATTR_PREFETCHABLE:
611 case VM_MEMATTR_WRITE_THROUGH:
612 return (LPTE_W | LPTE_M);
617 * Assume the page is cache inhibited and access is guarded unless
618 * it's in our available memory array.
620 pte_lo = LPTE_I | LPTE_G;
621 for (i = 0; i < pregions_sz; i++) {
622 if ((pa >= pregions[i].mr_start) &&
623 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
624 pte_lo &= ~(LPTE_I | LPTE_G);
634 * Quick sort callout for comparing memory regions.
636 static int mr_cmp(const void *a, const void *b);
637 static int om_cmp(const void *a, const void *b);
640 mr_cmp(const void *a, const void *b)
642 const struct mem_region *regiona;
643 const struct mem_region *regionb;
647 if (regiona->mr_start < regionb->mr_start)
649 else if (regiona->mr_start > regionb->mr_start)
656 om_cmp(const void *a, const void *b)
658 const struct ofw_map *mapa;
659 const struct ofw_map *mapb;
663 if (mapa->om_pa_hi < mapb->om_pa_hi)
665 else if (mapa->om_pa_hi > mapb->om_pa_hi)
667 else if (mapa->om_pa_lo < mapb->om_pa_lo)
669 else if (mapa->om_pa_lo > mapb->om_pa_lo)
676 moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap)
681 * Initialize segment registers and MMU
684 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync();
685 for (i = 0; i < 16; i++) {
686 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
688 __asm __volatile ("ptesync; mtsdr1 %0; isync"
689 :: "r"((u_int)moea64_pteg_table
690 | (32 - cntlzw(moea64_pteg_mask >> 11))));
695 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
697 struct ofw_map translations[sz/sizeof(struct ofw_map)];
703 bzero(translations, sz);
704 if (OF_getprop(mmu, "translations", translations, sz) == -1)
705 panic("moea64_bootstrap: can't get ofw translations");
707 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
708 sz /= sizeof(*translations);
709 qsort(translations, sz, sizeof (*translations), om_cmp);
711 for (i = 0, ofw_mappings = 0; i < sz; i++) {
712 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
713 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va,
714 translations[i].om_len);
716 if (translations[i].om_pa_lo % PAGE_SIZE)
717 panic("OFW translation not page-aligned!");
719 if (translations[i].om_pa_hi)
720 panic("OFW translations above 32-bit boundary!");
722 pa_base = translations[i].om_pa_lo;
724 /* Now enter the pages for this mapping */
727 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
728 moea64_kenter(mmup, translations[i].om_va + off,
738 moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
745 vm_size_t size, physsz, hwphyssz;
746 vm_offset_t pa, va, off;
750 /* We don't have a direct map since there is no BAT */
753 /* Make sure battable is zero, since we have no BAT */
754 for (i = 0; i < 16; i++) {
755 battable[i].batu = 0;
756 battable[i].batl = 0;
759 /* Get physical memory regions from firmware */
760 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
761 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
763 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp);
764 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
765 panic("moea64_bootstrap: phys_avail too small");
766 qsort(regions, regions_sz, sizeof(*regions), mr_cmp);
767 phys_avail_count = 0;
770 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
771 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
772 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
773 regions[i].mr_start + regions[i].mr_size,
776 (physsz + regions[i].mr_size) >= hwphyssz) {
777 if (physsz < hwphyssz) {
778 phys_avail[j] = regions[i].mr_start;
779 phys_avail[j + 1] = regions[i].mr_start +
786 phys_avail[j] = regions[i].mr_start;
787 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
789 physsz += regions[i].mr_size;
791 physmem = btoc(physsz);
794 * Allocate PTEG table.
797 moea64_pteg_count = PTEGCOUNT;
799 moea64_pteg_count = 0x1000;
801 while (moea64_pteg_count < physmem)
802 moea64_pteg_count <<= 1;
803 #endif /* PTEGCOUNT */
805 size = moea64_pteg_count * sizeof(struct lpteg);
806 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes",
807 moea64_pteg_count, size);
810 * We now need to allocate memory. This memory, to be allocated,
811 * has to reside in a page table. The page table we are about to
812 * allocate. We don't have BAT. So drop to data real mode for a minute
813 * as a measure of last resort. We do this a couple times.
816 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size);
818 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg));
821 moea64_pteg_mask = moea64_pteg_count - 1;
823 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table);
826 * Allocate pv/overflow lists.
828 size = sizeof(struct pvo_head) * moea64_pteg_count;
830 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
832 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
835 for (i = 0; i < moea64_pteg_count; i++)
836 LIST_INIT(&moea64_pvo_table[i]);
840 * Initialize the lock that synchronizes access to the pteg and pvo
843 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF |
845 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
848 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU.
850 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN);
853 * Initialise the unmanaged pvo pool.
855 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
856 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
857 moea64_bpvo_pool_index = 0;
860 * Make sure kernel vsid is allocated as well as VSID 0.
862 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
863 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
864 moea64_vsid_bitmap[0] |= 1;
867 * Initialize the kernel pmap (which is statically allocated).
869 for (i = 0; i < 16; i++)
870 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
872 kernel_pmap->pmap_phys = kernel_pmap;
873 kernel_pmap->pm_active = ~0;
875 PMAP_LOCK_INIT(kernel_pmap);
878 * Now map in all the other buffers we allocated earlier
882 size = moea64_pteg_count * sizeof(struct lpteg);
883 off = (vm_offset_t)(moea64_pteg_table);
884 for (pa = off; pa < off + size; pa += PAGE_SIZE)
885 moea64_kenter(mmup, pa, pa);
886 size = sizeof(struct pvo_head) * moea64_pteg_count;
887 off = (vm_offset_t)(moea64_pvo_table);
888 for (pa = off; pa < off + size; pa += PAGE_SIZE)
889 moea64_kenter(mmup, pa, pa);
890 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
891 off = (vm_offset_t)(moea64_bpvo_pool);
892 for (pa = off; pa < off + size; pa += PAGE_SIZE)
893 moea64_kenter(mmup, pa, pa);
896 * Map certain important things, like ourselves.
898 * NOTE: We do not map the exception vector space. That code is
899 * used only in real mode, and leaving it unmapped allows us to
900 * catch NULL pointer deferences, instead of making NULL a valid
904 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE)
905 moea64_kenter(mmup, pa, pa);
908 if (!ofw_real_mode) {
910 * Set up the Open Firmware pmap and add its mappings.
913 moea64_pinit(mmup, &ofw_pmap);
914 for (i = 0; i < 16; i++)
915 ofw_pmap.pm_sr[i] = kernel_pmap->pm_sr[i];
917 if ((chosen = OF_finddevice("/chosen")) == -1)
918 panic("moea64_bootstrap: can't find /chosen");
919 OF_getprop(chosen, "mmu", &mmui, 4);
920 if ((mmu = OF_instance_to_package(mmui)) == -1)
921 panic("moea64_bootstrap: can't get mmu package");
922 if ((sz = OF_getproplen(mmu, "translations")) == -1)
923 panic("moea64_bootstrap: can't get ofw translation count");
924 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
925 panic("moea64_bootstrap: too many ofw translations");
927 moea64_add_ofw_mappings(mmup, mmu, sz);
935 * Calculate the last available physical address.
937 for (i = 0; phys_avail[i + 2] != 0; i += 2)
939 Maxmem = powerpc_btop(phys_avail[i + 1]);
942 * Initialize MMU and remap early physical mappings
944 moea64_bridge_cpu_bootstrap(mmup,0);
945 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync();
947 bs_remap_earlyboot();
950 * Set the start and end of kva.
952 virtual_avail = VM_MIN_KERNEL_ADDRESS;
953 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
956 * Figure out how far we can extend virtual_end into segment 16
957 * without running into existing mappings. Segment 16 is guaranteed
958 * to contain neither RAM nor devices (at least on Apple hardware),
959 * but will generally contain some OFW mappings we should not
963 PMAP_LOCK(kernel_pmap);
964 while (moea64_pvo_find_va(kernel_pmap, virtual_end+1, NULL) == NULL)
965 virtual_end += PAGE_SIZE;
966 PMAP_UNLOCK(kernel_pmap);
969 * Allocate some things for page zeroing. We put this directly
970 * in the page table, marked with LPTE_LOCKED, to avoid any
971 * of the PVO book-keeping or other parts of the VM system
972 * from even knowing that this hack exists.
975 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF);
976 for (i = 0; i < 2; i++) {
981 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
982 virtual_end -= PAGE_SIZE;
986 vsid = va_to_vsid(kernel_pmap, moea64_scratchpage_va[i]);
987 moea64_pte_create(&pt, vsid, moea64_scratchpage_va[i],
989 pt.pte_hi |= LPTE_LOCKED;
991 ptegidx = va_to_pteg(vsid, moea64_scratchpage_va[i]);
992 pteidx = moea64_pte_insert(ptegidx, &pt);
993 if (pt.pte_hi & LPTE_HID)
994 ptegidx ^= moea64_pteg_mask;
996 moea64_scratchpage_pte[i] =
997 &moea64_pteg_table[ptegidx].pt[pteidx];
1003 * Allocate a kernel stack with a guard page for thread0 and map it
1004 * into the kernel page map.
1006 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
1007 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1008 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
1009 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
1010 thread0.td_kstack = va;
1011 thread0.td_kstack_pages = KSTACK_PAGES;
1012 for (i = 0; i < KSTACK_PAGES; i++) {
1013 moea64_kenter(mmup, va, pa);
1019 * Allocate virtual address space for the message buffer.
1021 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE);
1022 msgbufp = (struct msgbuf *)virtual_avail;
1024 virtual_avail += round_page(MSGBUF_SIZE);
1025 while (va < virtual_avail) {
1026 moea64_kenter(mmup, va, pa);
1032 * Allocate virtual address space for the dynamic percpu area.
1034 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
1035 dpcpu = (void *)virtual_avail;
1036 virtual_avail += DPCPU_SIZE;
1037 while (va < virtual_avail) {
1038 moea64_kenter(mmup, va, pa);
1042 dpcpu_init(dpcpu, 0);
1046 * Activate a user pmap. The pmap must be activated before it's address
1047 * space can be accessed in any way.
1050 moea64_activate(mmu_t mmu, struct thread *td)
1055 * Load all the data we need up front to encourage the compiler to
1056 * not issue any loads while we have interrupts disabled below.
1058 pm = &td->td_proc->p_vmspace->vm_pmap;
1059 pmr = pm->pmap_phys;
1061 pm->pm_active |= PCPU_GET(cpumask);
1062 PCPU_SET(curpmap, pmr);
1066 moea64_deactivate(mmu_t mmu, struct thread *td)
1070 pm = &td->td_proc->p_vmspace->vm_pmap;
1071 pm->pm_active &= ~(PCPU_GET(cpumask));
1072 PCPU_SET(curpmap, NULL);
1076 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1078 struct pvo_entry *pvo;
1081 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1085 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1086 pm->pm_stats.wired_count++;
1087 pvo->pvo_vaddr |= PVO_WIRED;
1089 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1090 pm->pm_stats.wired_count--;
1091 pvo->pvo_vaddr &= ~PVO_WIRED;
1098 * This goes through and sets the physical address of our
1099 * special scratch PTE to the PA we want to zero or copy. Because
1100 * of locking issues (this can get called in pvo_enter() by
1101 * the UMA allocator), we can't use most other utility functions here
1105 void moea64_set_scratchpage_pa(int which, vm_offset_t pa) {
1107 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1109 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID;
1110 TLBIE(kernel_pmap, moea64_scratchpage_va[which]);
1112 moea64_scratchpage_pte[which]->pte_lo &=
1113 ~(LPTE_WIMG | LPTE_RPGN);
1114 moea64_scratchpage_pte[which]->pte_lo |=
1115 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1118 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID;
1123 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1128 dst = VM_PAGE_TO_PHYS(mdst);
1129 src = VM_PAGE_TO_PHYS(msrc);
1131 mtx_lock(&moea64_scratchpage_mtx);
1133 moea64_set_scratchpage_pa(0,src);
1134 moea64_set_scratchpage_pa(1,dst);
1136 kcopy((void *)moea64_scratchpage_va[0],
1137 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1139 mtx_unlock(&moea64_scratchpage_mtx);
1143 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1145 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1147 if (!moea64_initialized)
1148 panic("moea64_zero_page: can't zero pa %#x", pa);
1149 if (size + off > PAGE_SIZE)
1150 panic("moea64_zero_page: size + off > PAGE_SIZE");
1152 mtx_lock(&moea64_scratchpage_mtx);
1154 moea64_set_scratchpage_pa(0,pa);
1155 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1156 mtx_unlock(&moea64_scratchpage_mtx);
1160 * Zero a page of physical memory by temporarily mapping it
1163 moea64_zero_page(mmu_t mmu, vm_page_t m)
1165 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1168 if (!moea64_initialized)
1169 panic("moea64_zero_page: can't zero pa %#x", pa);
1171 mtx_lock(&moea64_scratchpage_mtx);
1173 moea64_set_scratchpage_pa(0,pa);
1174 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1175 __asm __volatile("dcbz 0,%0" ::
1176 "r"(moea64_scratchpage_va[0] + off));
1177 mtx_unlock(&moea64_scratchpage_mtx);
1181 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1184 moea64_zero_page(mmu, m);
1188 * Map the given physical page at the specified virtual address in the
1189 * target pmap with the protection requested. If specified the page
1190 * will be wired down.
1193 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1194 vm_prot_t prot, boolean_t wired)
1197 vm_page_lock_queues();
1199 moea64_enter_locked(pmap, va, m, prot, wired);
1200 vm_page_unlock_queues();
1205 * Map the given physical page at the specified virtual address in the
1206 * target pmap with the protection requested. If specified the page
1207 * will be wired down.
1209 * The page queues and pmap must be locked.
1213 moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1216 struct pvo_head *pvo_head;
1223 if (!moea64_initialized) {
1224 pvo_head = &moea64_pvo_kunmanaged;
1226 zone = moea64_upvo_zone;
1229 pvo_head = vm_page_to_pvoh(m);
1231 zone = moea64_mpvo_zone;
1232 pvo_flags = PVO_MANAGED;
1235 if (pmap_bootstrapped)
1236 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1237 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1239 /* XXX change the pvo head for fake pages */
1240 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) {
1241 pvo_flags &= ~PVO_MANAGED;
1242 pvo_head = &moea64_pvo_kunmanaged;
1243 zone = moea64_upvo_zone;
1246 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1248 if (prot & VM_PROT_WRITE) {
1250 if (pmap_bootstrapped)
1251 vm_page_flag_set(m, PG_WRITEABLE);
1255 if (prot & VM_PROT_EXECUTE)
1256 pvo_flags |= VM_PROT_EXECUTE;
1259 pvo_flags |= PVO_WIRED;
1261 if ((m->flags & PG_FICTITIOUS) != 0)
1262 pvo_flags |= PVO_FAKE;
1264 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1268 * Flush the page from the instruction cache if this page is
1269 * mapped executable and cacheable.
1271 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1272 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1277 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz)
1281 * This is much trickier than on older systems because
1282 * we can't sync the icache on physical addresses directly
1283 * without a direct map. Instead we check a couple of cases
1284 * where the memory is already mapped in and, failing that,
1285 * use the same trick we use for page zeroing to create
1286 * a temporary mapping for this physical address.
1289 if (!pmap_bootstrapped) {
1291 * If PMAP is not bootstrapped, we are likely to be
1294 __syncicache((void *)pa, sz);
1295 } else if (pmap == kernel_pmap) {
1296 __syncicache((void *)va, sz);
1298 /* Use the scratch page to set up a temp mapping */
1300 mtx_lock(&moea64_scratchpage_mtx);
1302 moea64_set_scratchpage_pa(1,pa);
1303 __syncicache((void *)moea64_scratchpage_va[1], sz);
1305 mtx_unlock(&moea64_scratchpage_mtx);
1310 * Maps a sequence of resident pages belonging to the same object.
1311 * The sequence begins with the given page m_start. This page is
1312 * mapped at the given virtual address start. Each subsequent page is
1313 * mapped at a virtual address that is offset from start by the same
1314 * amount as the page is offset from m_start within the object. The
1315 * last page in the sequence is the page with the largest offset from
1316 * m_start that can be mapped at a virtual address less than the given
1317 * virtual address end. Not every virtual page between start and end
1318 * is mapped; only those for which a resident page exists with the
1319 * corresponding offset from m_start are mapped.
1322 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1323 vm_page_t m_start, vm_prot_t prot)
1326 vm_pindex_t diff, psize;
1328 psize = atop(end - start);
1331 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1332 moea64_enter_locked(pm, start + ptoa(diff), m, prot &
1333 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1334 m = TAILQ_NEXT(m, listq);
1340 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1344 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1351 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1353 struct pvo_entry *pvo;
1357 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1361 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF);
1367 * Atomically extract and hold the physical page with the given
1368 * pmap and virtual address pair if that mapping permits the given
1372 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1374 struct pvo_entry *pvo;
1378 vm_page_lock_queues();
1380 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1381 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1382 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1383 (prot & VM_PROT_WRITE) == 0)) {
1384 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1387 vm_page_unlock_queues();
1393 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1396 * This entire routine is a horrible hack to avoid bothering kmem
1397 * for new KVA addresses. Because this can get called from inside
1398 * kmem allocation routines, calling kmem for a new address here
1399 * can lead to multiply locking non-recursive mutexes.
1401 static vm_pindex_t color;
1405 int pflags, needed_lock;
1407 *flags = UMA_SLAB_PRIV;
1408 needed_lock = !PMAP_LOCKED(kernel_pmap);
1411 PMAP_LOCK(kernel_pmap);
1413 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT)
1414 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED;
1416 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED;
1418 pflags |= VM_ALLOC_ZERO;
1421 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ);
1423 if (wait & M_NOWAIT)
1430 va = VM_PAGE_TO_PHYS(m);
1432 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone,
1433 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M,
1434 PVO_WIRED | PVO_BOOTSTRAP);
1437 PMAP_UNLOCK(kernel_pmap);
1439 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1440 bzero((void *)va, PAGE_SIZE);
1446 moea64_init(mmu_t mmu)
1449 CTR0(KTR_PMAP, "moea64_init");
1451 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1452 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1453 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1454 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1455 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1456 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1458 if (!hw_direct_map) {
1459 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1460 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1463 moea64_initialized = TRUE;
1467 moea64_is_modified(mmu_t mmu, vm_page_t m)
1470 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1473 return (moea64_query_bit(m, LPTE_CHG));
1477 moea64_clear_reference(mmu_t mmu, vm_page_t m)
1480 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1482 moea64_clear_bit(m, LPTE_REF, NULL);
1486 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1489 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1491 moea64_clear_bit(m, LPTE_CHG, NULL);
1495 * Clear the write and modified bits in each of the given page's mappings.
1498 moea64_remove_write(mmu_t mmu, vm_page_t m)
1500 struct pvo_entry *pvo;
1505 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1506 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1507 (m->flags & PG_WRITEABLE) == 0)
1509 lo = moea64_attr_fetch(m);
1511 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1512 pmap = pvo->pvo_pmap;
1515 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1516 pt = moea64_pvo_to_pte(pvo, -1);
1517 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1518 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1520 moea64_pte_synch(pt, &pvo->pvo_pte.lpte);
1521 lo |= pvo->pvo_pte.lpte.pte_lo;
1522 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1523 moea64_pte_change(pt, &pvo->pvo_pte.lpte,
1524 pvo->pvo_pmap, PVO_VADDR(pvo));
1530 if ((lo & LPTE_CHG) != 0) {
1531 moea64_attr_clear(m, LPTE_CHG);
1534 vm_page_flag_clear(m, PG_WRITEABLE);
1538 * moea64_ts_referenced:
1540 * Return a count of reference bits for a page, clearing those bits.
1541 * It is not necessary for every reference bit to be cleared, but it
1542 * is necessary that 0 only be returned when there are truly no
1543 * reference bits set.
1545 * XXX: The exact number of bits to check and clear is a matter that
1546 * should be tested and standardized at some point in the future for
1547 * optimal aging of shared pages.
1550 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1554 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1557 count = moea64_clear_bit(m, LPTE_REF, NULL);
1563 * Modify the WIMG settings of all mappings for a page.
1566 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1568 struct pvo_entry *pvo;
1569 struct pvo_head *pvo_head;
1574 if (m->flags & PG_FICTITIOUS) {
1575 m->md.mdpg_cache_attrs = ma;
1579 vm_page_lock_queues();
1580 pvo_head = vm_page_to_pvoh(m);
1581 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1582 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1583 pmap = pvo->pvo_pmap;
1586 pt = moea64_pvo_to_pte(pvo, -1);
1587 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1588 pvo->pvo_pte.lpte.pte_lo |= lo;
1590 moea64_pte_change(pt, &pvo->pvo_pte.lpte,
1591 pvo->pvo_pmap, PVO_VADDR(pvo));
1592 if (pvo->pvo_pmap == kernel_pmap)
1598 m->md.mdpg_cache_attrs = ma;
1599 vm_page_unlock_queues();
1603 * Map a wired page into kernel virtual address space.
1606 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1611 pte_lo = moea64_calc_wimg(pa, ma);
1613 PMAP_LOCK(kernel_pmap);
1614 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone,
1615 &moea64_pvo_kunmanaged, va, pa, pte_lo,
1616 PVO_WIRED | VM_PROT_EXECUTE);
1618 if (error != 0 && error != ENOENT)
1619 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va,
1623 * Flush the memory from the instruction cache.
1625 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) {
1626 __syncicache((void *)va, PAGE_SIZE);
1628 PMAP_UNLOCK(kernel_pmap);
1632 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1635 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1639 * Extract the physical page address associated with the given kernel virtual
1643 moea64_kextract(mmu_t mmu, vm_offset_t va)
1645 struct pvo_entry *pvo;
1649 * Shortcut the direct-mapped case when applicable. We never put
1650 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1652 if (va < VM_MIN_KERNEL_ADDRESS)
1655 PMAP_LOCK(kernel_pmap);
1656 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1657 KASSERT(pvo != NULL, ("moea64_kextract: no addr found"));
1658 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF);
1659 PMAP_UNLOCK(kernel_pmap);
1664 * Remove a wired page from kernel virtual address space.
1667 moea64_kremove(mmu_t mmu, vm_offset_t va)
1669 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1673 * Map a range of physical addresses into kernel virtual address space.
1675 * The value passed in *virt is a suggested virtual address for the mapping.
1676 * Architectures which can support a direct-mapped physical to virtual region
1677 * can return the appropriate address within that region, leaving '*virt'
1678 * unchanged. We cannot and therefore do not; *virt is updated with the
1679 * first usable address after the mapped region.
1682 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1683 vm_offset_t pa_end, int prot)
1685 vm_offset_t sva, va;
1689 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1690 moea64_kenter(mmu, va, pa_start);
1697 * Returns true if the pmap's pv is one of the first
1698 * 16 pvs linked to from this page. This count may
1699 * be changed upwards or downwards in the future; it
1700 * is only necessary that true be returned for a small
1701 * subset of pmaps for proper page aging.
1704 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1707 struct pvo_entry *pvo;
1709 if (!moea64_initialized || (m->flags & PG_FICTITIOUS))
1712 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1715 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1716 if (pvo->pvo_pmap == pmap)
1726 * Return the number of managed mappings to the given physical page
1730 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1732 struct pvo_entry *pvo;
1736 if (!moea64_initialized || (m->flags & PG_FICTITIOUS) != 0)
1738 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1739 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1740 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1745 static u_int moea64_vsidcontext;
1748 moea64_pinit(mmu_t mmu, pmap_t pmap)
1753 PMAP_LOCK_INIT(pmap);
1756 __asm __volatile("mftb %0" : "=r"(entropy));
1758 if (pmap_bootstrapped)
1759 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap);
1761 pmap->pmap_phys = pmap;
1764 * Allocate some segment registers for this pmap.
1766 mtx_lock(&moea64_slb_mutex);
1767 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1771 * Create a new value by mutiplying by a prime and adding in
1772 * entropy from the timebase register. This is to make the
1773 * VSID more random so that the PT hash function collides
1774 * less often. (Note that the prime casues gcc to do shifts
1775 * instead of a multiply.)
1777 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1778 hash = moea64_vsidcontext & (NPMAPS - 1);
1779 if (hash == 0) /* 0 is special, avoid it */
1782 mask = 1 << (hash & (VSID_NBPW - 1));
1783 hash = (moea64_vsidcontext & 0xfffff);
1784 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
1785 /* anything free in this bucket? */
1786 if (moea64_vsid_bitmap[n] == 0xffffffff) {
1787 entropy = (moea64_vsidcontext >> 20);
1790 i = ffs(~moea64_vsid_bitmap[n]) - 1;
1792 hash &= 0xfffff & ~(VSID_NBPW - 1);
1795 KASSERT(!(moea64_vsid_bitmap[n] & mask),
1796 ("Allocating in-use VSID %#zx\n", hash));
1797 moea64_vsid_bitmap[n] |= mask;
1798 mtx_unlock(&moea64_slb_mutex);
1800 for (i = 0; i < 16; i++) {
1801 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1806 mtx_unlock(&moea64_slb_mutex);
1807 panic("%s: out of segments",__func__);
1811 * Initialize the pmap associated with process 0.
1814 moea64_pinit0(mmu_t mmu, pmap_t pm)
1816 moea64_pinit(mmu, pm);
1817 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1821 * Set the physical protection on the specified range of this map as requested.
1824 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1827 struct pvo_entry *pvo;
1831 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva,
1835 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1836 ("moea64_protect: non current pmap"));
1838 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1839 moea64_remove(mmu, pm, sva, eva);
1843 vm_page_lock_queues();
1845 for (; sva < eva; sva += PAGE_SIZE) {
1846 pvo = moea64_pvo_find_va(pm, sva, &pteidx);
1851 * Grab the PTE pointer before we diddle with the cached PTE
1855 pt = moea64_pvo_to_pte(pvo, pteidx);
1858 * Change the protection of the page.
1860 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1861 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1862 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
1863 if ((prot & VM_PROT_EXECUTE) == 0)
1864 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
1867 * If the PVO is in the page table, update that pte as well.
1870 moea64_pte_change(pt, &pvo->pvo_pte.lpte,
1871 pvo->pvo_pmap, PVO_VADDR(pvo));
1872 if ((pvo->pvo_pte.lpte.pte_lo &
1873 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1874 moea64_syncicache(pm, sva,
1875 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN,
1881 vm_page_unlock_queues();
1886 * Map a list of wired pages into kernel virtual address space. This is
1887 * intended for temporary mappings which do not need page modification or
1888 * references recorded. Existing mappings in the region are overwritten.
1891 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
1893 while (count-- > 0) {
1894 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1901 * Remove page mappings from kernel virtual address space. Intended for
1902 * temporary mappings entered by moea64_qenter.
1905 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
1907 while (count-- > 0) {
1908 moea64_kremove(mmu, va);
1914 moea64_release(mmu_t mmu, pmap_t pmap)
1919 * Free segment register's VSID
1921 if (pmap->pm_sr[0] == 0)
1922 panic("moea64_release: pm_sr[0] = 0");
1924 mtx_lock(&moea64_slb_mutex);
1925 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1926 mask = 1 << (idx % VSID_NBPW);
1928 moea64_vsid_bitmap[idx] &= ~mask;
1929 mtx_unlock(&moea64_slb_mutex);
1930 PMAP_LOCK_DESTROY(pmap);
1934 * Remove the given range of addresses from the specified map.
1937 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1939 struct pvo_entry *pvo;
1942 vm_page_lock_queues();
1944 for (; sva < eva; sva += PAGE_SIZE) {
1945 pvo = moea64_pvo_find_va(pm, sva, &pteidx);
1947 moea64_pvo_remove(pvo, pteidx);
1950 vm_page_unlock_queues();
1955 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
1956 * will reflect changes in pte's back to the vm_page.
1959 moea64_remove_all(mmu_t mmu, vm_page_t m)
1961 struct pvo_head *pvo_head;
1962 struct pvo_entry *pvo, *next_pvo;
1965 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1967 pvo_head = vm_page_to_pvoh(m);
1968 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1969 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1971 MOEA_PVO_CHECK(pvo); /* sanity check */
1972 pmap = pvo->pvo_pmap;
1974 moea64_pvo_remove(pvo, -1);
1977 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) {
1978 moea64_attr_clear(m, LPTE_CHG);
1981 vm_page_flag_clear(m, PG_WRITEABLE);
1985 * Allocate a physical page of memory directly from the phys_avail map.
1986 * Can only be called from moea64_bootstrap before avail start and end are
1990 moea64_bootstrap_alloc(vm_size_t size, u_int align)
1995 size = round_page(size);
1996 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1998 s = (phys_avail[i] + align - 1) & ~(align - 1);
2003 if (s < phys_avail[i] || e > phys_avail[i + 1])
2006 if (s == phys_avail[i]) {
2007 phys_avail[i] += size;
2008 } else if (e == phys_avail[i + 1]) {
2009 phys_avail[i + 1] -= size;
2011 for (j = phys_avail_count * 2; j > i; j -= 2) {
2012 phys_avail[j] = phys_avail[j - 2];
2013 phys_avail[j + 1] = phys_avail[j - 1];
2016 phys_avail[i + 3] = phys_avail[i + 1];
2017 phys_avail[i + 1] = s;
2018 phys_avail[i + 2] = e;
2024 panic("moea64_bootstrap_alloc: could not allocate memory");
2031 register_t msr, scratch;
2033 for (i = 0; i < 0xFF000; i += 0x00001000) {
2047 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1));
2052 moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
2053 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags)
2055 struct pvo_entry *pvo;
2063 * One nasty thing that can happen here is that the UMA calls to
2064 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2065 * which calls UMA...
2067 * We break the loop by detecting recursion and allocating out of
2068 * the bootstrap pool.
2072 bootstrap = (flags & PVO_BOOTSTRAP);
2074 if (!moea64_initialized)
2078 * Compute the PTE Group index.
2081 vsid = va_to_vsid(pm, va);
2082 ptegidx = va_to_pteg(vsid, va);
2085 * Remove any existing mapping for this page. Reuse the pvo entry if
2086 * there is a mapping.
2090 moea64_pvo_enter_calls++;
2092 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2093 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2094 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2095 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) ==
2096 (pte_lo & LPTE_PP)) {
2100 moea64_pvo_remove(pvo, -1);
2106 * If we aren't overwriting a mapping, try to allocate.
2109 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2110 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d",
2111 moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2112 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2114 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2115 moea64_bpvo_pool_index++;
2119 * Note: drop the table lock around the UMA allocation in
2120 * case the UMA allocator needs to manipulate the page
2121 * table. The mapping we are working with is already
2122 * protected by the PMAP lock.
2125 pvo = uma_zalloc(zone, M_NOWAIT);
2134 moea64_pvo_entries++;
2135 pvo->pvo_vaddr = va;
2137 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2138 pvo->pvo_vaddr &= ~ADDR_POFF;
2140 if (!(flags & VM_PROT_EXECUTE))
2141 pte_lo |= LPTE_NOEXEC;
2142 if (flags & PVO_WIRED)
2143 pvo->pvo_vaddr |= PVO_WIRED;
2144 if (pvo_head != &moea64_pvo_kunmanaged)
2145 pvo->pvo_vaddr |= PVO_MANAGED;
2147 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2148 if (flags & PVO_FAKE)
2149 pvo->pvo_vaddr |= PVO_FAKE;
2151 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2152 (uint64_t)(pa) | pte_lo);
2155 * Remember if the list was empty and therefore will be the first
2158 if (LIST_FIRST(pvo_head) == NULL)
2160 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2162 if (pvo->pvo_vaddr & PVO_WIRED)
2163 pm->pm_stats.wired_count++;
2164 pm->pm_stats.resident_count++;
2167 * We hope this succeeds but it isn't required.
2169 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte);
2171 PVO_PTEGIDX_SET(pvo, i);
2173 panic("moea64_pvo_enter: overflow");
2174 moea64_pte_overflow++;
2177 if (pm == kernel_pmap)
2182 return (first ? ENOENT : 0);
2186 moea64_pvo_remove(struct pvo_entry *pvo, int pteidx)
2191 * If there is an active pte entry, we need to deactivate it (and
2192 * save the ref & cfg bits).
2195 pt = moea64_pvo_to_pte(pvo, pteidx);
2197 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap,
2199 PVO_PTEGIDX_CLR(pvo);
2201 moea64_pte_overflow--;
2205 * Update our statistics.
2207 pvo->pvo_pmap->pm_stats.resident_count--;
2208 if (pvo->pvo_vaddr & PVO_WIRED)
2209 pvo->pvo_pmap->pm_stats.wired_count--;
2212 * Save the REF/CHG bits into their cache if the page is managed.
2214 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) {
2217 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2219 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo &
2220 (LPTE_REF | LPTE_CHG));
2225 * Remove this PVO from the PV list.
2227 LIST_REMOVE(pvo, pvo_vlink);
2230 * Remove this from the overflow list and return it to the pool
2231 * if we aren't going to reuse it.
2233 LIST_REMOVE(pvo, pvo_olink);
2235 moea64_pvo_entries--;
2236 moea64_pvo_remove_calls++;
2240 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2241 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2242 moea64_upvo_zone, pvo);
2246 moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2250 * We can find the actual pte entry without searching by grabbing
2251 * the PTEG index from 3 unused bits in pvo_vaddr and by
2252 * noticing the HID bit.
2254 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID)
2255 ptegidx ^= moea64_pteg_mask;
2257 return ((ptegidx << 3) | PVO_PTEGIDX_GET(pvo));
2260 static struct pvo_entry *
2261 moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2263 struct pvo_entry *pvo;
2268 vsid = va_to_vsid(pm, va);
2269 ptegidx = va_to_pteg(vsid, va);
2272 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2273 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2275 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx);
2284 static struct lpte *
2285 moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2290 * If we haven't been supplied the ptegidx, calculate it.
2296 vsid = va_to_vsid(pvo->pvo_pmap, PVO_VADDR(pvo));
2297 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo));
2298 pteidx = moea64_pvo_pte_index(pvo, ptegidx);
2301 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7];
2303 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
2304 !PVO_PTEGIDX_ISSET(pvo)) {
2305 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no "
2306 "valid pte index", pvo);
2309 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 &&
2310 PVO_PTEGIDX_ISSET(pvo)) {
2311 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo "
2312 "pvo but no valid pte", pvo);
2315 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) ==
2317 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) {
2318 panic("moea64_pvo_to_pte: pvo %p has valid pte in "
2319 "moea64_pteg_table %p but invalid in pvo", pvo, pt);
2322 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) &
2323 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) {
2324 panic("moea64_pvo_to_pte: pvo %p pte does not match "
2325 "pte %p in moea64_pteg_table difference is %#x",
2327 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo));
2330 ASSERT_TABLE_LOCK();
2334 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) {
2335 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in "
2336 "moea64_pteg_table but valid in pvo", pvo, pt);
2343 moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt)
2348 ASSERT_TABLE_LOCK();
2351 * First try primary hash.
2353 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2354 if ((pt->pte_hi & LPTE_VALID) == 0 &&
2355 (pt->pte_hi & LPTE_LOCKED) == 0) {
2356 pvo_pt->pte_hi &= ~LPTE_HID;
2357 moea64_pte_set(pt, pvo_pt);
2363 * Now try secondary hash.
2365 ptegidx ^= moea64_pteg_mask;
2367 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2368 if ((pt->pte_hi & LPTE_VALID) == 0 &&
2369 (pt->pte_hi & LPTE_LOCKED) == 0) {
2370 pvo_pt->pte_hi |= LPTE_HID;
2371 moea64_pte_set(pt, pvo_pt);
2376 panic("moea64_pte_insert: overflow");
2381 moea64_query_bit(vm_page_t m, u_int64_t ptebit)
2383 struct pvo_entry *pvo;
2386 if (moea64_attr_fetch(m) & ptebit)
2389 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2391 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2392 MOEA_PVO_CHECK(pvo); /* sanity check */
2395 * See if we saved the bit off. If so, cache it and return
2398 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2399 moea64_attr_save(m, ptebit);
2400 MOEA_PVO_CHECK(pvo); /* sanity check */
2406 * No luck, now go through the hard part of looking at the PTEs
2407 * themselves. Sync so that any pending REF/CHG bits are flushed to
2411 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2412 MOEA_PVO_CHECK(pvo); /* sanity check */
2415 * See if this pvo has a valid PTE. if so, fetch the
2416 * REF/CHG bits from the valid PTE. If the appropriate
2417 * ptebit is set, cache it and return success.
2420 pt = moea64_pvo_to_pte(pvo, -1);
2422 moea64_pte_synch(pt, &pvo->pvo_pte.lpte);
2423 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2426 moea64_attr_save(m, ptebit);
2427 MOEA_PVO_CHECK(pvo); /* sanity check */
2438 moea64_clear_bit(vm_page_t m, u_int64_t ptebit, u_int64_t *origbit)
2441 struct pvo_entry *pvo;
2445 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2448 * Clear the cached value.
2450 rv = moea64_attr_fetch(m);
2451 moea64_attr_clear(m, ptebit);
2454 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2455 * we can reset the right ones). note that since the pvo entries and
2456 * list heads are accessed via BAT0 and are never placed in the page
2457 * table, we don't have to worry about further accesses setting the
2463 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2464 * valid pte clear the ptebit from the valid pte.
2467 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2468 MOEA_PVO_CHECK(pvo); /* sanity check */
2471 pt = moea64_pvo_to_pte(pvo, -1);
2473 moea64_pte_synch(pt, &pvo->pvo_pte.lpte);
2474 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2476 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit);
2479 rv |= pvo->pvo_pte.lpte.pte_lo;
2480 pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2481 MOEA_PVO_CHECK(pvo); /* sanity check */
2485 if (origbit != NULL) {
2493 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2495 struct pvo_entry *pvo;
2499 PMAP_LOCK(kernel_pmap);
2500 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) {
2501 pvo = moea64_pvo_find_va(kernel_pmap, ppa, NULL);
2503 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2508 PMAP_UNLOCK(kernel_pmap);
2514 * Map a set of physical memory pages into the kernel virtual
2515 * address space. Return a pointer to where it is mapped. This
2516 * routine is intended to be used for mapping device memory,
2520 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2522 vm_offset_t va, tmpva, ppa, offset;
2524 ppa = trunc_page(pa);
2525 offset = pa & PAGE_MASK;
2526 size = roundup(offset + size, PAGE_SIZE);
2528 va = kmem_alloc_nofault(kernel_map, size);
2531 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2533 for (tmpva = va; size > 0;) {
2534 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2540 return ((void *)(va + offset));
2544 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2547 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2551 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2553 vm_offset_t base, offset;
2555 base = trunc_page(va);
2556 offset = va & PAGE_MASK;
2557 size = roundup(offset + size, PAGE_SIZE);
2559 kmem_free(kernel_map, base, size);
2563 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2565 struct pvo_entry *pvo;
2572 lim = round_page(va);
2573 len = MIN(lim - va, sz);
2574 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2576 pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) |
2578 moea64_syncicache(pm, va, pa, len);