sys/gnu/dts/arm/imx6qdl-gw5904.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49
  50 / {
  51         /* these are used by bootloader for disabling nodes */
  52         aliases {
  53                 led0 = &led0;
  54                 led1 = &led1;
  55                 led2 = &led2;
  56                 usb0 = &usbh1;
  57                 usb1 = &usbotg;
  58         };
  59
  60         chosen {
  61                 stdout-path = &uart2;
  62         };
  63
  64         backlight {
  65                 compatible = "pwm-backlight";
  66                 pwms = <&pwm4 0 5000000>;
  67                 brightness-levels = <0 4 8 16 32 64 128 255>;
  68                 default-brightness-level = <7>;
  69         };
  70
  71         leds {
  72                 compatible = "gpio-leds";
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_gpio_leds>;
  75
  76                 led0: user1 {
  77                         label = "user1";
  78                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  79                         default-state = "on";
  80                         linux,default-trigger = "heartbeat";
  81                 };
  82
  83                 led1: user2 {
  84                         label = "user2";
  85                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  86                         default-state = "off";
  87                 };
  88
  89                 led2: user3 {
  90                         label = "user3";
  91                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  92                         default-state = "off";
  93                 };
  94         };
  95
  96         memory@10000000 {
  97                 device_type = "memory";
  98                 reg = <0x10000000 0x40000000>;
  99         };
 100
 101         pps {
 102                 compatible = "pps-gpio";
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&pinctrl_pps>;
 105                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 106         };
 107
 108         reg_1p0v: regulator-1p0v {
 109                 compatible = "regulator-fixed";
 110                 regulator-name = "1P0V";
 111                 regulator-min-microvolt = <1000000>;
 112                 regulator-max-microvolt = <1000000>;
 113                 regulator-always-on;
 114         };
 115
 116         reg_3p3v: regulator-3p3v {
 117                 compatible = "regulator-fixed";
 118                 regulator-name = "3P3V";
 119                 regulator-min-microvolt = <3300000>;
 120                 regulator-max-microvolt = <3300000>;
 121                 regulator-always-on;
 122         };
 123
 124         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 125                 compatible = "regulator-fixed";
 126                 regulator-name = "usb_h1_vbus";
 127                 regulator-min-microvolt = <5000000>;
 128                 regulator-max-microvolt = <5000000>;
 129                 regulator-always-on;
 130         };
 131
 132         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 133                 compatible = "regulator-fixed";
 134                 regulator-name = "usb_otg_vbus";
 135                 regulator-min-microvolt = <5000000>;
 136                 regulator-max-microvolt = <5000000>;
 137                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 138                 enable-active-high;
 139         };
 140 };
 141
 142 &clks {
 143         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 144                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 145         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 146                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 147 };
 148
 149 &fec {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_enet>;
 152         phy-mode = "rgmii-id";
 153         status = "okay";
 154
 155         fixed-link {
 156                 speed = <1000>;
 157                 full-duplex;
 158         };
 159
 160         mdio {
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163
 164                 switch@0 {
 165                         compatible = "marvell,mv88e6085";
 166                         reg = <0>;
 167
 168                         ports {
 169                                 #address-cells = <1>;
 170                                 #size-cells = <0>;
 171
 172                                 port@0 {
 173                                         reg = <0>;
 174                                         label = "lan4";
 175                                 };
 176
 177                                 port@1 {
 178                                         reg = <1>;
 179                                         label = "lan3";
 180                                 };
 181
 182                                 port@2 {
 183                                         reg = <2>;
 184                                         label = "lan2";
 185                                 };
 186
 187                                 port@3 {
 188                                         reg = <3>;
 189                                         label = "lan1";
 190                                 };
 191
 192                                 port@5 {
 193                                         reg = <5>;
 194                                         label = "cpu";
 195                                         ethernet = <&fec>;
 196                                 };
 197                         };
 198                 };
 199         };
 200 };
 201
 202 &i2c1 {
 203         clock-frequency = <100000>;
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_i2c1>;
 206         status = "okay";
 207
 208         pca9555: gpio@23 {
 209                 compatible = "nxp,pca9555";
 210                 reg = <0x23>;
 211                 gpio-controller;
 212                 #gpio-cells = <2>;
 213         };
 214
 215         eeprom1: eeprom@50 {
 216                 compatible = "atmel,24c02";
 217                 reg = <0x50>;
 218                 pagesize = <16>;
 219         };
 220
 221         eeprom2: eeprom@51 {
 222                 compatible = "atmel,24c02";
 223                 reg = <0x51>;
 224                 pagesize = <16>;
 225         };
 226
 227         eeprom3: eeprom@52 {
 228                 compatible = "atmel,24c02";
 229                 reg = <0x52>;
 230                 pagesize = <16>;
 231         };
 232
 233         eeprom4: eeprom@53 {
 234                 compatible = "atmel,24c02";
 235                 reg = <0x53>;
 236                 pagesize = <16>;
 237         };
 238
 239         dts1672: rtc@68 {
 240                 compatible = "dallas,ds1672";
 241                 reg = <0x68>;
 242         };
 243 };
 244
 245 &i2c2 {
 246         clock-frequency = <100000>;
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_i2c2>;
 249         status = "okay";
 250
 251         magn@1c {
 252                 compatible = "st,lsm9ds1-magn";
 253                 reg = <0x1c>;
 254                 pinctrl-names = "default";
 255                 pinctrl-0 = <&pinctrl_mag>;
 256                 interrupt-parent = <&gpio5>;
 257                 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 258         };
 259
 260         ltc3676: pmic@3c {
 261                 compatible = "lltc,ltc3676";
 262                 reg = <0x3c>;
 263                 interrupt-parent = <&gpio1>;
 264                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 265
 266                 regulators {
 267                         /* VDD_SOC (1+R1/R2 = 1.635) */
 268                         reg_vdd_soc: sw1 {
 269                                 regulator-name = "vddsoc";
 270                                 regulator-min-microvolt = <674400>;
 271                                 regulator-max-microvolt = <1308000>;
 272                                 lltc,fb-voltage-divider = <127000 200000>;
 273                                 regulator-ramp-delay = <7000>;
 274                                 regulator-boot-on;
 275                                 regulator-always-on;
 276                         };
 277
 278                         /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
 279                         reg_1p8v: sw2 {
 280                                 regulator-name = "vdd1p8";
 281                                 regulator-min-microvolt = <1033310>;
 282                                 regulator-max-microvolt = <2004000>;
 283                                 lltc,fb-voltage-divider = <301000 200000>;
 284                                 regulator-ramp-delay = <7000>;
 285                                 regulator-boot-on;
 286                                 regulator-always-on;
 287                         };
 288
 289                         /* VDD_ARM (1+R1/R2 = 1.635) */
 290                         reg_vdd_arm: sw3 {
 291                                 regulator-name = "vddarm";
 292                                 regulator-min-microvolt = <674400>;
 293                                 regulator-max-microvolt = <1308000>;
 294                                 lltc,fb-voltage-divider = <127000 200000>;
 295                                 regulator-ramp-delay = <7000>;
 296                                 regulator-boot-on;
 297                                 regulator-always-on;
 298                         };
 299
 300                         /* VDD_DDR (1+R1/R2 = 2.105) */
 301                         reg_vdd_ddr: sw4 {
 302                                 regulator-name = "vddddr";
 303                                 regulator-min-microvolt = <868310>;
 304                                 regulator-max-microvolt = <1684000>;
 305                                 lltc,fb-voltage-divider = <221000 200000>;
 306                                 regulator-ramp-delay = <7000>;
 307                                 regulator-boot-on;
 308                                 regulator-always-on;
 309                         };
 310
 311                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 312                         reg_2p5v: ldo2 {
 313                                 regulator-name = "vdd2p5";
 314                                 regulator-min-microvolt = <2490375>;
 315                                 regulator-max-microvolt = <2490375>;
 316                                 lltc,fb-voltage-divider = <487000 200000>;
 317                                 regulator-boot-on;
 318                                 regulator-always-on;
 319                         };
 320
 321                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 322                         reg_3p0v: ldo4 {
 323                                 regulator-name = "vdd3p0";
 324                                 regulator-min-microvolt = <3023250>;
 325                                 regulator-max-microvolt = <3023250>;
 326                                 lltc,fb-voltage-divider = <634000 200000>;
 327                                 regulator-boot-on;
 328                                 regulator-always-on;
 329                         };
 330                 };
 331         };
 332
 333         imu@6a {
 334                 compatible = "st,lsm9ds1-imu";
 335                 reg = <0x6a>;
 336                 st,drdy-int-pin = <1>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&pinctrl_imu>;
 339                 interrupt-parent = <&gpio4>;
 340                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
 341         };
 342 };
 343
 344 &i2c3 {
 345         clock-frequency = <100000>;
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_i2c3>;
 348         status = "okay";
 349
 350         egalax_ts: touchscreen@4 {
 351                 compatible = "eeti,egalax_ts";
 352                 reg = <0x04>;
 353                 interrupt-parent = <&gpio1>;
 354                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 355                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 356         };
 357 };
 358
 359 &ldb {
 360         status = "okay";
 361
 362         lvds-channel@0 {
 363                 fsl,data-mapping = "spwg";
 364                 fsl,data-width = <18>;
 365                 status = "okay";
 366
 367                 display-timings {
 368                         native-mode = <&timing0>;
 369                         timing0: hsd100pxn1 {
 370                                 clock-frequency = <65000000>;
 371                                 hactive = <1024>;
 372                                 vactive = <768>;
 373                                 hback-porch = <220>;
 374                                 hfront-porch = <40>;
 375                                 vback-porch = <21>;
 376                                 vfront-porch = <7>;
 377                                 hsync-len = <60>;
 378                                 vsync-len = <10>;
 379                         };
 380                 };
 381         };
 382 };
 383
 384 &pcie {
 385         pinctrl-names = "default";
 386         pinctrl-0 = <&pinctrl_pcie>;
 387         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 388         status = "okay";
 389 };
 390
 391 &pwm2 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 394         status = "disabled";
 395 };
 396
 397 &pwm3 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 400         status = "disabled";
 401 };
 402
 403 &pwm4 {
 404         pinctrl-names = "default";
 405         pinctrl-0 = <&pinctrl_pwm4>;
 406         status = "okay";
 407 };
 408
 409 &uart1 {
 410         pinctrl-names = "default";
 411         pinctrl-0 = <&pinctrl_uart1>;
 412         status = "okay";
 413 };
 414
 415 &uart2 {
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&pinctrl_uart2>;
 418         status = "okay";
 419 };
 420
 421 &uart3 {
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&pinctrl_uart3>;
 424         uart-has-rtscts;
 425         status = "okay";
 426 };
 427
 428 &uart4 {
 429         pinctrl-names = "default";
 430         pinctrl-0 = <&pinctrl_uart4>;
 431         uart-has-rtscts;
 432         status = "okay";
 433 };
 434
 435 &uart5 {
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&pinctrl_uart5>;
 438         status = "okay";
 439 };
 440
 441 &usbotg {
 442         vbus-supply = <&reg_usb_otg_vbus>;
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_usbotg>;
 445         disable-over-current;
 446         status = "okay";
 447 };
 448
 449 &usbh1 {
 450         vbus-supply = <&reg_usb_h1_vbus>;
 451         status = "okay";
 452 };
 453
 454 &usdhc3 {
 455         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 456         pinctrl-0 = <&pinctrl_usdhc3>;
 457         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 458         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 459         non-removable;
 460         vmmc-supply = <&reg_3p3v>;
 461         keep-power-in-suspend;
 462         status = "okay";
 463 };
 464
 465 &wdog1 {
 466         pinctrl-names = "default";
 467         pinctrl-0 = <&pinctrl_wdog>;
 468         fsl,ext-reset-output;
 469 };
 470
 471 &iomuxc {
 472         pinctrl_enet: enetgrp {
 473                 fsl,pins = <
 474                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 475                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 476                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 477                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 478                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 479                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 480                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 481                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 482                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 483                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 484                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 485                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 486                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 487                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 488                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 489                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 490                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 491                 >;
 492         };
 493
 494         pinctrl_gpio_leds: gpioledsgrp {
 495                 fsl,pins = <
 496                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 497                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 498                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 499                 >;
 500         };
 501
 502         pinctrl_i2c1: i2c1grp {
 503                 fsl,pins = <
 504                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 505                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 506                 >;
 507         };
 508
 509         pinctrl_i2c2: i2c2grp {
 510                 fsl,pins = <
 511                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 512                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 513                 >;
 514         };
 515
 516         pinctrl_i2c3: i2c3grp {
 517                 fsl,pins = <
 518                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 519                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 520                 >;
 521         };
 522
 523         pinctrl_imu: imugrp {
 524                 fsl,pins = <
 525                         MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x1b0b0
 526                 >;
 527         };
 528
 529         pinctrl_mag: maggrp {
 530                 fsl,pins = <
 531                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 532                 >;
 533         };
 534
 535         pinctrl_pcie: pciegrp {
 536                 fsl,pins = <
 537                         MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x1b0b0 /* PCIE RST */
 538                 >;
 539         };
 540
 541         pinctrl_pmic: pmicgrp {
 542                 fsl,pins = <
 543                         MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0 /* PMIC_IRQ# */
 544                 >;
 545         };
 546
 547         pinctrl_pps: ppsgrp {
 548                 fsl,pins = <
 549                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 550                 >;
 551         };
 552
 553         pinctrl_pwm2: pwm2grp {
 554                 fsl,pins = <
 555                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 556                 >;
 557         };
 558
 559         pinctrl_pwm3: pwm3grp {
 560                 fsl,pins = <
 561                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 562                 >;
 563         };
 564
 565         pinctrl_pwm4: pwm4grp {
 566                 fsl,pins = <
 567                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 568                 >;
 569         };
 570
 571         pinctrl_uart1: uart1grp {
 572                 fsl,pins = <
 573                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 574                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 575                 >;
 576         };
 577
 578         pinctrl_uart2: uart2grp {
 579                 fsl,pins = <
 580                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 581                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 582                 >;
 583         };
 584
 585         pinctrl_uart3: uart3grp {
 586                 fsl,pins = <
 587                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 588                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 589                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 590                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 591                 >;
 592         };
 593
 594         pinctrl_uart4: uart4grp {
 595                 fsl,pins = <
 596                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 597                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 598                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 599                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 600                 >;
 601         };
 602
 603         pinctrl_uart5: uart5grp {
 604                 fsl,pins = <
 605                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 606                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 607                 >;
 608         };
 609
 610         pinctrl_usbotg: usbotggrp {
 611                 fsl,pins = <
 612                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 613                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 614                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 615                 >;
 616         };
 617
 618         pinctrl_usdhc3: usdhc3grp {
 619                 fsl,pins = <
 620                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 621                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 622                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
 623                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 624                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 625                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 626                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 627                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 628                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 629                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 630                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 631                 >;
 632         };
 633
 634         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 635                 fsl,pins = <
 636                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 637                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 638                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
 639                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 640                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 641                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 642                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 643                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 644                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 645                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 646                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 647                 >;
 648         };
 649
 650         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 651                 fsl,pins = <
 652                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 653                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 654                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
 655                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 656                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 657                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 658                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 659                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 660                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 661                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 662                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 663                 >;
 664         };
 665
 666         pinctrl_wdog: wdoggrp {
 667                 fsl,pins = <
 668                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 669                 >;
 670         };
 671 };