2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003-2008, Joseph Koshy
5 * Copyright (c) 2007 The FreeBSD Foundation
8 * Portions of this software were developed by A. Joseph Koshy under
9 * sponsorship from the FreeBSD Foundation and Google, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #include <dev/hwpmc/pmc_events.h>
40 #include <sys/counter.h>
41 #include <machine/pmc_mdep.h>
42 #include <machine/profile.h>
44 #include <sys/epoch.h>
48 #define PMC_MODULE_NAME "hwpmc"
49 #define PMC_NAME_MAX 64 /* HW counter name size */
50 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
53 * Kernel<->userland API version number [MMmmpppp]
55 * Major numbers are to be incremented when an incompatible change to
56 * the ABI occurs that older clients will not be able to handle.
58 * Minor numbers are incremented when a backwards compatible change
59 * occurs that allows older correct programs to run unchanged. For
60 * example, when support for a new PMC type is added.
62 * The patch version is incremented for every bug fix.
64 #define PMC_VERSION_MAJOR 0x03
65 #define PMC_VERSION_MINOR 0x01
66 #define PMC_VERSION_PATCH 0x0000
68 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \
69 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
72 * Kinds of CPUs known.
74 * We keep track of CPU variants that need to be distinguished in
75 * some way for PMC operations. CPU names are grouped by manufacturer
76 * and numbered sparsely in order to minimize changes to the ABI involved
77 * when new CPUs are added.
80 #define __PMC_CPUS() \
81 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \
82 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \
83 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \
84 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \
85 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \
86 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \
87 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \
88 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \
89 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
90 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
91 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
92 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
93 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
94 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
95 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
96 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \
97 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \
98 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \
99 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \
100 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \
101 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \
102 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \
103 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \
104 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \
105 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \
106 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \
107 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \
108 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \
109 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
110 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
111 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
112 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \
113 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
114 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \
115 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \
116 __PMC_CPU(GENERIC, 0x400, "Generic") \
117 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \
118 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \
119 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \
120 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \
121 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \
122 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \
123 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \
124 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57")
128 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
132 #define PMC_CPU_FIRST PMC_CPU_AMD_K7
133 #define PMC_CPU_LAST PMC_CPU_GENERIC
139 #define __PMC_CLASSES() \
140 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
141 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \
142 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
143 __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \
144 __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \
145 __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \
146 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \
147 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \
148 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \
149 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \
150 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \
151 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \
152 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \
153 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \
154 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \
155 __PMC_CLASS(SOFT, 0x0F, "Software events") \
156 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \
157 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \
158 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \
159 __PMC_CLASS(E500, 0x13, "Freescale e500 class")
163 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V,
167 #define PMC_CLASS_FIRST PMC_CLASS_TSC
168 #define PMC_CLASS_LAST PMC_CLASS_E500
171 * A PMC can be in the following states:
174 * DISABLED -- administratively prohibited from being used.
175 * FREE -- HW available for use
177 * ALLOCATED -- allocated
178 * STOPPED -- allocated, but not counting events
179 * RUNNING -- allocated, and in operation; 'pm_runcount'
180 * holds the number of CPUs using this PMC at
182 * DELETED -- being destroyed
185 #define __PMC_HWSTATES() \
186 __PMC_STATE(DISABLED) \
189 #define __PMC_SWSTATES() \
190 __PMC_STATE(ALLOCATED) \
191 __PMC_STATE(STOPPED) \
192 __PMC_STATE(RUNNING) \
195 #define __PMC_STATES() \
201 #define __PMC_STATE(S) PMC_STATE_##S,
206 #define PMC_STATE_FIRST PMC_STATE_DISABLED
207 #define PMC_STATE_LAST PMC_STATE_DELETED
210 * An allocated PMC may used as a 'global' counter or as a
211 * 'thread-private' one. Each such mode of use can be in either
212 * statistical sampling mode or in counting mode. Thus a PMC in use
214 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling
215 * SC i.e., SYSTEM COUNTER -- system-wide counting mode
216 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling
217 * TC i.e., THREAD COUNTER -- thread virtual, counting mode
219 * Statistical profiling modes rely on the PMC periodically delivering
220 * a interrupt to the CPU (when the configured number of events have
221 * been measured), so the PMC must have the ability to generate
224 * In counting modes, the PMC counts its configured events, with the
225 * value of the PMC being read whenever needed by its owner process.
227 * The thread specific modes "virtualize" the PMCs -- the PMCs appear
228 * to be thread private and count events only when the profiled thread
229 * actually executes on the CPU.
231 * The system-wide "global" modes keep the PMCs running all the time
232 * and are used to measure the behaviour of the whole system.
235 #define __PMC_MODES() \
243 #define __PMC_MODE(M,N) PMC_MODE_##M = N,
247 #define PMC_MODE_FIRST PMC_MODE_SS
248 #define PMC_MODE_LAST PMC_MODE_TC
250 #define PMC_IS_COUNTING_MODE(mode) \
251 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC)
252 #define PMC_IS_SYSTEM_MODE(mode) \
253 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC)
254 #define PMC_IS_SAMPLING_MODE(mode) \
255 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS)
256 #define PMC_IS_VIRTUAL_MODE(mode) \
257 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC)
260 * PMC row disposition
263 #define __PMC_DISPOSITIONS(N) \
264 __PMC_DISP(STANDALONE) /* global/disabled counters */ \
265 __PMC_DISP(FREE) /* free/available */ \
266 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \
267 __PMC_DISP(UNKNOWN) /* sentinel */
271 #define __PMC_DISP(D) PMC_DISP_##D ,
275 #define PMC_DISP_FIRST PMC_DISP_STANDALONE
276 #define PMC_DISP_LAST PMC_DISP_THREAD
279 * Counter capabilities
281 * __PMC_CAPS(NAME, VALUE, DESCRIPTION)
284 #define __PMC_CAPS() \
285 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \
286 __PMC_CAP(USER, 1, "count user-mode events") \
287 __PMC_CAP(SYSTEM, 2, "count system-mode events") \
288 __PMC_CAP(EDGE, 3, "do edge detection of events") \
289 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \
290 __PMC_CAP(READ, 5, "read PMC counter") \
291 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \
292 __PMC_CAP(INVERT, 7, "invert comparison sense") \
293 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \
294 __PMC_CAP(PRECISE, 9, "perform precise sampling") \
295 __PMC_CAP(TAGGING, 10, "tag upstream events") \
296 __PMC_CAP(CASCADE, 11, "cascade counters")
301 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) ,
305 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT
306 #define PMC_CAP_LAST PMC_CAP_CASCADE
311 * These are generated from the definitions in "dev/hwpmc/pmc_events.h".
316 #undef __PMC_EV_BLOCK
317 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
318 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N ,
323 * PMC SYSCALL INTERFACE
327 * "PMC_OPS" -- these are the commands recognized by the kernel
328 * module, and are used when performing a system call from userland.
330 #define __PMC_OPS() \
331 __PMC_OP(CONFIGURELOG, "Set log file") \
332 __PMC_OP(FLUSHLOG, "Flush log file") \
333 __PMC_OP(GETCPUINFO, "Get system CPU information") \
334 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \
335 __PMC_OP(GETMODULEVERSION, "Get module version") \
336 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \
337 __PMC_OP(PMCADMIN, "Set PMC state") \
338 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \
339 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \
340 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \
341 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \
342 __PMC_OP(PMCRELEASE, "Release a PMC") \
343 __PMC_OP(PMCRW, "Read/Set a PMC") \
344 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \
345 __PMC_OP(PMCSTART, "Start a PMC") \
346 __PMC_OP(PMCSTOP, "Stop a PMC") \
347 __PMC_OP(WRITELOG, "Write a cookie to the log file") \
348 __PMC_OP(CLOSELOG, "Close log file") \
349 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list")
354 #define __PMC_OP(N, D) PMC_OP_##N,
360 * Flags used in operations on PMCs.
363 #define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */
364 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */
365 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */
366 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */
367 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */
368 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */
369 #define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */
371 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */
374 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/
375 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */
376 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */
378 #define PMC_CALLCHAIN_DEPTH_MAX 128
380 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/
383 * Cookies used to denote allocated PMCs, and the values of PMCs.
386 typedef uint32_t pmc_id_t;
387 typedef uint64_t pmc_value_t;
389 #define PMC_ID_INVALID (~ (pmc_id_t) 0)
392 * PMC IDs have the following format:
394 * +--------+----------+-----------+-----------+
395 * | CPU | PMC MODE | PMC CLASS | ROW INDEX |
396 * +--------+----------+-----------+-----------+
398 * where each field is 8 bits wide. Field 'CPU' is set to the
399 * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode
400 * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC
401 * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index
404 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total
405 * number of hardware PMCs on this cpu.
409 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF)
410 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8)
411 #define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16)
412 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24)
413 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \
414 ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \
415 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF))
418 * Data structures for system calls supported by the pmc driver.
424 * Allocate a PMC on the named CPU.
427 #define PMC_CPU_ANY ~0
429 struct pmc_op_pmcallocate {
430 uint32_t pm_caps; /* PMC_CAP_* */
431 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */
432 enum pmc_class pm_class; /* class of PMC desired */
433 enum pmc_event pm_ev; /* [enum pmc_event] desired */
434 uint32_t pm_flags; /* additional modifiers PMC_F_* */
435 enum pmc_mode pm_mode; /* desired mode */
436 pmc_id_t pm_pmcid; /* [return] process pmc id */
438 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */
444 * Set the administrative state (i.e., whether enabled or disabled) of
445 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an
446 * absolute PMC number and need not have been first allocated by the
450 struct pmc_op_pmcadmin {
451 int pm_cpu; /* CPU# */
452 uint32_t pm_flags; /* flags */
453 int pm_pmc; /* PMC# */
454 enum pmc_state pm_state; /* desired state */
458 * OP PMCATTACH / OP PMCDETACH
460 * Attach/detach a PMC and a process.
463 struct pmc_op_pmcattach {
464 pmc_id_t pm_pmc; /* PMC to attach to */
465 pid_t pm_pid; /* target process */
471 * Set the sampling rate (i.e., the reload count) for statistical counters.
472 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE.
475 struct pmc_op_pmcsetcount {
476 pmc_value_t pm_count; /* initial/sample count */
477 pmc_id_t pm_pmcid; /* PMC id to set */
484 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs
485 * to have been previously allocated using PMCALLOCATE.
489 struct pmc_op_pmcrw {
490 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/
491 pmc_id_t pm_pmcid; /* pmc id */
492 pmc_value_t pm_value; /* new&returned value */
499 * retrieve PMC state for a named CPU. The caller is expected to
500 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return
505 char pm_name[PMC_NAME_MAX]; /* pmc name */
506 enum pmc_class pm_class; /* enum pmc_class */
507 int pm_enabled; /* whether enabled */
508 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */
509 pid_t pm_ownerpid; /* owner, or -1 */
510 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */
511 enum pmc_event pm_event; /* current event */
512 uint32_t pm_flags; /* current flags */
513 pmc_value_t pm_reloadcount; /* sampling counters only */
516 struct pmc_op_getpmcinfo {
517 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */
518 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */
525 * Retrieve system CPU information.
529 struct pmc_classinfo {
530 enum pmc_class pm_class; /* class id */
531 uint32_t pm_caps; /* counter capabilities */
532 uint32_t pm_width; /* width of the PMC */
533 uint32_t pm_num; /* number of PMCs in class */
536 struct pmc_op_getcpuinfo {
537 enum pmc_cputype pm_cputype; /* what kind of CPU */
538 uint32_t pm_ncpu; /* max CPU number */
539 uint32_t pm_npmc; /* #PMCs per CPU */
540 uint32_t pm_nclass; /* #classes of PMCs */
541 struct pmc_classinfo pm_classes[PMC_CLASS_MAX];
547 * Configure a log file for writing system-wide statistics to.
550 struct pmc_op_configurelog {
552 int pm_logfd; /* logfile fd (or -1) */
558 * Retrieve pmc(4) driver-wide statistics.
561 struct pmc_driverstats {
562 counter_u64_t pm_intr_ignored; /* #interrupts ignored */
563 counter_u64_t pm_intr_processed; /* #interrupts processed */
564 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */
565 counter_u64_t pm_syscalls; /* #syscalls */
566 counter_u64_t pm_syscall_errors; /* #syscalls with errors */
567 counter_u64_t pm_buffer_requests; /* #buffer requests */
568 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */
569 counter_u64_t pm_log_sweeps; /* #sample buffer processing
574 struct pmc_op_getdriverstats {
575 unsigned int pm_intr_ignored; /* #interrupts ignored */
576 unsigned int pm_intr_processed; /* #interrupts processed */
577 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */
578 unsigned int pm_syscalls; /* #syscalls */
579 unsigned int pm_syscall_errors; /* #syscalls with errors */
580 unsigned int pm_buffer_requests; /* #buffer requests */
581 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */
582 unsigned int pm_log_sweeps; /* #sample buffer processing
587 * OP RELEASE / OP START / OP STOP
589 * Simple operations on a PMC id.
592 struct pmc_op_simple {
599 * Flush the current log buffer and write 4 bytes of user data to it.
602 struct pmc_op_writelog {
603 uint32_t pm_userdata;
609 * Retrieve the machine specific address associated with the allocated
610 * PMC. This number can be used subsequently with a read-performance-counter
614 struct pmc_op_getmsr {
615 uint32_t pm_msr; /* machine specific address */
616 pmc_id_t pm_pmcid; /* allocated pmc id */
622 * Retrieve a PMC dynamic class events list.
625 struct pmc_dyn_event_descr {
626 char pm_ev_name[PMC_NAME_MAX];
627 enum pmc_event pm_ev_code;
630 struct pmc_op_getdyneventinfo {
631 enum pmc_class pm_class;
632 unsigned int pm_nevent;
633 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT];
638 #include <sys/malloc.h>
639 #include <sys/sysctl.h>
640 #include <sys/_cpuset.h>
642 #include <machine/frame.h>
644 #define PMC_HASH_SIZE 1024
645 #define PMC_MTXPOOL_SIZE 2048
646 #define PMC_LOG_BUFFER_SIZE 128
647 #define PMC_NLOGBUFFERS_PCPU 8
648 #define PMC_NSAMPLES 64
649 #define PMC_CALLCHAIN_DEPTH 32
650 #define PMC_THREADLIST_MAX 64
652 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "."
657 * (b) - pmc_bufferlist_mtx (spin lock)
658 * (k) - pmc_kthread_mtx (sleep lock)
659 * (o) - po->po_mtx (spin lock)
666 struct pmc_syscall_args {
667 register_t pmop_code; /* one of PMC_OP_* */
668 void *pmop_data; /* syscall parameter */
672 * Interface to processor specific s1tuff
678 * Machine independent (i.e., the common parts) of a human readable
683 char pd_name[PMC_NAME_MAX]; /* name */
684 uint32_t pd_caps; /* capabilities */
685 enum pmc_class pd_class; /* class of the PMC */
686 uint32_t pd_width; /* width in bits */
692 * This structure records all the target processes associated with a
697 LIST_ENTRY(pmc_target) pt_next;
698 struct pmc_process *pt_process; /* target descriptor */
704 * Describes each allocated PMC.
706 * Each PMC has precisely one owner, namely the process that allocated
709 * A PMC may be attached to multiple target processes. The
710 * 'pm_targets' field links all the target processes being monitored
713 * The 'pm_savedvalue' field is protected by a mutex.
715 * On a multi-cpu machine, multiple target threads associated with a
716 * process-virtual PMC could be concurrently executing on different
717 * CPUs. The 'pm_runcount' field is atomically incremented every time
718 * the PMC gets scheduled on a CPU and atomically decremented when it
719 * get descheduled. Deletion of a PMC is only permitted when this
723 struct pmc_pcpu_state {
725 uint8_t pps_cpustate;
726 } __aligned(CACHE_LINE_SIZE);
728 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */
729 LIST_ENTRY(pmc) pm_next; /* owner's list */
732 * System-wide PMCs are allocated on a CPU and are not moved
733 * around. For system-wide PMCs we record the CPU the PMC was
734 * allocated on in the 'CPU' field of the pmc ID.
736 * Virtual PMCs run on whichever CPU is currently executing
737 * their targets' threads. For these PMCs we need to save
738 * their current PMC counter values when they are taken off
743 pmc_value_t pm_savedvalue; /* Virtual PMCS */
747 * For sampling mode PMCs, we keep track of the PMC's "reload
748 * count", which is the counter value to be loaded in when
749 * arming the PMC for the next counting session. For counting
750 * modes on PMCs that are read-only (e.g., the x86 TSC), we
751 * keep track of the initial value at the start of
752 * counting-mode operation.
756 pmc_value_t pm_reloadcount; /* sampling PMC modes */
757 pmc_value_t pm_initial; /* counting PMC modes */
760 struct pmc_pcpu_state *pm_pcpu_state;
761 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */
762 uint32_t pm_caps; /* PMC capabilities */
763 enum pmc_event pm_event; /* event being measured */
764 uint32_t pm_flags; /* additional flags PMC_F_... */
765 struct pmc_owner *pm_owner; /* owner thread state */
766 counter_u64_t pm_runcount; /* #cpus currently on */
767 enum pmc_state pm_state; /* current PMC state */
768 uint32_t pm_overflowcnt; /* count overflow interrupts */
771 * The PMC ID field encodes the row-index for the PMC, its
772 * mode, class and the CPU# associated with the PMC.
775 pmc_id_t pm_id; /* allocated PMC id */
778 union pmc_md_pmc pm_md;
782 * Accessor macros for 'struct pmc'
785 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id)
786 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id)
787 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id)
788 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id)
791 * struct pmc_threadpmcstate
793 * Record per-PMC, per-thread state.
795 struct pmc_threadpmcstate {
796 pmc_value_t pt_pmcval; /* per-thread reload count */
802 * Record a 'target' thread being profiled.
805 LIST_ENTRY(pmc_thread) pt_next; /* linked list */
806 struct thread *pt_td; /* target thread */
807 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */
813 * Record a 'target' process being profiled.
815 * The target process being profiled could be different from the owner
816 * process which allocated the PMCs. Each target process descriptor
817 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a
818 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]'
819 * array. The size of this structure is thus PMC architecture
824 struct pmc_targetstate {
825 struct pmc *pp_pmc; /* target PMC */
826 pmc_value_t pp_pmcval; /* per-process value */
830 LIST_ENTRY(pmc_process) pp_next; /* hash chain */
831 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */
832 struct mtx *pp_tdslock; /* lock on pp_tds thread list */
833 int pp_refcnt; /* reference count */
834 uint32_t pp_flags; /* flags PMC_PP_* */
835 struct proc *pp_proc; /* target process */
836 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */
839 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001
844 * We associate a PMC with an 'owner' process.
846 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its
847 * lifetime, where NCPUS is the numbers of CPUS in the system and
848 * NHWPMC is the number of hardware PMCs per CPU. These are
849 * maintained in the list headed by the 'po_pmcs' to save on space.
854 LIST_ENTRY(pmc_owner) po_next; /* hash chain */
855 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */
856 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */
857 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */
858 struct mtx po_mtx; /* spin lock for (o) */
859 struct proc *po_owner; /* owner proc */
860 uint32_t po_flags; /* (k) flags PMC_PO_* */
861 struct proc *po_kthread; /* (k) helper kthread */
862 struct file *po_file; /* file reference */
863 int po_error; /* recorded error */
864 short po_sscount; /* # SS PMCs owned */
865 short po_logprocmaps; /* global mappings done */
866 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */
869 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */
870 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */
871 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020
874 * struct pmc_hw -- describe the state of the PMC hardware
876 * When in use, a HW PMC is associated with one allocated 'struct pmc'
877 * pointed to by field 'phw_pmc'. When inactive, this field is NULL.
879 * On an SMP box, one or more HW PMC's in process virtual mode with
880 * the same 'phw_pmc' could be executing on different CPUs. In order
881 * to handle this case correctly, we need to ensure that only
882 * incremental counts get added to the saved value in the associated
883 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC
884 * value at the time the hardware is started during this context
885 * switch (i.e., the difference between the new (hardware) count and
886 * the saved count is atomically added to the count field in 'struct
887 * pmc' at context switch time).
892 uint32_t phw_state; /* see PHW_* macros below */
893 struct pmc *phw_pmc; /* current thread PMC */
896 #define PMC_PHW_RI_MASK 0x000000FF
897 #define PMC_PHW_CPU_SHIFT 8
898 #define PMC_PHW_CPU_MASK 0x0000FF00
899 #define PMC_PHW_FLAGS_SHIFT 16
900 #define PMC_PHW_FLAGS_MASK 0xFFFF0000
902 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK)
903 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK)
904 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \
906 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \
908 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \
910 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \
912 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01))
913 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02))
918 * Space for N (tunable) PC samples and associated control data.
922 uint16_t ps_nsamples; /* callchain depth */
923 uint8_t ps_cpu; /* cpu number */
924 uint8_t ps_flags; /* other flags */
925 pid_t ps_pid; /* process PID or -1 */
926 struct thread *ps_td; /* which thread */
927 struct pmc *ps_pmc; /* interrupting PMC */
928 uintptr_t *ps_pc; /* (const) callchain start */
931 #define PMC_SAMPLE_FREE ((uint16_t) 0)
932 #define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF)
934 struct pmc_samplebuffer {
935 struct pmc_sample * volatile ps_read; /* read pointer */
936 struct pmc_sample * volatile ps_write; /* write pointer */
937 uintptr_t *ps_callchains; /* all saved call chains */
938 struct pmc_sample *ps_fence; /* one beyond ps_samples[] */
939 struct pmc_sample ps_samples[]; /* array of sample entries */
944 * struct pmc_cpustate
946 * A CPU is modelled as a collection of HW PMCs with space for additional
951 uint32_t pc_state; /* physical cpu number + flags */
952 struct pmc_samplebuffer *pc_sb[2]; /* space for samples */
953 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */
956 #define PMC_PCPU_CPU_MASK 0x000000FF
957 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00
958 #define PMC_PCPU_FLAGS_SHIFT 8
959 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK)
960 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT)
961 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK)
962 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK)
963 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1))
968 * CPU binding information.
972 int pb_bound; /* is bound? */
973 int pb_cpu; /* if so, to which CPU */
980 * struct pmc_classdep
982 * PMC class-dependent operations.
984 struct pmc_classdep {
985 uint32_t pcd_caps; /* class capabilities */
986 enum pmc_class pcd_class; /* class id */
987 int pcd_num; /* number of PMCs */
988 int pcd_ri; /* row index of the first PMC in class */
989 int pcd_width; /* width of the PMC */
991 /* configuring/reading/writing the hardware PMCs */
992 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm);
993 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm);
994 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value);
995 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);
997 /* pmc allocation/release */
998 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t,
999 const struct pmc_op_pmcallocate *_a);
1000 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm);
1002 /* starting and stopping PMCs */
1003 int (*pcd_start_pmc)(int _cpu, int _ri);
1004 int (*pcd_stop_pmc)(int _cpu, int _ri);
1007 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi,
1008 struct pmc **_ppmc);
1010 /* class-dependent initialization & finalization */
1011 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
1012 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
1014 /* machine-specific interface */
1015 int (*pcd_get_msr)(int _ri, uint32_t *_msr);
1021 * Machine dependent bits needed per CPU type.
1025 uint32_t pmd_cputype; /* from enum pmc_cputype */
1026 uint32_t pmd_npmc; /* number of PMCs per CPU */
1027 uint32_t pmd_nclass; /* number of PMC classes present */
1030 * Machine dependent methods.
1033 /* per-cpu initialization and finalization */
1034 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
1035 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
1037 /* thread context switch in/out */
1038 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp);
1039 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp);
1041 /* handle a PMC interrupt */
1042 int (*pmd_intr)(int _cpu, struct trapframe *_tf);
1045 * PMC class dependent information.
1047 struct pmc_classdep pmd_classdep[];
1051 * Per-CPU state. This is an array of 'mp_ncpu' pointers
1052 * to struct pmc_cpu descriptors.
1055 extern struct pmc_cpu **pmc_pcpu;
1057 /* driver statistics */
1058 extern struct pmc_driverstats pmc_stats;
1060 /* cpu model name for pmu lookup */
1061 extern char pmc_cpuid[64];
1063 #if defined(HWPMC_DEBUG)
1064 #include <sys/ktr.h>
1066 /* debug flags, major flag groups */
1067 struct pmc_debugflags {
1079 extern struct pmc_debugflags pmc_debugflags;
1081 #define KTR_PMC KTR_SUBSYS
1083 #define PMC_DEBUG_STRSIZE 128
1084 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1086 #define PMCDBG0(M, N, L, F) do { \
1087 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1088 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \
1090 #define PMCDBG1(M, N, L, F, p1) do { \
1091 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1092 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \
1094 #define PMCDBG2(M, N, L, F, p1, p2) do { \
1095 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1096 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \
1098 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \
1099 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1100 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \
1102 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \
1103 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1104 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\
1106 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \
1107 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1108 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1111 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \
1112 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1113 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1118 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */
1119 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */
1120 #define PMC_DEBUG_MAJ_LOG 2 /* logging */
1121 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */
1122 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */
1123 #define PMC_DEBUG_MAJ_OWN 5 /* owner */
1124 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */
1125 #define PMC_DEBUG_MAJ_PRC 7 /* processes */
1126 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */
1130 /* Common (8 bits) */
1131 #define PMC_DEBUG_MIN_ALL 0 /* allocation */
1132 #define PMC_DEBUG_MIN_REL 1 /* release */
1133 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */
1134 #define PMC_DEBUG_MIN_INI 3 /* init */
1135 #define PMC_DEBUG_MIN_FND 4 /* find */
1138 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */
1139 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */
1142 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */
1143 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */
1146 #define PMC_DEBUG_MIN_TLK 8 /* link target */
1147 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */
1148 #define PMC_DEBUG_MIN_EXT 10 /* process exit */
1149 #define PMC_DEBUG_MIN_EXC 11 /* process exec */
1150 #define PMC_DEBUG_MIN_FRK 12 /* process fork */
1151 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */
1152 #define PMC_DEBUG_MIN_SIG 14 /* signalling */
1154 /* CONTEXT SWITCHES */
1155 #define PMC_DEBUG_MIN_SWI 8 /* switch in */
1156 #define PMC_DEBUG_MIN_SWO 9 /* switch out */
1159 #define PMC_DEBUG_MIN_REG 8 /* pmc register */
1160 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */
1162 /* MACHINE DEPENDENT LAYER */
1163 #define PMC_DEBUG_MIN_REA 8 /* read */
1164 #define PMC_DEBUG_MIN_WRI 9 /* write */
1165 #define PMC_DEBUG_MIN_CFG 10 /* config */
1166 #define PMC_DEBUG_MIN_STA 11 /* start */
1167 #define PMC_DEBUG_MIN_STO 12 /* stop */
1168 #define PMC_DEBUG_MIN_INT 13 /* interrupts */
1171 #define PMC_DEBUG_MIN_BND 8 /* bind */
1172 #define PMC_DEBUG_MIN_SEL 9 /* select */
1175 #define PMC_DEBUG_MIN_GTB 8 /* get buf */
1176 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */
1177 #define PMC_DEBUG_MIN_FLS 10 /* flush */
1178 #define PMC_DEBUG_MIN_SAM 11 /* sample */
1179 #define PMC_DEBUG_MIN_CLO 12 /* close */
1182 #define PMCDBG0(M, N, L, F) /* nothing */
1183 #define PMCDBG1(M, N, L, F, p1)
1184 #define PMCDBG2(M, N, L, F, p1, p2)
1185 #define PMCDBG3(M, N, L, F, p1, p2, p3)
1186 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4)
1187 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5)
1188 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6)
1191 /* declare a dedicated memory pool */
1192 MALLOC_DECLARE(M_PMC);
1198 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */
1199 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */
1200 int pmc_getrowdisp(int _ri);
1201 int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm,
1202 struct trapframe *_tf, int _inuserspace);
1203 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples,
1204 struct trapframe *_tf);
1205 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples,
1206 struct trapframe *_tf);
1207 struct pmc_mdep *pmc_mdep_alloc(int nclasses);
1208 void pmc_mdep_free(struct pmc_mdep *md);
1209 #endif /* _KERNEL */
1210 #endif /* _SYS_PMC_H_ */