#include <dt-bindings/clock/jz4780-cgu.h>
#include <dt-bindings/dma/jz4780-dma.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "ingenic,jz4780";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "ingenic,xburst";
			reg = <0>;
		};
		cpu1: cpu@1 {
			compatible = "ingenic,xburst";
			reg = <1>;
			clocks = <&cgu JZ4780_CLK_CORE1>;
		};
	};

	cpuintc: cpuintc@0 {
		#address-cells = <0>;
		#interrupt-cells = <1>;
		interrupt-controller;
		compatible = "mti,cpu-interrupt-controller";
	};

	intc: intc@10001000 {
		compatible = "ingenic,jz4780-intc";
		reg = <0x10001000 0x50>;

		interrupt-controller;
		#interrupt-cells = <1>;

		interrupt-parent = <&cpuintc>;
		interrupts = <2>;
	};

	ext: ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

	rtc: rtc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};

	cgu: jz4780-cgu@10000000 {
		compatible = "ingenic,jz4780-cgu";
		reg = <0x10000000 0x100>;

		clocks = <&ext>, <&rtc>;
		clock-names = "ext", "rtc";

		#clock-cells = <1>;
	};

	gpu: jz4780-sgx@13040000 {
		compatible = "ingenic,jz4780-sgx";
		reg = <0x13040000 0x4000>;

		clocks = <&cgu JZ4780_CLK_GPU>;
		clock-names = "gpu";

		interrupt-parent = <&intc>;
		interrupts = <63>;
	};

	apb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <>;

		tcu@0x10002000 {
			compatible = "ingenic,jz4780-tcu";
			reg = <0x10002000 0x140>;

			interrupt-parent = <&intc>;
			interrupts = <27 26 25>;
		};

		watchdog: jz47xx-watchdog@0x10002000 {
			compatible = "ingenic,jz4780-watchdog";
			reg = <0x10002000 0x100>;

			clocks = <&rtc>;
			clock-names = "rtc";
		};

		rtcdev: rtcdev@10003000 {
			compatible = "ingenic,jz4780-rtc";
			reg = <0x10003000 0x4c>;
			interrupt-parent = <&intc>;
			interrupts = <32>;
		};

		i2s: i2s@10020000 {
			compatible = "ingenic,jz4780-i2s";
			reg = <0x10020000 0x94>;

			clocks = <&cgu JZ4780_CLK_AIC>, <&cgu JZ4780_CLK_I2SPLL>;
			clock-names = "aic", "i2s";

			dmas = <&dma 0 JZ4780_DMA_I2S0_RX 0xffffffff>, <&dma JZ4780_DMA_I2S0_TX 0 0xffffffff>;
			dma-names = "rx" , "tx";

		};

		codec: codec@100200a4 {
			compatible = "ingenic,jz4780-codec";
			reg = <0x100200a4 0x8>;

			clocks = <&cgu JZ4780_CLK_I2SPLL>;
			clock-names = "i2s";

		};

		pinctrl@0x10010000 {
			compatible = "ingenic,jz4780-pinctrl";
			reg = <0x10010000 0x600>;

			gpa: gpa {
				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&intc>;
				interrupts = <17>;

				ingenic,pull-ups = <0x3fffffff>;
			};

			gpb: gpb {
				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&intc>;
				interrupts = <16>;

				ingenic,pull-downs = <0x000f0c03>;
				ingenic,pull-ups   = <0xfff0030c>;
			};

			gpc: gpc {
				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&intc>;
				interrupts = <15>;

				ingenic,pull-ups = <0xffffffff>;
			};

			gpd: gpd {
				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&intc>;
				interrupts = <14>;

				ingenic,pull-downs = <0x0000b000>;
				ingenic,pull-ups   = <0xffff4fff>;
			};

			gpe: gpe {
				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&intc>;
				interrupts = <13>;

				ingenic,pull-downs = <0x00000483>;
				ingenic,pull-ups   = <0xfffffb7c>;
			};

			gpf: gpf {
				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;

				interrupt-parent = <&intc>;
				interrupts = <12>;

				ingenic,pull-downs = <0x00580ff0>;
				ingenic,pull-ups   = <0xffa7f00f>;
			};

			pincfg_nobias: nobias {
				bias-disable;
			};

			pincfg_pull_up: pull_up {
				bias-pull-up;
			};

			pincfg_pull_down: pull_down {
				bias-pull-down;
			};

			pinfunc_uart0: uart0 {
				pins_uart0_data: uart0-data {
					ingenic,pins = <&gpf  0 0 &pincfg_pull_up  /* rxd */
							&gpf  3 0 &pincfg_nobias>; /* txd */
				};

				pins_uart0_dataplusflow: uart0-dataplusflow {
					ingenic,pins = <&gpf  0 0 &pincfg_pull_up  /* rxd */
							&gpf  1 0 &pincfg_nobias   /* cts */
							&gpf  2 0 &pincfg_nobias   /* rts */
							&gpf  3 0 &pincfg_nobias>; /* txd */
				};
			};

			pinfunc_uart1: uart1 {
				pins_uart1_data: uart1-data {
					ingenic,pins = <&gpd  26 0 &pincfg_pull_up  /* rxd */
							&gpd  28 0 &pincfg_nobias>; /* txd */
				};

				pins_uart1_dataplusflow: uart1-dataplusflow {
					ingenic,pins = <&gpd  26 0 &pincfg_pull_up  /* rxd */
							&gpd  27 0 &pincfg_nobias   /* cts */
							&gpd  29 0 &pincfg_nobias   /* rts */
							&gpd  28 0 &pincfg_nobias>; /* txd */
				};
			};

			pinfunc_uart2: uart2 {
				pins_uart2_data: uart2-data {
					ingenic,pins = <&gpd  6 1 &pincfg_nobias  /* rxd */
							&gpd  7 1 &pincfg_nobias>; /* txd */
				};

				pins_uart2_dataplusflow: uart2-dataplusflow {
					ingenic,pins = <&gpd  6 1 &pincfg_nobias  /* rxd */
							&gpd  5 1 &pincfg_nobias   /* cts */
							&gpd  4 1 &pincfg_nobias   /* rts */
							&gpd  7 1 &pincfg_nobias>; /* txd */
				};
			};

			pinfunc_uart3: uart3 {
				pins_uart3_data: uart3-data {
					ingenic,pins = <&gpd 12 0 &pincfg_pull_down /* rxd */
							&gpe  5 1 &pincfg_nobias>;  /* txd */
				};

				pins_uart3_dataplusflow: uart3-dataplusflow {
					ingenic,pins = <&gpd 12 0 &pincfg_pull_down /* rxd */
							&gpe  5 1 &pincfg_nobias    /* txd */
							&gpe  8 0 &pincfg_nobias    /* cts */
							&gpe  9 0 &pincfg_nobias>;  /* rts */
				};
			};

			pinfunc_uart4: uart4 {
				pins_uart4_data: uart4-data {
					ingenic,pins = <&gpc 20 2 &pincfg_pull_up   /* rxd */
							&gpc 10 2 &pincfg_nobias>;  /* txd */
				};
			};

			pinfunc_msc0: msc0 {
				pins_msc0_pa: msc0-pa {
					ingenic,pins = <&gpa  4 1 &pincfg_nobias   /* d4 */
							&gpa  5 1 &pincfg_nobias   /* d5 */
							&gpa  6 1 &pincfg_nobias   /* d6 */
							&gpa  7 1 &pincfg_nobias   /* d7 */
							&gpa 18 1 &pincfg_nobias   /* clk */
							&gpa 19 1 &pincfg_nobias   /* cmd */
							&gpa 20 1 &pincfg_nobias   /* d0 */
							&gpa 21 1 &pincfg_nobias   /* d1 */
							&gpa 22 1 &pincfg_nobias   /* d2 */
							&gpa 23 1 &pincfg_nobias   /* d3 */
							&gpa 24 1 &pincfg_nobias>; /* rst */
				};

				pins_msc0_pe: msc0-pe {
					ingenic,pins = <&gpe 20 0 &pincfg_nobias   /* d0 */
							&gpe 21 0 &pincfg_nobias   /* d1 */
							&gpe 22 0 &pincfg_nobias   /* d2 */
							&gpe 23 0 &pincfg_nobias   /* d3 */
							&gpe 28 0 &pincfg_nobias   /* clk */
							&gpe 29 0 &pincfg_nobias>; /* cmd */
				};
			};

			pinfunc_msc1: msc1 {
				pins_msc1_pd: msc1-pd {
					ingenic,pins = <&gpd 20 0 &pincfg_nobias   /* d0 */
							&gpd 21 0 &pincfg_nobias   /* d1 */
							&gpd 22 0 &pincfg_nobias   /* d2 */
							&gpd 23 0 &pincfg_nobias   /* d3 */
							&gpd 24 0 &pincfg_nobias   /* clk */
							&gpd 25 0 &pincfg_nobias>; /* cmd */
				};

				pins_msc1_pe: msc1-pe {
					ingenic,pins = <&gpe 20 1 &pincfg_nobias   /* d0 */
							&gpe 21 1 &pincfg_nobias   /* d1 */
							&gpe 22 1 &pincfg_nobias   /* d2 */
							&gpe 23 1 &pincfg_nobias   /* d3 */
							&gpe 28 1 &pincfg_nobias   /* clk */
							&gpe 29 1 &pincfg_nobias>; /* cmd */
				};
			};

			pinfunc_nemc: nemc {
				pins_nemc_data: nemc-data {
					ingenic,pins = <&gpa 0 0 &pincfg_nobias    /* sd0 */
							&gpa 1 0 &pincfg_nobias    /* sd1 */
							&gpa 2 0 &pincfg_nobias    /* sd2 */
							&gpa 3 0 &pincfg_nobias    /* sd3 */
							&gpa 4 0 &pincfg_nobias    /* sd4 */
							&gpa 5 0 &pincfg_nobias    /* sd5 */
							&gpa 6 0 &pincfg_nobias    /* sd6 */
							&gpa 7 0 &pincfg_nobias>;  /* sd7 */
				};

				pins_nemc_cle_ale: nemc-cle-ale {
					ingenic,pins = <&gpb 0 0 &pincfg_nobias    /* sa0_cl */
							&gpb 1 0 &pincfg_nobias>;  /* sa1_al */
				};

				pins_nemc_addr: nemc-addr {
					ingenic,pins = <&gpb 0 0 &pincfg_nobias    /* sa0_cl */
							&gpb 1 0 &pincfg_nobias    /* sa1_al */
							&gpb 2 0 &pincfg_nobias    /* sa2 */
							&gpb 3 0 &pincfg_nobias    /* sa3 */
							&gpb 4 0 &pincfg_nobias    /* sa4 */
							&gpb 5 0 &pincfg_nobias>;  /* sa5 */
				};

				pins_nemc_rd_we: nemc-rd-we {
					ingenic,pins = <&gpa 16 0 &pincfg_nobias   /* rd */
							&gpa 17 0 &pincfg_nobias>; /* we */
				};

				pins_nemc_frd_fwe: nemc-frd-fwe {
					ingenic,pins = <&gpa 18 0 &pincfg_nobias   /* rd */
							&gpa 19 0 &pincfg_nobias>; /* we */
				};

				pins_nemc_cs1: nemc-cs1 {
					ingenic,pins = <&gpa 21 0 &pincfg_nobias>; /* cs1 */
				};

				pins_nemc_cs6: nemc-cs6 {
					ingenic,pins = <&gpa 26 0 &pincfg_nobias>; /* cs6 */
				};
			};

			pinfunc_i2c0: i2c0 {
				pins_i2c0_data: i2c0-data{
					ingenic,pins = <&gpd  30 0 &pincfg_nobias  /* sda */
							&gpd  31 0 &pincfg_nobias>; /* sck */
				};
			};

			pinfunc_i2c1: i2c1 {
				pins_i2c1_data: i2c1-data{
					ingenic,pins = <&gpe  30 0 &pincfg_nobias  /* sda */
							&gpe  31 0 &pincfg_nobias>; /* sck */
				};
			};

			pinfunc_i2c2: i2c2 {
				pins_i2c2_data: i2c2-data{
					ingenic,pins = <&gpf  16 2 &pincfg_nobias  /* sda */
							&gpf  17 2 &pincfg_nobias>; /* sck */
				};
			};

			pinfunc_i2c3: i2c3 {
				pins_i2c3_data: i2c3-data{
					ingenic,pins = <&gpd  10 1 &pincfg_nobias  /* sda */
							&gpd  11 1 &pincfg_nobias>; /* sck */
				};
			};

			pinfunc_i2c4: i2c4 {
				pins_i2c4_data: i2c4-data-pe{
					ingenic,pins = <&gpe  12 1 &pincfg_nobias  /* sda */
							&gpe  13 1 &pincfg_nobias>; /* sck */
				};

				pins_i2c4_data_pf: i2c4-data-pf{
					ingenic,pins = <&gpf 25 1 &pincfg_nobias /* hdmi_sda */
							&gpf 24 1 &pincfg_nobias>; /* hdmi_sck */
				};
			};

			pinfunc_cim: cim {
				pins_cim: cim-pb {
					ingenic,pins = <&gpb   6 0 &pincfg_nobias
							&gpb   7 0 &pincfg_nobias
							&gpb   8 0 &pincfg_nobias
							&gpb   9 0 &pincfg_nobias
							&gpb  10 0 &pincfg_nobias
							&gpb  11 0 &pincfg_nobias
							&gpb  12 0 &pincfg_nobias
							&gpb  13 0 &pincfg_nobias
							&gpb  14 0 &pincfg_nobias
							&gpb  15 0 &pincfg_nobias
							&gpb  16 0 &pincfg_nobias
							&gpb  17 0 &pincfg_nobias>;
				};
			};
		};

		spi_gpio {
			compatible = "spi-gpio";
			#address-cells = <1>;
			#size-cells = <0>;
			num-chipselects = <2>;

			gpio-miso = <&gpe 14 0>;
			gpio-sck = <&gpe 15 0>;
			gpio-mosi = <&gpe 17 0>;
			cs-gpios = <&gpe 16 0
					&gpe 18 0>;

			spidev@0 {
				compatible = "spidev";
				reg = <0>;
				spi-max-frequency = <1000000>;
			};
		};

		uart0: serial@10030000 {
			compatible = "ingenic,jz4780-uart";
			reg = <0x10030000 0x100>;
			reg-shift = <2>;

			interrupt-parent = <&intc>;
			interrupts = <51>;

			clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
			clock-names = "baud", "module";
		};

		uart1: serial@10031000 {
			compatible = "ingenic,jz4780-uart";
			reg = <0x10031000 0x100>;
			reg-shift = <2>;

			interrupt-parent = <&intc>;
			interrupts = <50>;

			clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
			clock-names = "baud", "module";
		};

		uart2: serial@10032000 {
			compatible = "ingenic,jz4780-uart";
			reg = <0x10032000 0x100>;
			reg-shift = <2>;

			interrupt-parent = <&intc>;
			interrupts = <49>;

			clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
			clock-names = "baud", "module";
		};

		uart3: serial@10033000 {
			compatible = "ingenic,jz4780-uart";
			reg = <0x10033000 0x100>;
			reg-shift = <2>;

			interrupt-parent = <&intc>;
			interrupts = <48>;

			clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
			clock-names = "baud", "module";
		};

		uart4: serial@10034000 {
			compatible = "ingenic,jz4780-uart";
			reg = <0x10034000 0x100>;
			reg-shift = <2>;

			interrupt-parent = <&intc>;
			interrupts = <34>;

			clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
			clock-names = "baud", "module";
		};

		i2c0: i2c0@0x10050000 {
			compatible = "ingenic,jz4780-i2c";
			reg = <0x10050000 0x1000>;

			interrupt-parent = <&intc>;
			interrupts = <60>;

			clocks = <&cgu JZ4780_CLK_SMB0>;

			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c1@0x10051000 {
			compatible = "ingenic,jz4780-i2c";
			reg = <0x10051000 0x1000>;

			interrupt-parent = <&intc>;
			interrupts = <59>;

			clocks = <&cgu JZ4780_CLK_SMB1>;

			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c2@0x10052000 {
			compatible = "ingenic,jz4780-i2c";
			reg = <0x10052000 0x1000>;

			interrupt-parent = <&intc>;
			interrupts = <58>;

			clocks = <&cgu JZ4780_CLK_SMB2>;

			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c3: i2c3@0x10053000 {
			compatible = "ingenic,jz4780-i2c";
			reg = <0x10053000 0x1000>;

			interrupt-parent = <&intc>;
			interrupts = <57>;

			clocks = <&cgu JZ4780_CLK_SMB3>;

			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c4: i2c4@0x10054000 {
			compatible = "ingenic,jz4780-i2c";
			reg = <0x10054000 0x1000>;

			interrupt-parent = <&intc>;
			interrupts = <56>;

			clocks = <&cgu JZ4780_CLK_SMB4>;

			#address-cells = <1>;
			#size-cells = <0>;
		};

		lpcr: lcr@0x10000004 {
			compatible = "ingenic,jz4780-lcr";
			reg = <0x10000004 0x4>;

			regulators {
				vpu_power: VPU {
				};
				gpu_power: GPU {
				};
				gps_power: GPS {
				};
			};
		};

		adc@0x10070000 {
			compatible = "ingenic,jz4780-adc";
			reg = <0x10070000 0x30>;

			interrupt-parent = <&intc>;
			interrupts = <18>;

			clocks = <&cgu JZ4780_CLK_SADC>;
			clock-names = "adc";
		};
	};

	ahb2 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <>;


		lcd: jz4780-lcdk@0x13050000 {
			compatible = "ingenic,jz4780-lcd";
			reg = <0x13050000 0x1800>;

			clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
			clock-names = "lcd_clk", "lcd_pixclk";

			interrupt-parent = <&intc>;
			interrupts = <31>;

			hdmi = <&hdmi>;
			ddc = <&i2c4>;
		};

		cim: jz4780-cim@0x13060000 {
			compatible = "ingenic,jz4780-cim";
			reg = <0x13060000 0x68>;
			reg-shift = <2>;

			interrupt-parent = <&intc>;
			interrupts = <30>;

			pinctrl-names = "default";
			pinctrl-0 = <&pins_cim>;

			clocks = <&cgu JZ4780_CLK_CIM>, <&cgu JZ4780_CLK_CIMMCLK>;
			clock-names = "cim", "module";
		};

		hdmi: jz4780-hdmi3@0x10180000 {
			compatible = "synopsys,dwc-hdmi";
			reg = <0x10180000 0x8000>;
			reg-shift = <2>;

			clocks = <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_AHB0>;
			clock-names = "hdmi" , "ahb";

			clock-frequency = <27000000>;

			interrupt-parent = <&intc>;
			interrupts = <3>;

			ddc = <&i2c4>;
		};


		nemc: nemc@13410000 {
			compatible = "ingenic,jz4780-nemc";
			reg = <0x13410000 0x10000>;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <1 0 0x1b000000 0x1000000
			          2 0 0x1a000000 0x1000000
			          3 0 0x19000000 0x1000000
			          4 0 0x18000000 0x1000000
			          5 0 0x17000000 0x1000000
			          6 0 0x16000000 0x1000000>;

			clocks = <&cgu JZ4780_CLK_NEMC>;
		};

		efuse: efuse@134100D0 {
			compatible = "ingenic,jz4780-efuse";
			reg = <0x134100D0 0xFF>;

			clocks = <&cgu JZ4780_CLK_AHB2>;
			clock-names = "bus_clk";
		};

		dma: dma@13420000 {
			compatible = "ingenic,jz4780-dma";
			reg = <0x13420000 0x10000>;

			interrupt-parent = <&intc>;
			interrupts = <10>;

			clocks = <&cgu JZ4780_CLK_PDMA>;

			#dma-cells = <3>;
		};

		msc0: msc@13450000 {
			compatible = "ingenic,jz4780-mmc";
			reg = <0x13450000 0x1000>;

			interrupt-parent = <&intc>;
			interrupts = <37>;

			clocks = <&cgu JZ4780_CLK_MSC0>;
			clock-names = "mmc";

			cap-sd-highspeed;
			cap-mmc-highspeed;
			cap-sdio-irq;

			dmas = <&dma JZ4780_DMA_MSC0_TX JZ4780_DMA_MSC0_RX 0xffffffff>;
			dma-names = "rx-tx";
		};

		msc1: msc@13460000 {
			compatible = "ingenic,jz4780-mmc";
			reg = <0x13460000 0x1000>;

			status = "disabled";

			interrupt-parent = <&intc>;
			interrupts = <36>;

			clocks = <&cgu JZ4780_CLK_MSC1>;
			clock-names = "mmc";

			cap-sd-highspeed;
			cap-mmc-highspeed;
			cap-sdio-irq;

			dmas = <&dma JZ4780_DMA_MSC1_TX JZ4780_DMA_MSC1_RX 0xffffffff>;
			dma-names = "rx-tx";
		};

		ehci: jz4780-ehci@0x13490000 {
			compatible = "ingenic,jz4780-ehci";
			reg = <0x13490000 0x10000>;

			interrupt-parent = <&intc>;
			interrupts = <20>;

			clocks = <&cgu JZ4780_CLK_UHC>;
		};

		ohci: jz4780-ohci@0x134a0000 {
			compatible = "ingenic,jz4780-ohci";
			reg = <0x134a0000 0x10000>;

			interrupt-parent = <&intc>;
			interrupts = <5>;

			clocks = <&cgu JZ4780_CLK_UHC>;
			clock-names = "uhc";
		};

		bch: bch@134d0000 {
			compatible = "ingenic,jz4780-bch";
			reg = <0x134d0000 0x10000>;

			clocks = <&cgu JZ4780_CLK_BCH>;
		};

		otg: jz4780-otg@0x13500000 {
			compatible = "ingenic,jz4780-otg";
			reg = <0x13500000 0x40000>;

			interrupt-parent = <&intc>;
			interrupts = <21>;

			clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_OTG1>;
			clock-names = "otg_phy", "otg1";
		};
	};
};