From 032ac3f16bf323d2142f0bed529f877b411e9288 Mon Sep 17 00:00:00 2001
From: dumbbell <dumbbell@ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f>
Date: Sun, 9 Feb 2014 16:16:24 +0000
Subject: [PATCH] MFC r254848, r258930:

drm: Import drm_pcie_get_speed_cap_mask() in drm_pci.c

This comes with several PCI_VENDOR_ID_* defines which should go in a
more central place.


git-svn-id: svn://svn.freebsd.org/base/stable/9@261667 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f
---
 sys/dev/drm2/drmP.h    | 17 +++++++++++++
 sys/dev/drm2/drm_pci.c | 54 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/sys/dev/drm2/drmP.h b/sys/dev/drm2/drmP.h
index 325faa84a..637b07719 100644
--- a/sys/dev/drm2/drmP.h
+++ b/sys/dev/drm2/drmP.h
@@ -1415,5 +1415,22 @@ do {									\
 #define	EREMOTEIO	ENXIO
 #define	ERESTARTSYS	ERESTART
 
+#define	PCI_VENDOR_ID_APPLE		0x106b
+#define	PCI_VENDOR_ID_ASUSTEK		0x1043
+#define	PCI_VENDOR_ID_ATI		0x1002
+#define	PCI_VENDOR_ID_DELL		0x1028
+#define	PCI_VENDOR_ID_HP		0x103c
+#define	PCI_VENDOR_ID_IBM		0x1014
+#define	PCI_VENDOR_ID_INTEL		0x8086
+#define	PCI_VENDOR_ID_SERVERWORKS	0x1166
+#define	PCI_VENDOR_ID_SONY		0x104d
+#define	PCI_VENDOR_ID_VIA		0x1106
+
+#define DRM_PCIE_SPEED_25 1
+#define DRM_PCIE_SPEED_50 2
+#define DRM_PCIE_SPEED_80 4
+
+extern int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask);
+
 #endif /* __KERNEL__ */
 #endif /* _DRM_P_H_ */
diff --git a/sys/dev/drm2/drm_pci.c b/sys/dev/drm2/drm_pci.c
index 3d7a3cc7f..ac9d4e6be 100644
--- a/sys/dev/drm2/drm_pci.c
+++ b/sys/dev/drm2/drm_pci.c
@@ -123,3 +123,57 @@ drm_pci_free(struct drm_device *dev, drm_dma_handle_t *dmah)
 }
 
 /*@}*/
+
+int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *mask)
+{
+	device_t root;
+	int pos;
+	u32 lnkcap = 0, lnkcap2 = 0;
+
+	*mask = 0;
+	if (!drm_device_is_pcie(dev))
+		return -EINVAL;
+
+	root =
+	    device_get_parent( /* pcib             */
+	    device_get_parent( /* `-- pci          */
+	    device_get_parent( /*     `-- vgapci   */
+	    dev->device)));    /*         `-- drmn */
+
+	pos = 0;
+	pci_find_cap(root, PCIY_EXPRESS, &pos);
+	if (!pos)
+		return -EINVAL;
+
+	/* we've been informed via and serverworks don't make the cut */
+	if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
+	    pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
+		return -EINVAL;
+
+	lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
+	lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
+
+	lnkcap &= PCIEM_LINK_CAP_MAX_SPEED;
+	lnkcap2 &= 0xfe;
+
+#define	PCI_EXP_LNKCAP2_SLS_2_5GB 0x02	/* Supported Link Speed 2.5GT/s */
+#define	PCI_EXP_LNKCAP2_SLS_5_0GB 0x04	/* Supported Link Speed 5.0GT/s */
+#define	PCI_EXP_LNKCAP2_SLS_8_0GB 0x08	/* Supported Link Speed 8.0GT/s */
+
+	if (lnkcap2) { /* PCIE GEN 3.0 */
+		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
+			*mask |= DRM_PCIE_SPEED_25;
+		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
+			*mask |= DRM_PCIE_SPEED_50;
+		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
+			*mask |= DRM_PCIE_SPEED_80;
+	} else {
+		if (lnkcap & 1)
+			*mask |= DRM_PCIE_SPEED_25;
+		if (lnkcap & 2)
+			*mask |= DRM_PCIE_SPEED_50;
+	}
+
+	DRM_INFO("probing gen 2 caps for device %x:%x = %x/%x\n", pci_get_vendor(root), pci_get_device(root), lnkcap, lnkcap2);
+	return 0;
+}
-- 
2.45.0