From 2315c10644402294a7210d9212272320b1d920ae Mon Sep 17 00:00:00 2001 From: jhb Date: Mon, 22 Dec 2014 18:40:59 +0000 Subject: [PATCH] MFC 260557,271076,271077,271082,271083,271098: - Remove spaces from boot messages when we print the CPU ID/Family/Stepping - Move prototypes for various functions into out of C files and into . - Reduce diffs between i386 and amd64 initcpu.c and identcpu.c files. - Move blacklists of broken TSCs out of the printcpuinfo() function and into the TSC probe routine. - Merge the amd64 and i386 identcpu.c into a single x86 implementation. git-svn-id: svn://svn.freebsd.org/base/stable/10@276070 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f --- sys/amd64/amd64/identcpu.c | 923 -------------------------- sys/amd64/amd64/machdep.c | 4 - sys/amd64/include/md_var.h | 3 + sys/conf/files.amd64 | 2 +- sys/conf/files.i386 | 2 +- sys/conf/files.pc98 | 2 +- sys/i386/i386/initcpu.c | 47 +- sys/i386/i386/machdep.c | 8 - sys/i386/i386/trap.c | 2 +- sys/i386/include/md_var.h | 16 +- sys/pc98/pc98/machdep.c | 4 - sys/{i386/i386 => x86/x86}/identcpu.c | 767 +++++++++++++++------ sys/x86/x86/tsc.c | 33 + 13 files changed, 655 insertions(+), 1158 deletions(-) delete mode 100644 sys/amd64/amd64/identcpu.c rename sys/{i386/i386 => x86/x86}/identcpu.c (65%) diff --git a/sys/amd64/amd64/identcpu.c b/sys/amd64/amd64/identcpu.c deleted file mode 100644 index 74be82cfb..000000000 --- a/sys/amd64/amd64/identcpu.c +++ /dev/null @@ -1,923 +0,0 @@ -/*- - * Copyright (c) 1992 Terrence R. Lambert. - * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. - * Copyright (c) 1997 KATO Takenori. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_cpu.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* XXX - should be in header file: */ -void printcpuinfo(void); -void identify_cpu(void); -void earlysetcpuclass(void); -void panicifcpuunsupported(void); - -static u_int find_cpu_vendor_id(void); -static void print_AMD_info(void); -static void print_AMD_assoc(int i); -static void print_via_padlock_info(void); -static void print_vmx_info(void); - -int cpu_class; -char machine[] = "amd64"; - -#ifdef SCTL_MASK32 -extern int adaptive_machine_arch; -#endif - -static int -sysctl_hw_machine(SYSCTL_HANDLER_ARGS) -{ -#ifdef SCTL_MASK32 - static const char machine32[] = "i386"; -#endif - int error; - -#ifdef SCTL_MASK32 - if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) - error = SYSCTL_OUT(req, machine32, sizeof(machine32)); - else -#endif - error = SYSCTL_OUT(req, machine, sizeof(machine)); - return (error); - -} -SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, - NULL, 0, sysctl_hw_machine, "A", "Machine class"); - -static char cpu_model[128]; -SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, - cpu_model, 0, "Machine model"); - -static int hw_clockrate; -SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, - &hw_clockrate, 0, "CPU instruction clock rate"); - -static eventhandler_tag tsc_post_tag; - -static char cpu_brand[48]; - -static struct { - char *cpu_name; - int cpu_class; -} amd64_cpus[] = { - { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ - { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ -}; - -static struct { - char *vendor; - u_int vendor_id; -} cpu_vendors[] = { - { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ - { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ - { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ -}; - - -void -printcpuinfo(void) -{ - u_int regs[4], i; - char *brand; - - cpu_class = amd64_cpus[cpu].cpu_class; - printf("CPU: "); - strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); - - /* Check for extended CPUID information and a processor name. */ - if (cpu_exthigh >= 0x80000004) { - brand = cpu_brand; - for (i = 0x80000002; i < 0x80000005; i++) { - do_cpuid(i, regs); - memcpy(brand, regs, sizeof(regs)); - brand += sizeof(regs); - } - } - - switch (cpu_vendor_id) { - case CPU_VENDOR_INTEL: - /* Please make up your mind folks! */ - strcat(cpu_model, "EM64T"); - break; - case CPU_VENDOR_AMD: - /* - * Values taken from AMD Processor Recognition - * http://www.amd.com/K6/k6docs/pdf/20734g.pdf - * (also describes ``Features'' encodings. - */ - strcpy(cpu_model, "AMD "); - if ((cpu_id & 0xf00) == 0xf00) - strcat(cpu_model, "AMD64 Processor"); - else - strcat(cpu_model, "Unknown"); - break; - case CPU_VENDOR_CENTAUR: - strcpy(cpu_model, "VIA "); - if ((cpu_id & 0xff0) == 0x6f0) - strcat(cpu_model, "Nano Processor"); - else - strcat(cpu_model, "Unknown"); - break; - default: - strcat(cpu_model, "Unknown"); - break; - } - - /* - * Replace cpu_model with cpu_brand minus leading spaces if - * we have one. - */ - brand = cpu_brand; - while (*brand == ' ') - ++brand; - if (*brand != '\0') - strcpy(cpu_model, brand); - - printf("%s (", cpu_model); - switch(cpu_class) { - case CPUCLASS_K8: - if (tsc_freq != 0) { - hw_clockrate = (tsc_freq + 5000) / 1000000; - printf("%jd.%02d-MHz ", - (intmax_t)(tsc_freq + 4999) / 1000000, - (u_int)((tsc_freq + 4999) / 10000) % 100); - } - printf("K8"); - break; - default: - printf("Unknown"); /* will panic below... */ - } - printf("-class CPU)\n"); - if (*cpu_vendor) - printf(" Origin = \"%s\"", cpu_vendor); - if (cpu_id) - printf(" Id = 0x%x", cpu_id); - - if (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_CENTAUR) { - printf(" Family = 0x%x", CPUID_TO_FAMILY(cpu_id)); - printf(" Model = 0x%x", CPUID_TO_MODEL(cpu_id)); - printf(" Stepping = %u", cpu_id & CPUID_STEPPING); - - /* - * AMD CPUID Specification - * http://support.amd.com/us/Embedded_TechDocs/25481.pdf - * - * Intel Processor Identification and CPUID Instruction - * http://www.intel.com/assets/pdf/appnote/241618.pdf - */ - if (cpu_high > 0) { - - /* - * Here we should probably set up flags indicating - * whether or not various features are available. - * The interesting ones are probably VME, PSE, PAE, - * and PGE. The code already assumes without bothering - * to check that all CPUs >= Pentium have a TSC and - * MSRs. - */ - printf("\n Features=0x%b", cpu_feature, - "\020" - "\001FPU" /* Integral FPU */ - "\002VME" /* Extended VM86 mode support */ - "\003DE" /* Debugging Extensions (CR4.DE) */ - "\004PSE" /* 4MByte page tables */ - "\005TSC" /* Timestamp counter */ - "\006MSR" /* Machine specific registers */ - "\007PAE" /* Physical address extension */ - "\010MCE" /* Machine Check support */ - "\011CX8" /* CMPEXCH8 instruction */ - "\012APIC" /* SMP local APIC */ - "\013oldMTRR" /* Previous implementation of MTRR */ - "\014SEP" /* Fast System Call */ - "\015MTRR" /* Memory Type Range Registers */ - "\016PGE" /* PG_G (global bit) support */ - "\017MCA" /* Machine Check Architecture */ - "\020CMOV" /* CMOV instruction */ - "\021PAT" /* Page attributes table */ - "\022PSE36" /* 36 bit address space support */ - "\023PN" /* Processor Serial number */ - "\024CLFLUSH" /* Has the CLFLUSH instruction */ - "\025" - "\026DTS" /* Debug Trace Store */ - "\027ACPI" /* ACPI support */ - "\030MMX" /* MMX instructions */ - "\031FXSR" /* FXSAVE/FXRSTOR */ - "\032SSE" /* Streaming SIMD Extensions */ - "\033SSE2" /* Streaming SIMD Extensions #2 */ - "\034SS" /* Self snoop */ - "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ - "\036TM" /* Thermal Monitor clock slowdown */ - "\037IA64" /* CPU can execute IA64 instructions */ - "\040PBE" /* Pending Break Enable */ - ); - - if (cpu_feature2 != 0) { - printf("\n Features2=0x%b", cpu_feature2, - "\020" - "\001SSE3" /* SSE3 */ - "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ - "\003DTES64" /* 64-bit Debug Trace */ - "\004MON" /* MONITOR/MWAIT Instructions */ - "\005DS_CPL" /* CPL Qualified Debug Store */ - "\006VMX" /* Virtual Machine Extensions */ - "\007SMX" /* Safer Mode Extensions */ - "\010EST" /* Enhanced SpeedStep */ - "\011TM2" /* Thermal Monitor 2 */ - "\012SSSE3" /* SSSE3 */ - "\013CNXT-ID" /* L1 context ID available */ - "\014" - "\015FMA" /* Fused Multiply Add */ - "\016CX16" /* CMPXCHG16B Instruction */ - "\017xTPR" /* Send Task Priority Messages*/ - "\020PDCM" /* Perf/Debug Capability MSR */ - "\021" - "\022PCID" /* Process-context Identifiers*/ - "\023DCA" /* Direct Cache Access */ - "\024SSE4.1" /* SSE 4.1 */ - "\025SSE4.2" /* SSE 4.2 */ - "\026x2APIC" /* xAPIC Extensions */ - "\027MOVBE" /* MOVBE Instruction */ - "\030POPCNT" /* POPCNT Instruction */ - "\031TSCDLT" /* TSC-Deadline Timer */ - "\032AESNI" /* AES Crypto */ - "\033XSAVE" /* XSAVE/XRSTOR States */ - "\034OSXSAVE" /* OS-Enabled State Management*/ - "\035AVX" /* Advanced Vector Extensions */ - "\036F16C" /* Half-precision conversions */ - "\037RDRAND" /* RDRAND Instruction */ - "\040HV" /* Hypervisor */ - ); - } - - if (amd_feature != 0) { - printf("\n AMD Features=0x%b", amd_feature, - "\020" /* in hex */ - "\001" /* Same */ - "\002" /* Same */ - "\003" /* Same */ - "\004" /* Same */ - "\005" /* Same */ - "\006" /* Same */ - "\007" /* Same */ - "\010" /* Same */ - "\011" /* Same */ - "\012" /* Same */ - "\013" /* Undefined */ - "\014SYSCALL" /* Have SYSCALL/SYSRET */ - "\015" /* Same */ - "\016" /* Same */ - "\017" /* Same */ - "\020" /* Same */ - "\021" /* Same */ - "\022" /* Same */ - "\023" /* Reserved, unknown */ - "\024MP" /* Multiprocessor Capable */ - "\025NX" /* Has EFER.NXE, NX */ - "\026" /* Undefined */ - "\027MMX+" /* AMD MMX Extensions */ - "\030" /* Same */ - "\031" /* Same */ - "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ - "\033Page1GB" /* 1-GB large page support */ - "\034RDTSCP" /* RDTSCP */ - "\035" /* Undefined */ - "\036LM" /* 64 bit long mode */ - "\0373DNow!+" /* AMD 3DNow! Extensions */ - "\0403DNow!" /* AMD 3DNow! */ - ); - } - - if (amd_feature2 != 0) { - printf("\n AMD Features2=0x%b", amd_feature2, - "\020" - "\001LAHF" /* LAHF/SAHF in long mode */ - "\002CMP" /* CMP legacy */ - "\003SVM" /* Secure Virtual Mode */ - "\004ExtAPIC" /* Extended APIC register */ - "\005CR8" /* CR8 in legacy mode */ - "\006ABM" /* LZCNT instruction */ - "\007SSE4A" /* SSE4A */ - "\010MAS" /* Misaligned SSE mode */ - "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ - "\012OSVW" /* OS visible workaround */ - "\013IBS" /* Instruction based sampling */ - "\014XOP" /* XOP extended instructions */ - "\015SKINIT" /* SKINIT/STGI */ - "\016WDT" /* Watchdog timer */ - "\017" - "\020LWP" /* Lightweight Profiling */ - "\021FMA4" /* 4-operand FMA instructions */ - "\022TCE" /* Translation Cache Extension */ - "\023" - "\024NodeId" /* NodeId MSR support */ - "\025" - "\026TBM" /* Trailing Bit Manipulation */ - "\027Topology" /* Topology Extensions */ - "\030PCXC" /* Core perf count */ - "\031PNXC" /* NB perf count */ - "\032" - "\033DBE" /* Data Breakpoint extension */ - "\034PTSC" /* Performance TSC */ - "\035PL2I" /* L2I perf count */ - "\036" - "\037" - "\040" - ); - } - - if (cpu_stdext_feature != 0) { - printf("\n Structured Extended Features=0x%b", - cpu_stdext_feature, - "\020" - /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ - "\001FSGSBASE" - "\002TSCADJ" - /* Bit Manipulation Instructions */ - "\004BMI1" - /* Hardware Lock Elision */ - "\005HLE" - /* Advanced Vector Instructions 2 */ - "\006AVX2" - /* Supervisor Mode Execution Prot. */ - "\010SMEP" - /* Bit Manipulation Instructions */ - "\011BMI2" - "\012ERMS" - /* Invalidate Processor Context ID */ - "\013INVPCID" - /* Restricted Transactional Memory */ - "\014RTM" - /* Intel Memory Protection Extensions */ - "\017MPX" - /* AVX512 Foundation */ - "\021AVX512F" - /* Enhanced NRBG */ - "\023RDSEED" - /* ADCX + ADOX */ - "\024ADX" - /* Supervisor Mode Access Prevention */ - "\025SMAP" - "\030CLFLUSHOPT" - "\032PROCTRACE" - "\033AVX512PF" - "\034AVX512ER" - "\035AVX512CD" - "\036SHA" - ); - } - - if (via_feature_rng != 0 || via_feature_xcrypt != 0) - print_via_padlock_info(); - - if (cpu_feature2 & CPUID2_VMX) - print_vmx_info(); - - if ((cpu_feature & CPUID_HTT) && - cpu_vendor_id == CPU_VENDOR_AMD) - cpu_feature &= ~CPUID_HTT; - - /* - * If this CPU supports P-state invariant TSC then - * mention the capability. - */ - if (tsc_is_invariant) { - printf("\n TSC: P-state invariant"); - if (tsc_perf_stat) - printf(", performance statistics"); - } - - } - } - /* Avoid ugly blank lines: only print newline when we have to. */ - if (*cpu_vendor || cpu_id) - printf("\n"); - - if (!bootverbose) - return; - - if (cpu_vendor_id == CPU_VENDOR_AMD) - print_AMD_info(); -} - -void -panicifcpuunsupported(void) -{ - -#ifndef HAMMER -#error "You need to specify a cpu type" -#endif - /* - * Now that we have told the user what they have, - * let them know if that machine type isn't configured. - */ - switch (cpu_class) { - case CPUCLASS_X86: -#ifndef HAMMER - case CPUCLASS_K8: -#endif - panic("CPU class not configured"); - default: - break; - } -} - - -/* Update TSC freq with the value indicated by the caller. */ -static void -tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) -{ - - /* If there was an error during the transition, don't do anything. */ - if (status != 0) - return; - - /* Total setting for this level gives the new frequency in MHz. */ - hw_clockrate = level->total_set.freq; -} - -static void -hook_tsc_freq(void *arg __unused) -{ - - if (tsc_is_invariant) - return; - - tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, - tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); -} - -SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); - -/* - * Final stage of CPU identification. - */ -void -identify_cpu(void) -{ - u_int regs[4], cpu_stdext_disable; - - do_cpuid(0, regs); - cpu_high = regs[0]; - ((u_int *)&cpu_vendor)[0] = regs[1]; - ((u_int *)&cpu_vendor)[1] = regs[3]; - ((u_int *)&cpu_vendor)[2] = regs[2]; - cpu_vendor[12] = '\0'; - cpu_vendor_id = find_cpu_vendor_id(); - - do_cpuid(1, regs); - cpu_id = regs[0]; - cpu_procinfo = regs[1]; - cpu_feature = regs[3]; - cpu_feature2 = regs[2]; - - /* - * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID - * function number again if it is set from BIOS. It is necessary - * for probing correct CPU topology later. - * XXX This is only done on the BSP package. - */ - if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) { - uint64_t msr; - msr = rdmsr(MSR_IA32_MISC_ENABLE); - if ((msr & 0x400000ULL) != 0) { - wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); - do_cpuid(0, regs); - cpu_high = regs[0]; - } - } - - if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { - do_cpuid(5, regs); - cpu_mon_mwait_flags = regs[2]; - cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; - cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; - } - - if (cpu_high >= 7) { - cpuid_count(7, 0, regs); - cpu_stdext_feature = regs[1]; - - /* - * Some hypervisors fail to filter out unsupported - * extended features. For now, disable the - * extensions, activation of which requires setting a - * bit in CR4, and which VM monitors do not support. - */ - if (cpu_feature2 & CPUID2_HV) { - cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | - CPUID_STDEXT_SMEP; - } else - cpu_stdext_disable = 0; - TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); - cpu_stdext_feature &= ~cpu_stdext_disable; - } - - if (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_CENTAUR) { - do_cpuid(0x80000000, regs); - cpu_exthigh = regs[0]; - } - if (cpu_exthigh >= 0x80000001) { - do_cpuid(0x80000001, regs); - amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); - amd_feature2 = regs[2]; - } - if (cpu_exthigh >= 0x80000007) { - do_cpuid(0x80000007, regs); - amd_pminfo = regs[3]; - } - if (cpu_exthigh >= 0x80000008) { - do_cpuid(0x80000008, regs); - cpu_procinfo2 = regs[2]; - } - - /* XXX */ - cpu = CPU_CLAWHAMMER; -} - -static u_int -find_cpu_vendor_id(void) -{ - int i; - - for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) - if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) - return (cpu_vendors[i].vendor_id); - return (0); -} - -static void -print_AMD_assoc(int i) -{ - if (i == 255) - printf(", fully associative\n"); - else - printf(", %d-way associative\n", i); -} - -static void -print_AMD_l2_assoc(int i) -{ - switch (i & 0x0f) { - case 0: printf(", disabled/not present\n"); break; - case 1: printf(", direct mapped\n"); break; - case 2: printf(", 2-way associative\n"); break; - case 4: printf(", 4-way associative\n"); break; - case 6: printf(", 8-way associative\n"); break; - case 8: printf(", 16-way associative\n"); break; - case 15: printf(", fully associative\n"); break; - default: printf(", reserved configuration\n"); break; - } -} - -static void -print_AMD_info(void) -{ - u_int regs[4]; - - if (cpu_exthigh < 0x80000005) - return; - - do_cpuid(0x80000005, regs); - printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); - print_AMD_assoc(regs[0] >> 24); - - printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); - print_AMD_assoc((regs[0] >> 8) & 0xff); - - printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); - print_AMD_assoc(regs[1] >> 24); - - printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); - print_AMD_assoc((regs[1] >> 8) & 0xff); - - printf("L1 data cache: %d kbytes", regs[2] >> 24); - printf(", %d bytes/line", regs[2] & 0xff); - printf(", %d lines/tag", (regs[2] >> 8) & 0xff); - print_AMD_assoc((regs[2] >> 16) & 0xff); - - printf("L1 instruction cache: %d kbytes", regs[3] >> 24); - printf(", %d bytes/line", regs[3] & 0xff); - printf(", %d lines/tag", (regs[3] >> 8) & 0xff); - print_AMD_assoc((regs[3] >> 16) & 0xff); - - if (cpu_exthigh >= 0x80000006) { - do_cpuid(0x80000006, regs); - if ((regs[0] >> 16) != 0) { - printf("L2 2MB data TLB: %d entries", - (regs[0] >> 16) & 0xfff); - print_AMD_l2_assoc(regs[0] >> 28); - printf("L2 2MB instruction TLB: %d entries", - regs[0] & 0xfff); - print_AMD_l2_assoc((regs[0] >> 28) & 0xf); - } else { - printf("L2 2MB unified TLB: %d entries", - regs[0] & 0xfff); - print_AMD_l2_assoc((regs[0] >> 28) & 0xf); - } - if ((regs[1] >> 16) != 0) { - printf("L2 4KB data TLB: %d entries", - (regs[1] >> 16) & 0xfff); - print_AMD_l2_assoc(regs[1] >> 28); - - printf("L2 4KB instruction TLB: %d entries", - (regs[1] >> 16) & 0xfff); - print_AMD_l2_assoc((regs[1] >> 28) & 0xf); - } else { - printf("L2 4KB unified TLB: %d entries", - (regs[1] >> 16) & 0xfff); - print_AMD_l2_assoc((regs[1] >> 28) & 0xf); - } - printf("L2 unified cache: %d kbytes", regs[2] >> 16); - printf(", %d bytes/line", regs[2] & 0xff); - printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); - print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); - } - - /* - * Opteron Rev E shows a bug as in very rare occasions a read memory - * barrier is not performed as expected if it is followed by a - * non-atomic read-modify-write instruction. - * As long as that bug pops up very rarely (intensive machine usage - * on other operating systems generally generates one unexplainable - * crash any 2 months) and as long as a model specific fix would be - * impratical at this stage, print out a warning string if the broken - * model and family are identified. - */ - if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && - CPUID_TO_MODEL(cpu_id) <= 0x3f) - printf("WARNING: This architecture revision has known SMP " - "hardware bugs which may cause random instability\n"); -} - -static void -print_via_padlock_info(void) -{ - u_int regs[4]; - - do_cpuid(0xc0000001, regs); - printf("\n VIA Padlock Features=0x%b", regs[3], - "\020" - "\003RNG" /* RNG */ - "\007AES" /* ACE */ - "\011AES-CTR" /* ACE2 */ - "\013SHA1,SHA256" /* PHE */ - "\015RSA" /* PMM */ - ); -} - -static uint32_t -vmx_settable(uint64_t basic, int msr, int true_msr) -{ - uint64_t val; - - if (basic & (1UL << 55)) - val = rdmsr(true_msr); - else - val = rdmsr(msr); - - /* Just report the controls that can be set to 1. */ - return (val >> 32); -} - -static void -print_vmx_info(void) -{ - uint64_t basic, msr; - uint32_t entry, exit, mask, pin, proc, proc2; - int comma; - - printf("\n VT-x: "); - msr = rdmsr(MSR_IA32_FEATURE_CONTROL); - if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) - printf("(disabled in BIOS) "); - basic = rdmsr(MSR_VMX_BASIC); - pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, - MSR_VMX_TRUE_PINBASED_CTLS); - proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, - MSR_VMX_TRUE_PROCBASED_CTLS); - if (proc & PROCBASED_SECONDARY_CONTROLS) - proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, - MSR_VMX_PROCBASED_CTLS2); - else - proc2 = 0; - exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); - entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); - - if (!bootverbose) { - comma = 0; - if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && - entry & VM_ENTRY_LOAD_PAT) { - printf("%sPAT", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_HLT_EXITING) { - printf("%sHLT", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_MTF) { - printf("%sMTF", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_PAUSE_EXITING) { - printf("%sPAUSE", comma ? "," : ""); - comma = 1; - } - if (proc2 & PROCBASED2_ENABLE_EPT) { - printf("%sEPT", comma ? "," : ""); - comma = 1; - } - if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { - printf("%sUG", comma ? "," : ""); - comma = 1; - } - if (proc2 & PROCBASED2_ENABLE_VPID) { - printf("%sVPID", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_USE_TPR_SHADOW && - proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && - proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && - proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && - proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { - printf("%sVID", comma ? "," : ""); - comma = 1; - if (pin & PINBASED_POSTED_INTERRUPT) - printf(",PostIntr"); - } - return; - } - - mask = basic >> 32; - printf("Basic Features=0x%b", mask, - "\020" - "\02132PA" /* 32-bit physical addresses */ - "\022SMM" /* SMM dual-monitor */ - "\027INS/OUTS" /* VM-exit info for INS and OUTS */ - "\030TRUE" /* TRUE_CTLS MSRs */ - ); - printf("\n Pin-Based Controls=0x%b", pin, - "\020" - "\001ExtINT" /* External-interrupt exiting */ - "\004NMI" /* NMI exiting */ - "\006VNMI" /* Virtual NMIs */ - "\007PreTmr" /* Activate VMX-preemption timer */ - "\010PostIntr" /* Process posted interrupts */ - ); - printf("\n Primary Processor Controls=0x%b", proc, - "\020" - "\003INTWIN" /* Interrupt-window exiting */ - "\004TSCOff" /* Use TSC offsetting */ - "\010HLT" /* HLT exiting */ - "\012INVLPG" /* INVLPG exiting */ - "\013MWAIT" /* MWAIT exiting */ - "\014RDPMC" /* RDPMC exiting */ - "\015RDTSC" /* RDTSC exiting */ - "\020CR3-LD" /* CR3-load exiting */ - "\021CR3-ST" /* CR3-store exiting */ - "\024CR8-LD" /* CR8-load exiting */ - "\025CR8-ST" /* CR8-store exiting */ - "\026TPR" /* Use TPR shadow */ - "\027NMIWIN" /* NMI-window exiting */ - "\030MOV-DR" /* MOV-DR exiting */ - "\031IO" /* Unconditional I/O exiting */ - "\032IOmap" /* Use I/O bitmaps */ - "\034MTF" /* Monitor trap flag */ - "\035MSRmap" /* Use MSR bitmaps */ - "\036MONITOR" /* MONITOR exiting */ - "\037PAUSE" /* PAUSE exiting */ - ); - if (proc & PROCBASED_SECONDARY_CONTROLS) - printf("\n Secondary Processor Controls=0x%b", proc2, - "\020" - "\001APIC" /* Virtualize APIC accesses */ - "\002EPT" /* Enable EPT */ - "\003DT" /* Descriptor-table exiting */ - "\004RDTSCP" /* Enable RDTSCP */ - "\005x2APIC" /* Virtualize x2APIC mode */ - "\006VPID" /* Enable VPID */ - "\007WBINVD" /* WBINVD exiting */ - "\010UG" /* Unrestricted guest */ - "\011APIC-reg" /* APIC-register virtualization */ - "\012VID" /* Virtual-interrupt delivery */ - "\013PAUSE-loop" /* PAUSE-loop exiting */ - "\014RDRAND" /* RDRAND exiting */ - "\015INVPCID" /* Enable INVPCID */ - "\016VMFUNC" /* Enable VM functions */ - "\017VMCS" /* VMCS shadowing */ - "\020EPT#VE" /* EPT-violation #VE */ - "\021XSAVES" /* Enable XSAVES/XRSTORS */ - ); - printf("\n Exit Controls=0x%b", mask, - "\020" - "\003DR" /* Save debug controls */ - /* Ignore Host address-space size */ - "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ - "\020AckInt" /* Acknowledge interrupt on exit */ - "\023PAT-SV" /* Save MSR_PAT */ - "\024PAT-LD" /* Load MSR_PAT */ - "\025EFER-SV" /* Save MSR_EFER */ - "\026EFER-LD" /* Load MSR_EFER */ - "\027PTMR-SV" /* Save VMX-preemption timer value */ - ); - printf("\n Entry Controls=0x%b", mask, - "\020" - "\003DR" /* Save debug controls */ - /* Ignore IA-32e mode guest */ - /* Ignore Entry to SMM */ - /* Ignore Deactivate dual-monitor treatment */ - "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ - "\017PAT" /* Load MSR_PAT */ - "\020EFER" /* Load MSR_EFER */ - ); - if (proc & PROCBASED_SECONDARY_CONTROLS && - (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { - msr = rdmsr(MSR_VMX_EPT_VPID_CAP); - mask = msr; - printf("\n EPT Features=0x%b", mask, - "\020" - "\001XO" /* Execute-only translations */ - "\007PW4" /* Page-walk length of 4 */ - "\011UC" /* EPT paging-structure mem can be UC */ - "\017WB" /* EPT paging-structure mem can be WB */ - "\0212M" /* EPT PDE can map a 2-Mbyte page */ - "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ - "\025INVEPT" /* INVEPT is supported */ - "\026AD" /* Accessed and dirty flags for EPT */ - "\032single" /* INVEPT single-context type */ - "\033all" /* INVEPT all-context type */ - ); - mask = msr >> 32; - printf("\n VPID Features=0x%b", mask, - "\020" - "\001INVVPID" /* INVVPID is supported */ - "\011individual" /* INVVPID individual-address type */ - "\012single" /* INVVPID single-context type */ - "\013all" /* INVVPID all-context type */ - /* INVVPID single-context-retaining-globals type */ - "\014single-globals" - ); - } -} diff --git a/sys/amd64/amd64/machdep.c b/sys/amd64/amd64/machdep.c index bb4d99dd1..ac84d0e78 100644 --- a/sys/amd64/amd64/machdep.c +++ b/sys/amd64/amd64/machdep.c @@ -153,10 +153,6 @@ CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); extern u_int64_t hammer_time(u_int64_t, u_int64_t); -extern void printcpuinfo(void); /* XXX header file */ -extern void identify_cpu(void); -extern void panicifcpuunsupported(void); - #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) diff --git a/sys/amd64/include/md_var.h b/sys/amd64/include/md_var.h index 5ddfbbd0b..c7b89a6c6 100644 --- a/sys/amd64/include/md_var.h +++ b/sys/amd64/include/md_var.h @@ -105,14 +105,17 @@ void fsbase_load_fault(void) __asm(__STRING(fsbase_load_fault)); void gsbase_load_fault(void) __asm(__STRING(gsbase_load_fault)); void dump_add_page(vm_paddr_t); void dump_drop_page(vm_paddr_t); +void identify_cpu(void); void initializecpu(void); void initializecpucache(void); void fillw(int /*u_short*/ pat, void *base, size_t cnt); void fpstate_drop(struct thread *td); int is_physical_memory(vm_paddr_t addr); int isa_nmi(int cd); +void panicifcpuunsupported(void); void pagecopy(void *from, void *to); void pagezero(void *addr); +void printcpuinfo(void); void setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int ist); int user_dbreg_trap(void); void minidumpsys(struct dumperinfo *); diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64 index 4f7272d71..2c9430093 100644 --- a/sys/conf/files.amd64 +++ b/sys/conf/files.amd64 @@ -114,7 +114,6 @@ amd64/amd64/elf_machdep.c standard amd64/amd64/exception.S standard amd64/amd64/fpu.c standard amd64/amd64/gdb_machdep.c optional gdb -amd64/amd64/identcpu.c standard amd64/amd64/in_cksum.c optional inet | inet6 amd64/amd64/initcpu.c standard amd64/amd64/io.c optional io @@ -578,6 +577,7 @@ x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt +x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c standard x86/x86/legacy.c standard diff --git a/sys/conf/files.i386 b/sys/conf/files.i386 index d6cd35097..0ba06efb7 100644 --- a/sys/conf/files.i386 +++ b/sys/conf/files.i386 @@ -460,7 +460,6 @@ i386/xen/exception.s optional xen i386/i386/gdb_machdep.c optional gdb i386/i386/geode.c optional cpu_geode i386/i386/i686_mem.c optional mem -i386/i386/identcpu.c standard i386/i386/in_cksum.c optional inet | inet6 i386/i386/initcpu.c standard i386/i386/io.c optional io @@ -594,6 +593,7 @@ x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt +x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c optional apic x86/x86/legacy.c optional native diff --git a/sys/conf/files.pc98 b/sys/conf/files.pc98 index 509a04a5f..ee2ee16d0 100644 --- a/sys/conf/files.pc98 +++ b/sys/conf/files.pc98 @@ -143,7 +143,6 @@ i386/i386/elf_machdep.c standard i386/i386/exception.s standard i386/i386/gdb_machdep.c optional gdb i386/i386/i686_mem.c optional mem -i386/i386/identcpu.c standard i386/i386/in_cksum.c optional inet | inet6 i386/i386/initcpu.c standard i386/i386/io.c optional io @@ -251,6 +250,7 @@ x86/pci/pci_bus.c optional pci x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/dump_machdep.c standard +x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c optional apic x86/x86/legacy.c standard diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c index 71c57b258..f93ea13cb 100644 --- a/sys/i386/i386/initcpu.c +++ b/sys/i386/i386/initcpu.c @@ -48,12 +48,6 @@ __FBSDID("$FreeBSD$"); #define CPU_ENABLE_SSE #endif -#if defined(I586_CPU) && defined(CPU_WT_ALLOC) -void enable_K5_wt_alloc(void); -void enable_K6_wt_alloc(void); -void enable_K6_2_wt_alloc(void); -#endif - #ifdef I486_CPU static void init_5x86(void); static void init_bluelightning(void); @@ -81,36 +75,37 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, */ static int hw_clflush_disable = -1; -/* Must *NOT* be BSS or locore will bzero these after setting them */ -int cpu = 0; /* Are we 386, 386sx, 486, etc? */ -u_int cpu_feature = 0; /* Feature flags */ -u_int cpu_feature2 = 0; /* Feature flags */ -u_int amd_feature = 0; /* AMD feature flags */ -u_int amd_feature2 = 0; /* AMD feature flags */ -u_int amd_pminfo = 0; /* AMD advanced power management info */ -u_int via_feature_rng = 0; /* VIA RNG features */ -u_int via_feature_xcrypt = 0; /* VIA ACE features */ -u_int cpu_high = 0; /* Highest arg to CPUID */ -u_int cpu_id = 0; /* Stepping ID */ -u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */ -u_int cpu_procinfo2 = 0; /* Multicore info */ -char cpu_vendor[20] = ""; /* CPU Origin code */ -u_int cpu_vendor_id = 0; /* CPU vendor ID */ +int cpu; /* Are we 386, 386sx, 486, etc? */ +u_int cpu_feature; /* Feature flags */ +u_int cpu_feature2; /* Feature flags */ +u_int amd_feature; /* AMD feature flags */ +u_int amd_feature2; /* AMD feature flags */ +u_int amd_pminfo; /* AMD advanced power management info */ +u_int via_feature_rng; /* VIA RNG features */ +u_int via_feature_xcrypt; /* VIA ACE features */ +u_int cpu_high; /* Highest arg to CPUID */ +u_int cpu_exthigh; /* Highest arg to extended CPUID */ +u_int cpu_id; /* Stepping ID */ +u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ +u_int cpu_procinfo2; /* Multicore info */ +char cpu_vendor[20]; /* CPU Origin code */ +u_int cpu_vendor_id; /* CPU vendor ID */ +#ifdef CPU_ENABLE_SSE +u_int cpu_fxsr; /* SSE enabled */ +u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ +#endif u_int cpu_clflush_line_size = 32; +u_int cpu_stdext_feature; u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ +u_int cyrix_did; /* Device ID of Cyrix CPU */ SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, &via_feature_rng, 0, "VIA RNG feature available in CPU"); SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU"); -#ifdef CPU_ENABLE_SSE -u_int cpu_fxsr; /* SSE enabled */ -u_int cpu_mxcsr_mask; /* valid bits in mxcsr */ -#endif - #ifdef I486_CPU /* * IBM Blue Lightning diff --git a/sys/i386/i386/machdep.c b/sys/i386/i386/machdep.c index 1e1889ae4..1b540755c 100644 --- a/sys/i386/i386/machdep.c +++ b/sys/i386/i386/machdep.c @@ -182,10 +182,6 @@ CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); extern void init386(int first); extern void dblfault_handler(void); -extern void printcpuinfo(void); /* XXX header file */ -extern void finishidentcpu(void); -extern void panicifcpuunsupported(void); - #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) @@ -1664,10 +1660,6 @@ struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ struct region_descriptor r_gdt, r_idt; /* table descriptors */ struct mtx dt_lock; /* lock for GDT and LDT */ -#if defined(I586_CPU) && !defined(NO_F00F_HACK) -extern int has_f00f_bug; -#endif - static struct i386tss dblfault_tss; static char dblfault_stack[PAGE_SIZE]; diff --git a/sys/i386/i386/trap.c b/sys/i386/i386/trap.c index 152addfec..9dd0f09fd 100644 --- a/sys/i386/i386/trap.c +++ b/sys/i386/i386/trap.c @@ -154,7 +154,7 @@ static char *trap_msg[] = { }; #if defined(I586_CPU) && !defined(NO_F00F_HACK) -extern int has_f00f_bug; +int has_f00f_bug = 0; /* Initialized so that it can be patched. */ #endif #ifdef KDB diff --git a/sys/i386/include/md_var.h b/sys/i386/include/md_var.h index 9c8a693f0..c2c8c6c64 100644 --- a/sys/i386/include/md_var.h +++ b/sys/i386/include/md_var.h @@ -48,6 +48,7 @@ extern u_int amd_pminfo; extern u_int via_feature_rng; extern u_int via_feature_xcrypt; extern u_int cpu_clflush_line_size; +extern u_int cpu_stdext_feature; extern u_int cpu_fxsr; extern u_int cpu_high; extern u_int cpu_id; @@ -56,10 +57,13 @@ extern u_int cpu_procinfo; extern u_int cpu_procinfo2; extern char cpu_vendor[]; extern u_int cpu_vendor_id; -extern u_int cyrix_did; extern u_int cpu_mon_mwait_flags; extern u_int cpu_mon_min_size; extern u_int cpu_mon_max_size; +extern u_int cyrix_did; +#if defined(I586_CPU) && !defined(NO_F00F_HACK) +extern int has_f00f_bug; +#endif extern char kstack[]; extern char sigcode[]; extern int szsigcode; @@ -94,15 +98,23 @@ void doreti_popl_fs(void) __asm(__STRING(doreti_popl_fs)); void doreti_popl_fs_fault(void) __asm(__STRING(doreti_popl_fs_fault)); void dump_add_page(vm_paddr_t); void dump_drop_page(vm_paddr_t); -void initializecpu(void); +void finishidentcpu(void); +#if defined(I586_CPU) && defined(CPU_WT_ALLOC) +void enable_K5_wt_alloc(void); +void enable_K6_wt_alloc(void); +void enable_K6_2_wt_alloc(void); +#endif void enable_sse(void); void fillw(int /*u_short*/ pat, void *base, size_t cnt); +void initializecpu(void); void i686_pagezero(void *addr); void sse2_pagezero(void *addr); void init_AMD_Elan_sc520(void); int is_physical_memory(vm_paddr_t addr); int isa_nmi(int cd); vm_paddr_t kvtop(void *addr); +void panicifcpuunsupported(void); +void printcpuinfo(void); void setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int selec); int user_dbreg_trap(void); void minidumpsys(struct dumperinfo *); diff --git a/sys/pc98/pc98/machdep.c b/sys/pc98/pc98/machdep.c index a5b799dc7..f17bc1987 100644 --- a/sys/pc98/pc98/machdep.c +++ b/sys/pc98/pc98/machdep.c @@ -151,10 +151,6 @@ CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); extern void init386(int first); extern void dblfault_handler(void); -extern void printcpuinfo(void); /* XXX header file */ -extern void finishidentcpu(void); -extern void panicifcpuunsupported(void); - #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) diff --git a/sys/i386/i386/identcpu.c b/sys/x86/x86/identcpu.c similarity index 65% rename from sys/i386/i386/identcpu.c rename to sys/x86/x86/identcpu.c index 1af3ac25c..e33ab8a2f 100644 --- a/sys/i386/i386/identcpu.c +++ b/sys/x86/x86/identcpu.c @@ -55,55 +55,75 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include #include +#include +#include + +#ifdef __i386__ #define IDENTBLUE_CYRIX486 0 #define IDENTBLUE_IBMCPU 1 #define IDENTBLUE_CYRIXM2 2 -/* XXX - should be in header file: */ -void printcpuinfo(void); -void finishidentcpu(void); -void earlysetcpuclass(void); -#if defined(I586_CPU) && defined(CPU_WT_ALLOC) -void enable_K5_wt_alloc(void); -void enable_K6_wt_alloc(void); -void enable_K6_2_wt_alloc(void); -#endif -void panicifcpuunsupported(void); - static void identifycyrix(void); -static void init_exthigh(void); +static void print_transmeta_info(void); +#endif static u_int find_cpu_vendor_id(void); static void print_AMD_info(void); static void print_INTEL_info(void); static void print_INTEL_TLB(u_int data); -static void print_AMD_assoc(int i); -static void print_transmeta_info(void); static void print_via_padlock_info(void); +static void print_vmx_info(void); int cpu_class; -u_int cpu_exthigh; /* Highest arg to extended CPUID */ -u_int cyrix_did; /* Device ID of Cyrix CPU */ char machine[] = MACHINE; -SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, + +#ifdef __amd64__ +#ifdef SCTL_MASK32 +extern int adaptive_machine_arch; +#endif + +static int +sysctl_hw_machine(SYSCTL_HANDLER_ARGS) +{ +#ifdef SCTL_MASK32 + static const char machine32[] = "i386"; +#endif + int error; + +#ifdef SCTL_MASK32 + if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) + error = SYSCTL_OUT(req, machine32, sizeof(machine32)); + else +#endif + error = SYSCTL_OUT(req, machine, sizeof(machine)); + return (error); + +} +SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, + NULL, 0, sysctl_hw_machine, "A", "Machine class"); +#else +SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class"); +#endif static char cpu_model[128]; -SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, +SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model"); static int hw_clockrate; -SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, +SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, &hw_clockrate, 0, "CPU instruction clock rate"); static eventhandler_tag tsc_post_tag; static char cpu_brand[48]; +#ifdef __i386__ #define MAX_BRAND_INDEX 8 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { @@ -117,11 +137,13 @@ static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { NULL, "Intel Pentium 4" }; +#endif static struct { char *cpu_name; int cpu_class; -} i386_cpus[] = { +} cpus[] = { +#ifdef __i386__ { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ { "i386DX", CPUCLASS_386 }, /* CPU_386 */ @@ -139,6 +161,10 @@ static struct { { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ +#else + { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ + { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ +#endif }; static struct { @@ -148,6 +174,7 @@ static struct { { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ +#ifdef __i386__ { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ @@ -159,33 +186,8 @@ static struct { /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, #endif -}; - -#if defined(I586_CPU) && !defined(NO_F00F_HACK) -int has_f00f_bug = 0; /* Initialized so that it can be patched. */ #endif - -static void -init_exthigh(void) -{ - static int done = 0; - u_int regs[4]; - - if (done == 0) { - if (cpu_high > 0 && - (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_TRANSMETA || - cpu_vendor_id == CPU_VENDOR_CENTAUR || - cpu_vendor_id == CPU_VENDOR_NSC)) { - do_cpuid(0x80000000, regs); - if (regs[0] >= 0x80000000) - cpu_exthigh = regs[0]; - } - - done = 1; - } -} +}; void printcpuinfo(void) @@ -193,12 +195,11 @@ printcpuinfo(void) u_int regs[4], i; char *brand; - cpu_class = i386_cpus[cpu].cpu_class; + cpu_class = cpus[cpu].cpu_class; printf("CPU: "); - strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model)); + strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); /* Check for extended CPUID information and a processor name. */ - init_exthigh(); if (cpu_exthigh >= 0x80000004) { brand = cpu_brand; for (i = 0x80000002; i < 0x80000005; i++) { @@ -208,7 +209,9 @@ printcpuinfo(void) } } - if (cpu_vendor_id == CPU_VENDOR_INTEL) { + switch (cpu_vendor_id) { + case CPU_VENDOR_INTEL: +#ifdef __i386__ if ((cpu_id & 0xf00) > 0x300) { u_int brand_index; @@ -341,13 +344,19 @@ printcpuinfo(void) cpu_brandtable[brand_index]); } } - } else if (cpu_vendor_id == CPU_VENDOR_AMD) { +#else + /* Please make up your mind folks! */ + strcat(cpu_model, "EM64T"); +#endif + break; + case CPU_VENDOR_AMD: /* * Values taken from AMD Processor Recognition * http://www.amd.com/K6/k6docs/pdf/20734g.pdf * (also describes ``Features'' encodings. */ strcpy(cpu_model, "AMD "); +#ifdef __i386__ switch (cpu_id & 0xFF0) { case 0x410: strcat(cpu_model, "Standard Am486DX"); @@ -372,7 +381,6 @@ printcpuinfo(void) break; case 0x500: strcat(cpu_model, "K5 model 0"); - tsc_freq = 0; break; case 0x510: strcat(cpu_model, "K5 model 1"); @@ -421,7 +429,15 @@ printcpuinfo(void) enable_K6_wt_alloc(); } #endif - } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { +#else + if ((cpu_id & 0xf00) == 0xf00) + strcat(cpu_model, "AMD64 Processor"); + else + strcat(cpu_model, "Unknown"); +#endif + break; +#ifdef __i386__ + case CPU_VENDOR_CYRIX: strcpy(cpu_model, "Cyrix "); switch (cpu_id & 0xff0) { case 0x440: @@ -557,7 +573,8 @@ printcpuinfo(void) } break; } - } else if (cpu_vendor_id == CPU_VENDOR_RISE) { + break; + case CPU_VENDOR_RISE: strcpy(cpu_model, "Rise "); switch (cpu_id & 0xff0) { case 0x500: /* 6401 and 6441 (Kirin) */ @@ -567,17 +584,13 @@ printcpuinfo(void) default: strcat(cpu_model, "Unknown"); } - } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { + break; +#endif + case CPU_VENDOR_CENTAUR: +#ifdef __i386__ switch (cpu_id & 0xff0) { case 0x540: strcpy(cpu_model, "IDT WinChip C6"); - /* - * http://www.centtech.com/c6_data_sheet.pdf - * - * I-12 RDTSC may return incoherent values in EDX:EAX - * I-13 RDTSC hangs when certain event counters are used - */ - tsc_freq = 0; break; case 0x580: strcpy(cpu_model, "IDT WinChip 2"); @@ -610,20 +623,33 @@ printcpuinfo(void) default: strcpy(cpu_model, "VIA/IDT Unknown"); } - } else if (cpu_vendor_id == CPU_VENDOR_IBM) { +#else + strcpy(cpu_model, "VIA "); + if ((cpu_id & 0xff0) == 0x6f0) + strcat(cpu_model, "Nano Processor"); + else + strcat(cpu_model, "Unknown"); +#endif + break; +#ifdef __i386__ + case CPU_VENDOR_IBM: strcpy(cpu_model, "Blue Lightning CPU"); - } else if (cpu_vendor_id == CPU_VENDOR_NSC) { + break; + case CPU_VENDOR_NSC: switch (cpu_id & 0xff0) { case 0x540: strcpy(cpu_model, "Geode SC1100"); cpu = CPU_GEODE1100; - if ((cpu_id & CPUID_STEPPING) == 0) - tsc_freq = 0; break; default: strcpy(cpu_model, "Geode/NSC unknown"); break; } + break; +#endif + default: + strcat(cpu_model, "Unknown"); + break; } /* @@ -637,7 +663,14 @@ printcpuinfo(void) strcpy(cpu_model, brand); printf("%s (", cpu_model); + if (tsc_freq != 0) { + hw_clockrate = (tsc_freq + 5000) / 1000000; + printf("%jd.%02d-MHz ", + (intmax_t)(tsc_freq + 4999) / 1000000, + (u_int)((tsc_freq + 4999) / 10000) % 100); + } switch(cpu_class) { +#ifdef __i386__ case CPUCLASS_286: printf("286"); break; @@ -651,48 +684,46 @@ printcpuinfo(void) #endif #if defined(I586_CPU) case CPUCLASS_586: - if (tsc_freq != 0) { - hw_clockrate = (tsc_freq + 5000) / 1000000; - printf("%jd.%02d-MHz ", - (intmax_t)(tsc_freq + 4999) / 1000000, - (u_int)((tsc_freq + 4999) / 10000) % 100); - } printf("586"); break; #endif #if defined(I686_CPU) case CPUCLASS_686: - if (tsc_freq != 0) { - hw_clockrate = (tsc_freq + 5000) / 1000000; - printf("%jd.%02d-MHz ", - (intmax_t)(tsc_freq + 4999) / 1000000, - (u_int)((tsc_freq + 4999) / 10000) % 100); - } printf("686"); break; +#endif +#else + case CPUCLASS_K8: + printf("K8"); + break; #endif default: printf("Unknown"); /* will panic below... */ } printf("-class CPU)\n"); - if(*cpu_vendor) - printf(" Origin = \"%s\"",cpu_vendor); - if(cpu_id) - printf(" Id = 0x%x", cpu_id); + if (*cpu_vendor) + printf(" Origin=\"%s\"", cpu_vendor); + if (cpu_id) + printf(" Id=0x%x", cpu_id); if (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_CENTAUR || +#ifdef __i386__ cpu_vendor_id == CPU_VENDOR_TRANSMETA || cpu_vendor_id == CPU_VENDOR_RISE || - cpu_vendor_id == CPU_VENDOR_CENTAUR || cpu_vendor_id == CPU_VENDOR_NSC || - (cpu_vendor_id == CPU_VENDOR_CYRIX && - ((cpu_id & 0xf00) > 0x500))) { - printf(" Family = 0x%x", CPUID_TO_FAMILY(cpu_id)); - printf(" Model = 0x%x", CPUID_TO_MODEL(cpu_id)); - printf(" Stepping = %u", cpu_id & CPUID_STEPPING); + (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || +#endif + 0) { + printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); + printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); + printf(" Stepping=%u", cpu_id & CPUID_STEPPING); +#ifdef __i386__ if (cpu_vendor_id == CPU_VENDOR_CYRIX) printf("\n DIR=0x%04x", cyrix_did); +#endif + /* * AMD CPUID Specification * http://support.amd.com/us/Embedded_TechDocs/25481.pdf @@ -860,9 +891,53 @@ printcpuinfo(void) ); } + if (cpu_stdext_feature != 0) { + printf("\n Structured Extended Features=0x%b", + cpu_stdext_feature, + "\020" + /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ + "\001FSGSBASE" + "\002TSCADJ" + /* Bit Manipulation Instructions */ + "\004BMI1" + /* Hardware Lock Elision */ + "\005HLE" + /* Advanced Vector Instructions 2 */ + "\006AVX2" + /* Supervisor Mode Execution Prot. */ + "\010SMEP" + /* Bit Manipulation Instructions */ + "\011BMI2" + "\012ERMS" + /* Invalidate Processor Context ID */ + "\013INVPCID" + /* Restricted Transactional Memory */ + "\014RTM" + /* Intel Memory Protection Extensions */ + "\017MPX" + /* AVX512 Foundation */ + "\021AVX512F" + /* Enhanced NRBG */ + "\023RDSEED" + /* ADCX + ADOX */ + "\024ADX" + /* Supervisor Mode Access Prevention */ + "\025SMAP" + "\030CLFLUSHOPT" + "\032PROCTRACE" + "\033AVX512PF" + "\034AVX512ER" + "\035AVX512CD" + "\036SHA" + ); + } + if (via_feature_rng != 0 || via_feature_xcrypt != 0) print_via_padlock_info(); + if (cpu_feature2 & CPUID2_VMX) + print_vmx_info(); + if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_AMD) cpu_feature &= ~CPUID_HTT; @@ -878,6 +953,7 @@ printcpuinfo(void) } } +#ifdef __i386__ } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { printf(" DIR=0x%04x", cyrix_did); printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); @@ -885,6 +961,7 @@ printcpuinfo(void) #ifndef CYRIX_CACHE_REALLY_WORKS if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) printf("\n CPU cache: write-through mode"); +#endif #endif } @@ -899,25 +976,34 @@ printcpuinfo(void) print_AMD_info(); else if (cpu_vendor_id == CPU_VENDOR_INTEL) print_INTEL_info(); +#ifdef __i386__ else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) print_transmeta_info(); +#endif } void panicifcpuunsupported(void) { +#ifdef __i386__ #if !defined(lint) #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) #error This kernel is not configured for one of the supported CPUs #endif #else /* lint */ #endif /* lint */ +#else /* __amd64__ */ +#ifndef HAMMER +#error "You need to specify a cpu type" +#endif +#endif /* * Now that we have told the user what they have, * let them know if that machine type isn't configured. */ switch (cpu_class) { +#ifdef __i386__ case CPUCLASS_286: /* a 286 should not make it this far, anyway */ case CPUCLASS_386: #if !defined(I486_CPU) @@ -928,6 +1014,12 @@ panicifcpuunsupported(void) #endif #if !defined(I686_CPU) case CPUCLASS_686: +#endif +#else /* __amd64__ */ + case CPUCLASS_X86: +#ifndef HAMMER + case CPUCLASS_K8: +#endif #endif panic("CPU class not configured"); default: @@ -935,7 +1027,7 @@ panicifcpuunsupported(void) } } - +#ifdef __i386__ static volatile u_int trap_by_rdmsr; /* @@ -1064,6 +1156,7 @@ identifycyrix(void) intr_restore(saveintr); } +#endif /* Update TSC freq with the value indicated by the caller. */ static void @@ -1092,14 +1185,35 @@ hook_tsc_freq(void *arg __unused) SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); /* - * Final stage of CPU identification. -- Should I check TI? + * Final stage of CPU identification. */ +#ifdef __i386__ void finishidentcpu(void) +#else +void +identify_cpu(void) +#endif { - int isblue = 0; - u_char ccr3; - u_int regs[4]; + u_int regs[4], cpu_stdext_disable; +#ifdef __i386__ + u_char ccr3; +#endif + +#ifdef __amd64__ + do_cpuid(0, regs); + cpu_high = regs[0]; + ((u_int *)&cpu_vendor)[0] = regs[1]; + ((u_int *)&cpu_vendor)[1] = regs[3]; + ((u_int *)&cpu_vendor)[2] = regs[2]; + cpu_vendor[12] = '\0'; + + do_cpuid(1, regs); + cpu_id = regs[0]; + cpu_procinfo = regs[1]; + cpu_feature = regs[3]; + cpu_feature2 = regs[2]; +#endif cpu_vendor_id = find_cpu_vendor_id(); @@ -1128,38 +1242,67 @@ finishidentcpu(void) cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; } - /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ + if (cpu_high >= 7) { + cpuid_count(7, 0, regs); + cpu_stdext_feature = regs[1]; + + /* + * Some hypervisors fail to filter out unsupported + * extended features. For now, disable the + * extensions, activation of which requires setting a + * bit in CR4, and which VM monitors do not support. + */ + if (cpu_feature2 & CPUID2_HV) { + cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | + CPUID_STDEXT_SMEP; + } else + cpu_stdext_disable = 0; + TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); + cpu_stdext_feature &= ~cpu_stdext_disable; + } + +#ifdef __i386__ + if (cpu_high > 0 && + (cpu_vendor_id == CPU_VENDOR_INTEL || + cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_TRANSMETA || + cpu_vendor_id == CPU_VENDOR_CENTAUR || + cpu_vendor_id == CPU_VENDOR_NSC)) { + do_cpuid(0x80000000, regs); + if (regs[0] >= 0x80000000) + cpu_exthigh = regs[0]; + } +#else if (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD) { - init_exthigh(); - if (cpu_exthigh >= 0x80000001) { - do_cpuid(0x80000001, regs); - amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); - amd_feature2 = regs[2]; - } - if (cpu_exthigh >= 0x80000007) { - do_cpuid(0x80000007, regs); - amd_pminfo = regs[3]; - } - if (cpu_exthigh >= 0x80000008) { - do_cpuid(0x80000008, regs); - cpu_procinfo2 = regs[2]; - } - } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { - init_exthigh(); - if (cpu_exthigh >= 0x80000001) { - do_cpuid(0x80000001, regs); - amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); - } - } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { + cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_CENTAUR) { + do_cpuid(0x80000000, regs); + cpu_exthigh = regs[0]; + } +#endif + if (cpu_exthigh >= 0x80000001) { + do_cpuid(0x80000001, regs); + amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); + amd_feature2 = regs[2]; + } + if (cpu_exthigh >= 0x80000007) { + do_cpuid(0x80000007, regs); + amd_pminfo = regs[3]; + } + if (cpu_exthigh >= 0x80000008) { + do_cpuid(0x80000008, regs); + cpu_procinfo2 = regs[2]; + } + +#ifdef __i386__ + if (cpu_vendor_id == CPU_VENDOR_CYRIX) { if (cpu == CPU_486) { /* * These conditions are equivalent to: * - CPU does not support cpuid instruction. * - Cyrix/IBM CPU is detected. */ - isblue = identblue(); - if (isblue == IDENTBLUE_IBMCPU) { + if (identblue() == IDENTBLUE_IBMCPU) { strcpy(cpu_vendor, "IBM"); cpu_vendor_id = CPU_VENDOR_IBM; cpu = CPU_BLUE; @@ -1232,14 +1375,17 @@ finishidentcpu(void) * cpu_vendor null string and puts CPU_486 into the * cpu. */ - isblue = identblue(); - if (isblue == IDENTBLUE_IBMCPU) { + if (identblue() == IDENTBLUE_IBMCPU) { strcpy(cpu_vendor, "IBM"); cpu_vendor_id = CPU_VENDOR_IBM; cpu = CPU_BLUE; return; } } +#else + /* XXX */ + cpu = CPU_CLAWHAMMER; +#endif } static u_int @@ -1262,35 +1408,88 @@ print_AMD_assoc(int i) printf(", %d-way associative\n", i); } +static void +print_AMD_l2_assoc(int i) +{ + switch (i & 0x0f) { + case 0: printf(", disabled/not present\n"); break; + case 1: printf(", direct mapped\n"); break; + case 2: printf(", 2-way associative\n"); break; + case 4: printf(", 4-way associative\n"); break; + case 6: printf(", 8-way associative\n"); break; + case 8: printf(", 16-way associative\n"); break; + case 15: printf(", fully associative\n"); break; + default: printf(", reserved configuration\n"); break; + } +} + static void print_AMD_info(void) { - quad_t amd_whcr; +#ifdef __i386__ + uint64_t amd_whcr; +#endif + u_int regs[4]; if (cpu_exthigh >= 0x80000005) { - u_int regs[4]; - do_cpuid(0x80000005, regs); - printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff); + printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); + print_AMD_assoc(regs[0] >> 24); + + printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); + print_AMD_assoc((regs[0] >> 8) & 0xff); + + printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); print_AMD_assoc(regs[1] >> 24); - printf("Instruction TLB: %d entries", regs[1] & 0xff); + + printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); print_AMD_assoc((regs[1] >> 8) & 0xff); + printf("L1 data cache: %d kbytes", regs[2] >> 24); printf(", %d bytes/line", regs[2] & 0xff); printf(", %d lines/tag", (regs[2] >> 8) & 0xff); print_AMD_assoc((regs[2] >> 16) & 0xff); + printf("L1 instruction cache: %d kbytes", regs[3] >> 24); printf(", %d bytes/line", regs[3] & 0xff); printf(", %d lines/tag", (regs[3] >> 8) & 0xff); print_AMD_assoc((regs[3] >> 16) & 0xff); - if (cpu_exthigh >= 0x80000006) { /* K6-III only */ - do_cpuid(0x80000006, regs); - printf("L2 internal cache: %d kbytes", regs[2] >> 16); - printf(", %d bytes/line", regs[2] & 0xff); - printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); - print_AMD_assoc((regs[2] >> 12) & 0x0f); + } + + if (cpu_exthigh >= 0x80000006) { + do_cpuid(0x80000006, regs); + if ((regs[0] >> 16) != 0) { + printf("L2 2MB data TLB: %d entries", + (regs[0] >> 16) & 0xfff); + print_AMD_l2_assoc(regs[0] >> 28); + printf("L2 2MB instruction TLB: %d entries", + regs[0] & 0xfff); + print_AMD_l2_assoc((regs[0] >> 28) & 0xf); + } else { + printf("L2 2MB unified TLB: %d entries", + regs[0] & 0xfff); + print_AMD_l2_assoc((regs[0] >> 28) & 0xf); + } + if ((regs[1] >> 16) != 0) { + printf("L2 4KB data TLB: %d entries", + (regs[1] >> 16) & 0xfff); + print_AMD_l2_assoc(regs[1] >> 28); + + printf("L2 4KB instruction TLB: %d entries", + (regs[1] >> 16) & 0xfff); + print_AMD_l2_assoc((regs[1] >> 28) & 0xf); + } else { + printf("L2 4KB unified TLB: %d entries", + (regs[1] >> 16) & 0xfff); + print_AMD_l2_assoc((regs[1] >> 28) & 0xf); } + printf("L2 unified cache: %d kbytes", regs[2] >> 16); + printf(", %d bytes/line", regs[2] & 0xff); + printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); + print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); } + +#ifdef __i386__ if (((cpu_id & 0xf00) == 0x500) && (((cpu_id & 0x0f0) > 0x80) || (((cpu_id & 0x0f0) == 0x80) @@ -1320,7 +1519,7 @@ print_AMD_info(void) (amd_whcr & 0x0100) ? "Enable" : "Disable"); } } - +#endif /* * Opteron Rev E shows a bug as in very rare occasions a read memory * barrier is not performed as expected if it is followed by a @@ -1370,11 +1569,9 @@ print_INTEL_info(void) nway = 1 << (nwaycode / 2); else nway = 0; - printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line", + printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); } - - printf("\n"); } static void @@ -1386,164 +1583,165 @@ print_INTEL_TLB(u_int data) default: break; case 0x1: - printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries"); + printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); break; case 0x2: - printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries"); + printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); break; case 0x3: - printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries"); + printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); break; case 0x4: - printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries"); + printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); break; case 0x6: - printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size"); + printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); break; case 0x8: - printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size"); + printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); break; case 0xa: - printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size"); + printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); break; case 0xc: - printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size"); + printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); break; case 0x22: - printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size"); + printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); break; case 0x23: - printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); + printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x25: - printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size"); + printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x29: - printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size"); + printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x2c: - printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size"); + printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); break; case 0x30: - printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size"); + printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); break; case 0x39: - printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size"); + printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); break; case 0x3b: - printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size"); + printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); break; case 0x3c: - printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size"); + printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); break; case 0x41: - printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size"); + printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); break; case 0x42: - printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size"); + printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); break; case 0x43: - printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size"); + printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); break; case 0x44: - printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size"); + printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); break; case 0x45: - printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size"); + printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); break; case 0x46: - printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size"); + printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); break; case 0x47: - printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size"); + printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); break; case 0x50: - printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries"); + printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); break; case 0x51: - printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries"); + printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); break; case 0x52: - printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries"); + printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); break; case 0x5b: - printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries"); + printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); break; case 0x5c: - printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries"); + printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); break; case 0x5d: - printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries"); + printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); break; case 0x60: - printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size"); + printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x66: - printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size"); + printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); break; case 0x67: - printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size"); + printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); break; case 0x68: - printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size"); + printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); break; case 0x70: - printf("\nTrace cache: 12K-uops, 8-way set associative"); + printf("Trace cache: 12K-uops, 8-way set associative\n"); break; case 0x71: - printf("\nTrace cache: 16K-uops, 8-way set associative"); + printf("Trace cache: 16K-uops, 8-way set associative\n"); break; case 0x72: - printf("\nTrace cache: 32K-uops, 8-way set associative"); + printf("Trace cache: 32K-uops, 8-way set associative\n"); break; case 0x78: - printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size"); + printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); break; case 0x79: - printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size"); + printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x7a: - printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size"); + printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x7b: - printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size"); + printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x7c: - printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); + printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); break; case 0x7d: - printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size"); + printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); break; case 0x7f: - printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size"); + printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); break; case 0x82: - printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size"); + printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); break; case 0x83: - printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size"); + printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); break; case 0x84: - printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size"); + printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); break; case 0x85: - printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size"); + printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); break; case 0x86: - printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size"); + printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); break; case 0x87: - printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size"); + printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); break; case 0xb0: - printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries"); + printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); break; case 0xb3: - printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries"); + printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); break; } } +#ifdef __i386__ static void print_transmeta_info(void) { @@ -1578,6 +1776,7 @@ print_transmeta_info(void) printf(" %s\n", info); } } +#endif static void print_via_padlock_info(void) @@ -1594,3 +1793,197 @@ print_via_padlock_info(void) "\015RSA" /* PMM */ ); } + +static uint32_t +vmx_settable(uint64_t basic, int msr, int true_msr) +{ + uint64_t val; + + if (basic & (1ULL << 55)) + val = rdmsr(true_msr); + else + val = rdmsr(msr); + + /* Just report the controls that can be set to 1. */ + return (val >> 32); +} + +static void +print_vmx_info(void) +{ + uint64_t basic, msr; + uint32_t entry, exit, mask, pin, proc, proc2; + int comma; + + printf("\n VT-x: "); + msr = rdmsr(MSR_IA32_FEATURE_CONTROL); + if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) + printf("(disabled in BIOS) "); + basic = rdmsr(MSR_VMX_BASIC); + pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, + MSR_VMX_TRUE_PINBASED_CTLS); + proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, + MSR_VMX_TRUE_PROCBASED_CTLS); + if (proc & PROCBASED_SECONDARY_CONTROLS) + proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, + MSR_VMX_PROCBASED_CTLS2); + else + proc2 = 0; + exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); + entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); + + if (!bootverbose) { + comma = 0; + if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && + entry & VM_ENTRY_LOAD_PAT) { + printf("%sPAT", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_HLT_EXITING) { + printf("%sHLT", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_MTF) { + printf("%sMTF", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_PAUSE_EXITING) { + printf("%sPAUSE", comma ? "," : ""); + comma = 1; + } + if (proc2 & PROCBASED2_ENABLE_EPT) { + printf("%sEPT", comma ? "," : ""); + comma = 1; + } + if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { + printf("%sUG", comma ? "," : ""); + comma = 1; + } + if (proc2 & PROCBASED2_ENABLE_VPID) { + printf("%sVPID", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_USE_TPR_SHADOW && + proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && + proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && + proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && + proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { + printf("%sVID", comma ? "," : ""); + comma = 1; + if (pin & PINBASED_POSTED_INTERRUPT) + printf(",PostIntr"); + } + return; + } + + mask = basic >> 32; + printf("Basic Features=0x%b", mask, + "\020" + "\02132PA" /* 32-bit physical addresses */ + "\022SMM" /* SMM dual-monitor */ + "\027INS/OUTS" /* VM-exit info for INS and OUTS */ + "\030TRUE" /* TRUE_CTLS MSRs */ + ); + printf("\n Pin-Based Controls=0x%b", pin, + "\020" + "\001ExtINT" /* External-interrupt exiting */ + "\004NMI" /* NMI exiting */ + "\006VNMI" /* Virtual NMIs */ + "\007PreTmr" /* Activate VMX-preemption timer */ + "\010PostIntr" /* Process posted interrupts */ + ); + printf("\n Primary Processor Controls=0x%b", proc, + "\020" + "\003INTWIN" /* Interrupt-window exiting */ + "\004TSCOff" /* Use TSC offsetting */ + "\010HLT" /* HLT exiting */ + "\012INVLPG" /* INVLPG exiting */ + "\013MWAIT" /* MWAIT exiting */ + "\014RDPMC" /* RDPMC exiting */ + "\015RDTSC" /* RDTSC exiting */ + "\020CR3-LD" /* CR3-load exiting */ + "\021CR3-ST" /* CR3-store exiting */ + "\024CR8-LD" /* CR8-load exiting */ + "\025CR8-ST" /* CR8-store exiting */ + "\026TPR" /* Use TPR shadow */ + "\027NMIWIN" /* NMI-window exiting */ + "\030MOV-DR" /* MOV-DR exiting */ + "\031IO" /* Unconditional I/O exiting */ + "\032IOmap" /* Use I/O bitmaps */ + "\034MTF" /* Monitor trap flag */ + "\035MSRmap" /* Use MSR bitmaps */ + "\036MONITOR" /* MONITOR exiting */ + "\037PAUSE" /* PAUSE exiting */ + ); + if (proc & PROCBASED_SECONDARY_CONTROLS) + printf("\n Secondary Processor Controls=0x%b", proc2, + "\020" + "\001APIC" /* Virtualize APIC accesses */ + "\002EPT" /* Enable EPT */ + "\003DT" /* Descriptor-table exiting */ + "\004RDTSCP" /* Enable RDTSCP */ + "\005x2APIC" /* Virtualize x2APIC mode */ + "\006VPID" /* Enable VPID */ + "\007WBINVD" /* WBINVD exiting */ + "\010UG" /* Unrestricted guest */ + "\011APIC-reg" /* APIC-register virtualization */ + "\012VID" /* Virtual-interrupt delivery */ + "\013PAUSE-loop" /* PAUSE-loop exiting */ + "\014RDRAND" /* RDRAND exiting */ + "\015INVPCID" /* Enable INVPCID */ + "\016VMFUNC" /* Enable VM functions */ + "\017VMCS" /* VMCS shadowing */ + "\020EPT#VE" /* EPT-violation #VE */ + "\021XSAVES" /* Enable XSAVES/XRSTORS */ + ); + printf("\n Exit Controls=0x%b", mask, + "\020" + "\003DR" /* Save debug controls */ + /* Ignore Host address-space size */ + "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ + "\020AckInt" /* Acknowledge interrupt on exit */ + "\023PAT-SV" /* Save MSR_PAT */ + "\024PAT-LD" /* Load MSR_PAT */ + "\025EFER-SV" /* Save MSR_EFER */ + "\026EFER-LD" /* Load MSR_EFER */ + "\027PTMR-SV" /* Save VMX-preemption timer value */ + ); + printf("\n Entry Controls=0x%b", mask, + "\020" + "\003DR" /* Save debug controls */ + /* Ignore IA-32e mode guest */ + /* Ignore Entry to SMM */ + /* Ignore Deactivate dual-monitor treatment */ + "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ + "\017PAT" /* Load MSR_PAT */ + "\020EFER" /* Load MSR_EFER */ + ); + if (proc & PROCBASED_SECONDARY_CONTROLS && + (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { + msr = rdmsr(MSR_VMX_EPT_VPID_CAP); + mask = msr; + printf("\n EPT Features=0x%b", mask, + "\020" + "\001XO" /* Execute-only translations */ + "\007PW4" /* Page-walk length of 4 */ + "\011UC" /* EPT paging-structure mem can be UC */ + "\017WB" /* EPT paging-structure mem can be WB */ + "\0212M" /* EPT PDE can map a 2-Mbyte page */ + "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ + "\025INVEPT" /* INVEPT is supported */ + "\026AD" /* Accessed and dirty flags for EPT */ + "\032single" /* INVEPT single-context type */ + "\033all" /* INVEPT all-context type */ + ); + mask = msr >> 32; + printf("\n VPID Features=0x%b", mask, + "\020" + "\001INVVPID" /* INVVPID is supported */ + "\011individual" /* INVVPID individual-address type */ + "\012single" /* INVVPID single-context type */ + "\013all" /* INVVPID all-context type */ + /* INVVPID single-context-retaining-globals type */ + "\014single-globals" + ); + } +} diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.c index 2a6c81d78..b80e0e849 100644 --- a/sys/x86/x86/tsc.c +++ b/sys/x86/x86/tsc.c @@ -330,6 +330,39 @@ init_TSC(void) if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) return; +#ifdef __i386__ + /* The TSC is known to be broken on certain CPUs. */ + switch (cpu_vendor_id) { + case CPU_VENDOR_AMD: + switch (cpu_id & 0xFF0) { + case 0x500: + /* K5 Model 0 */ + return; + } + break; + case CPU_VENDOR_CENTAUR: + switch (cpu_id & 0xff0) { + case 0x540: + /* + * http://www.centtech.com/c6_data_sheet.pdf + * + * I-12 RDTSC may return incoherent values in EDX:EAX + * I-13 RDTSC hangs when certain event counters are used + */ + return; + } + break; + case CPU_VENDOR_NSC: + switch (cpu_id & 0xff0) { + case 0x540: + if ((cpu_id & CPUID_STEPPING) == 0) + return; + break; + } + break; + } +#endif + probe_tsc_freq(); /* -- 2.45.0