From 24184023992f6fe57ab68050f11e5095d4dedd14 Mon Sep 17 00:00:00 2001
From: Adrian Chadd <adrian@FreeBSD.org>
Date: Tue, 15 Oct 2013 01:35:48 +0000
Subject: [PATCH] Add new features - an MDIO clock, WMAC reset, GMAC reset and
 ethernet switch reset/initialise functions.

The AR934x and QC955x SoCs both have a configurable MDIO base clock.
The others have the MDIO clock use the same clock as the system
reference clock, whatever that may be.

Tested:

* AR9344 SoC

TODO:

* mips24k - AR933x would be fine for now, just to ensure that things
  are sane.
---
 sys/mips/atheros/ar71xx_chip.c   |  3 ++-
 sys/mips/atheros/ar71xx_cpudef.h | 26 ++++++++++++++++++++++++++
 sys/mips/atheros/ar724x_chip.c   |  2 +-
 sys/mips/atheros/ar91xx_chip.c   |  2 +-
 4 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/sys/mips/atheros/ar71xx_chip.c b/sys/mips/atheros/ar71xx_chip.c
index db7920f6b25..2fdf376db17 100644
--- a/sys/mips/atheros/ar71xx_chip.c
+++ b/sys/mips/atheros/ar71xx_chip.c
@@ -81,6 +81,7 @@ uint32_t u_ar71xx_ddr_freq;
 uint32_t u_ar71xx_uart_freq;
 uint32_t u_ar71xx_wdt_freq;
 uint32_t u_ar71xx_refclk;
+uint32_t u_ar71xx_mdio_freq;
 
 static void
 ar71xx_chip_detect_mem_size(void)
@@ -94,7 +95,7 @@ ar71xx_chip_detect_sys_frequency(void)
 	uint32_t freq;
 	uint32_t div;
 
-	u_ar71xx_refclk = AR71XX_BASE_FREQ;
+	u_ar71xx_mdio_freq = u_ar71xx_refclk = AR71XX_BASE_FREQ;
 
 	pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
 
diff --git a/sys/mips/atheros/ar71xx_cpudef.h b/sys/mips/atheros/ar71xx_cpudef.h
index a30157c2a0a..9a1133bd2e5 100644
--- a/sys/mips/atheros/ar71xx_cpudef.h
+++ b/sys/mips/atheros/ar71xx_cpudef.h
@@ -57,6 +57,12 @@ struct ar71xx_cpu_def {
 	 * each chip.
 	 */
 	void (* ar71xx_chip_init_usb_peripheral) (void);
+
+	void (* ar71xx_chip_reset_ethernet_switch) (void);
+
+	void (* ar71xx_chip_reset_wmac) (void);
+
+	void (* ar71xx_chip_init_gmac) (void);
 };
 
 extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
@@ -111,6 +117,24 @@ static inline void ar71xx_init_usb_peripheral(void)
 	ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
 }
 
+static inline void ar71xx_reset_ethernet_switch(void)
+{
+	if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch)
+		ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch();
+}
+
+static inline void ar71xx_reset_wmac(void)
+{
+	if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac)
+		ar71xx_cpu_ops->ar71xx_chip_reset_wmac();
+}
+
+static inline void ar71xx_init_gmac(void)
+{
+	if (ar71xx_cpu_ops->ar71xx_chip_init_gmac)
+		ar71xx_cpu_ops->ar71xx_chip_init_gmac();
+}
+
 static inline void ar71xx_device_ddr_flush_ip2(void)
 {
 	ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2();
@@ -123,6 +147,7 @@ extern uint32_t u_ar71xx_ahb_freq;
 extern uint32_t u_ar71xx_ddr_freq;
 extern uint32_t u_ar71xx_uart_freq;
 extern uint32_t u_ar71xx_wdt_freq;
+extern uint32_t u_ar71xx_mdio_freq;
 
 static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
 static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
@@ -130,5 +155,6 @@ static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
 static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
 static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
 static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
+static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; }
 
 #endif
diff --git a/sys/mips/atheros/ar724x_chip.c b/sys/mips/atheros/ar724x_chip.c
index c06eca63cd2..3a8d332ae51 100644
--- a/sys/mips/atheros/ar724x_chip.c
+++ b/sys/mips/atheros/ar724x_chip.c
@@ -73,7 +73,7 @@ ar724x_chip_detect_sys_frequency(void)
 	uint32_t freq;
 	uint32_t div;
 
-	u_ar71xx_refclk = AR724X_BASE_FREQ;
+	u_ar71xx_mdio_freq = u_ar71xx_refclk = AR724X_BASE_FREQ;
 
 	pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
 
diff --git a/sys/mips/atheros/ar91xx_chip.c b/sys/mips/atheros/ar91xx_chip.c
index a4174b47363..4fb77f7730b 100644
--- a/sys/mips/atheros/ar91xx_chip.c
+++ b/sys/mips/atheros/ar91xx_chip.c
@@ -71,7 +71,7 @@ ar91xx_chip_detect_sys_frequency(void)
 	uint32_t freq;
 	uint32_t div;
 
-	u_ar71xx_refclk = AR91XX_BASE_FREQ;
+	u_ar71xx_mdio_freq = u_ar71xx_refclk = AR91XX_BASE_FREQ;
 
 	pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
 
-- 
2.45.2