From 2425e5de5775eeaf6acb17c38944251ecfd0e2e4 Mon Sep 17 00:00:00 2001
From: cem <cem@FreeBSD.org>
Date: Thu, 17 Jan 2019 19:44:47 +0000
Subject: [PATCH] Add definitions for AMD Spectre/Meltdown CPUID information

No functional change, aside from printing recognized bits in CPU
identification.

The bits are documented in 111006-B "Indirect Branch Control Extension"[1] and
124441 "Speculative Store Bypass Disable."[2]

Notably missing (left as future work):
  * Integration with hw.spec_store_bypass_disable and hw_ssb_active flag,
    which are currently Intel-specific
  * Integration with hw_ibrs_active global flag, which are currently
    Intel-specific
  * SSB_NO integration in hw_ssb_recalculate()
  * Bhyve integration (PR 235010)

[1]:
https://developer.amd.com/wp-content/resources/111006-B_AMD64TechnologyIndirectBranchControlExtenstion_WP_7-18Update_FNL.pdf

[2]:
https://developer.amd.com/wp-content/resources/124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

PR:		235010 (related, but does not fix)
MFC after:	a week
---
 sys/x86/include/specialreg.h | 15 +++++++++++++++
 sys/x86/x86/identcpu.c       | 25 +++++++++++++++++++++++--
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
index 81f7b058606..2ccffee6ddf 100644
--- a/sys/x86/include/specialreg.h
+++ b/sys/x86/include/specialreg.h
@@ -374,6 +374,17 @@
 #define	AMDFEID_CLZERO		0x00000001
 #define	AMDFEID_IRPERF		0x00000002
 #define	AMDFEID_XSAVEERPTR	0x00000004
+#define	AMDFEID_IBPB		0x00001000
+#define	AMDFEID_IBRS		0x00004000
+#define	AMDFEID_STIBP		0x00008000
+/* The below are only defined if the corresponding base feature above exists. */
+#define	AMDFEID_IBRS_ALWAYSON	0x00010000
+#define	AMDFEID_STIBP_ALWAYSON	0x00020000
+#define	AMDFEID_PREFER_IBRS	0x00040000
+#define	AMDFEID_SSBD		0x01000000
+/* SSBD via MSRC001_011F instead of MSR 0x48: */
+#define	AMDFEID_VIRT_SSBD	0x02000000
+#define	AMDFEID_SSB_NO		0x04000000
 
 /*
  * AMD extended function 8000_0008h ecx info
@@ -719,6 +730,10 @@
 /*
  * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
  * document 336996-001 Speculative Execution Side Channel Mitigations.
+ *
+ * AMD uses the same MSRs and bit definitions, as described in 111006-B
+ * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass
+ * Disable."
  */
 /* MSR IA32_SPEC_CTRL */
 #define	IA32_SPEC_CTRL_IBRS	0x00000001
diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c
index 8668235da52..ec408c88b38 100644
--- a/sys/x86/x86/identcpu.c
+++ b/sys/x86/x86/identcpu.c
@@ -1021,13 +1021,34 @@ printcpuinfo(void)
 			}
 
 			if (amd_extended_feature_extensions != 0) {
+				u_int amd_fe_masked;
+
+				amd_fe_masked = amd_extended_feature_extensions;
+				if ((amd_fe_masked & AMDFEID_IBRS) == 0)
+					amd_fe_masked &=
+					    ~(AMDFEID_IBRS_ALWAYSON |
+						AMDFEID_PREFER_IBRS);
+				if ((amd_fe_masked & AMDFEID_STIBP) == 0)
+					amd_fe_masked &=
+					    ~AMDFEID_STIBP_ALWAYSON;
+
 				printf("\n  "
 				    "AMD Extended Feature Extensions ID EBX="
-				    "0x%b", amd_extended_feature_extensions,
+				    "0x%b", amd_fe_masked,
 				    "\020"
 				    "\001CLZERO"
 				    "\002IRPerf"
-				    "\003XSaveErPtr");
+				    "\003XSaveErPtr"
+				    "\015IBPB"
+				    "\017IBRS"
+				    "\020STIBP"
+				    "\021IBRS_ALWAYSON"
+				    "\022STIBP_ALWAYSON"
+				    "\023PREFER_IBRS"
+				    "\031SSBD"
+				    "\032VIRT_SSBD"
+				    "\033SSB_NO"
+				    );
 			}
 
 			if (via_feature_rng != 0 || via_feature_xcrypt != 0)
-- 
2.45.0