From 2ff45c79addf0fdfbfacc265a1821cd5c0c226ea Mon Sep 17 00:00:00 2001
From: julian <julian@ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f>
Date: Fri, 7 Oct 2016 19:28:45 +0000
Subject: [PATCH] MFH: r259647

 o Remove assertions on ipa_version as sometimes the version detection
   using cpuid can be quirky (this is the case of VMWare without the
   vPMC support) but fail to probe hwpmc.
 o Apply the fix for XEON family of processors as established by
   315338-020 document (bug AJ85).

 Sponsored by:	EMC / Isilon storage division
 Reviewed by:	fabient
MFC courtesy of panzura.


git-svn-id: svn://svn.freebsd.org/base/stable/10@306824 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f
---
 sys/dev/hwpmc/hwpmc_core.c  | 20 +++++++-------------
 sys/dev/hwpmc/hwpmc_core.h  |  3 ++-
 sys/dev/hwpmc/hwpmc_intel.c | 16 ++++++++++++----
 3 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c
index f85c6d440..d9e6a7ffa 100644
--- a/sys/dev/hwpmc/hwpmc_core.c
+++ b/sys/dev/hwpmc/hwpmc_core.c
@@ -2723,35 +2723,33 @@ core2_intr(int cpu, struct trapframe *tf)
 }
 
 int
-pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
+pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override)
 {
 	int cpuid[CORE_CPUID_REQUEST_SIZE];
 	int ipa_version, flags, nflags;
 
 	do_cpuid(CORE_CPUID_REQUEST, cpuid);
 
-	ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
+	ipa_version = (version_override > 0) ? version_override :
+	    cpuid[CORE_CPUID_EAX] & 0xFF;
+	core_cputype = md->pmd_cputype;
 
 	PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
-	    md->pmd_cputype, maxcpu, ipa_version);
+	    core_cputype, maxcpu, ipa_version);
 
-	if (ipa_version < 1 || ipa_version > 3) {
+	if (ipa_version < 1 || ipa_version > 3 ||
+	    (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) {
 		/* Unknown PMC architecture. */
 		printf("hwpc_core: unknown PMC architecture: %d\n",
 		    ipa_version);
 		return (EPROGMISMATCH);
 	}
 
-	core_cputype = md->pmd_cputype;
-
 	core_pmcmask = 0;
 
 	/*
 	 * Initialize programmable counters.
 	 */
-	KASSERT(ipa_version >= 1,
-	    ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
-
 	core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
 	core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
 
@@ -2766,10 +2764,6 @@ pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
 	 * Initialize fixed function counters, if present.
 	 */
 	if (core_cputype != PMC_CPU_INTEL_CORE) {
-		KASSERT(ipa_version >= 2,
-		    ("[core,%d] ipa_version %d too small", __LINE__,
-			ipa_version));
-
 		core_iaf_ri = core_iap_npmc;
 		core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
 		core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
diff --git a/sys/dev/hwpmc/hwpmc_core.h b/sys/dev/hwpmc/hwpmc_core.h
index fc774b849..63b6d02d3 100644
--- a/sys/dev/hwpmc/hwpmc_core.h
+++ b/sys/dev/hwpmc/hwpmc_core.h
@@ -175,7 +175,8 @@ struct pmc_md_iap_pmc {
  * Prototypes.
  */
 
-int	pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu);
+int	pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu,
+	    int _version_override);
 void	pmc_core_finalize(struct pmc_mdep *_md);
 
 int	pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width);
diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index 1018d9988..b90975d3b 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -78,7 +78,7 @@ pmc_intel_initialize(void)
 {
 	struct pmc_mdep *pmc_mdep;
 	enum pmc_cputype cputype;
-	int error, model, nclasses, ncpus;
+	int error, model, nclasses, ncpus, stepping, verov;
 
 	KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
 	    ("[intel,%d] Initializing non-intel processor", __LINE__));
@@ -88,7 +88,9 @@ pmc_intel_initialize(void)
 	cputype = -1;
 	nclasses = 2;
 	error = 0;
+	verov = 0;
 	model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
+	stepping = cpu_id & 0xF;
 
 	switch (cpu_id & 0xF00) {
 #if	defined(__i386__)
@@ -119,8 +121,14 @@ pmc_intel_initialize(void)
 			cputype = PMC_CPU_INTEL_CORE;
 			break;
 		case 0xF:
-			cputype = PMC_CPU_INTEL_CORE2;
-			nclasses = 3;
+			/* Per Intel document 315338-020. */
+			if (stepping == 0x7) {
+				cputype = PMC_CPU_INTEL_CORE;
+				verov = 1;
+			} else {
+				cputype = PMC_CPU_INTEL_CORE2;
+				nclasses = 3;
+			}
 			break;
 		case 0x17:
 			cputype = PMC_CPU_INTEL_CORE2EXTREME;
@@ -232,7 +240,7 @@ pmc_intel_initialize(void)
 	case PMC_CPU_INTEL_IVYBRIDGE_XEON:
 	case PMC_CPU_INTEL_HASWELL:
 	case PMC_CPU_INTEL_HASWELL_XEON:
-		error = pmc_core_initialize(pmc_mdep, ncpus);
+		error = pmc_core_initialize(pmc_mdep, ncpus, verov);
 		break;
 
 		/*
-- 
2.45.0