From 552c5506283d37430d9f3eb28e927b198fbea4f5 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Sun, 27 Apr 2014 23:31:42 +0000 Subject: [PATCH] Do a read-after-write to ensure the interrupt register update is flushed to the hardware. The QCA HAL has a comment noting that if this isn't done, modifications to AR_IMR_S2 before AR_IMR is flushed may produce spurious interrupts. Obtained from: QCA --- sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c b/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c index 631ca2fca2e..32ce2ed5b07 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c @@ -337,6 +337,9 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) /* Write the new IMR and store off our SW copy. */ HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); OS_REG_WRITE(ah, AR_IMR, mask); + /* Flush write */ + (void) OS_REG_READ(ah, AR_IMR); + mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | -- 2.45.2