From 68f8dc2950baa33c02d7736ea6e268549115c8b3 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Thu, 15 Dec 2011 12:14:15 +0000 Subject: [PATCH] ARM pmap fixes: - Write Buffers have to be drained after write to Page Table even if caches are in write-through mode. - Make sure to sync PTE in pmap_zero_page_generic(). Submitted by: Michal Mazur Reviewed by: cognet Obtained from: Semihalf MFC after: 1 month --- sys/arm/arm/pmap.c | 1 + sys/arm/include/pmap.h | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/sys/arm/arm/pmap.c b/sys/arm/arm/pmap.c index ec7fb1bd5e3..b6d8c768dfe 100644 --- a/sys/arm/arm/pmap.c +++ b/sys/arm/arm/pmap.c @@ -4039,6 +4039,7 @@ pmap_zero_page_generic(vm_paddr_t phys, int off, int size) * order to work without corruption when write-allocate is enabled. */ *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); + PTE_SYNC(cdst_pte); cpu_tlb_flushD_SE(cdstp); cpu_cpwait(); if (off || size != PAGE_SIZE) diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h index 3d63432e332..5f499a1dc90 100644 --- a/sys/arm/include/pmap.h +++ b/sys/arm/include/pmap.h @@ -382,7 +382,8 @@ do { \ if (PMAP_NEEDS_PTE_SYNC) { \ cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ - }\ + } else \ + cpu_drain_writebuf(); \ } while (/*CONSTCOND*/0) #define PTE_SYNC_RANGE(pte, cnt) \ @@ -392,7 +393,8 @@ do { \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ cpu_l2cache_wb_range((vm_offset_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ - } \ + } else \ + cpu_drain_writebuf(); \ } while (/*CONSTCOND*/0) extern pt_entry_t pte_l1_s_cache_mode; -- 2.45.2