From 6be7edd09040f042c8be4db4b400e8df77396aa4 Mon Sep 17 00:00:00 2001 From: marius Date: Wed, 1 Feb 2012 21:24:06 +0000 Subject: [PATCH] MFC: r230662 Fully disable interrupts while we fiddle with the FP context in the VIS-based block copy/zero implementations. While with 4BSD it's sufficient to just disable the tick interrupts, with ULE+PREEMPTION it's otherwise also possible that these are preempted via IPIs. git-svn-id: svn://svn.freebsd.org/base/stable/8@230893 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f --- sys/sparc64/sparc64/support.S | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/sys/sparc64/sparc64/support.S b/sys/sparc64/sparc64/support.S index bb247d324..02bcfddab 100644 --- a/sys/sparc64/sparc64/support.S +++ b/sys/sparc64/sparc64/support.S @@ -580,8 +580,8 @@ fpu_fault_begin: * void spitfire_block_copy(void *src, void *dst, size_t len) */ ENTRY(spitfire_block_copy) - rdpr %pil, %o3 - wrpr %g0, PIL_TICK, %pil + rdpr %pstate, %o3 + wrpr %g0, PSTATE_NORMAL, %pstate wr %g0, ASI_BLK_S, %asi wr %g0, FPRS_FEF, %fprs @@ -603,7 +603,7 @@ ENTRY(spitfire_block_copy) or %o4, PCB_FEF, %o4 stx %o4, [PCB_REG + PCB_FLAGS] -1: wrpr %o3, 0, %pil +1: wrpr %o3, 0, %pstate ldda [%o0] %asi, %f0 add %o0, 64, %o0 @@ -653,8 +653,8 @@ END(spitfire_block_copy) ENTRY(zeus_block_copy) prefetch [%o0 + (0 * 64)], 0 - rdpr %pil, %o3 - wrpr %g0, PIL_TICK, %pil + rdpr %pstate, %o3 + wrpr %g0, PSTATE_NORMAL, %pstate wr %g0, ASI_BLK_S, %asi wr %g0, FPRS_FEF, %fprs @@ -676,7 +676,7 @@ ENTRY(zeus_block_copy) or %o4, PCB_FEF, %o4 stx %o4, [PCB_REG + PCB_FLAGS] -1: wrpr %o3, 0, %pil +1: wrpr %o3, 0, %pstate ldd [%o0 + (0 * 8)], %f0 prefetch [%o0 + (1 * 64)], 0 @@ -764,8 +764,8 @@ END(zeus_block_copy) */ ALTENTRY(zeus_block_zero) ENTRY(spitfire_block_zero) - rdpr %pil, %o3 - wrpr %g0, PIL_TICK, %pil + rdpr %pstate, %o3 + wrpr %g0, PSTATE_NORMAL, %pstate wr %g0, ASI_BLK_S, %asi wr %g0, FPRS_FEF, %fprs @@ -787,7 +787,7 @@ ENTRY(spitfire_block_zero) or %o4, PCB_FEF, %o4 stx %o4, [PCB_REG + PCB_FLAGS] -1: wrpr %o3, 0, %pil +1: wrpr %o3, 0, %pstate fzero %f0 fzero %f2 -- 2.45.2