From 812de85df230f367ecabb8c40fe3adf6df254d1a Mon Sep 17 00:00:00 2001 From: mhorne Date: Sun, 7 Apr 2019 18:24:26 +0000 Subject: [PATCH] Add option to build LLVM RISC-V target Reviewed by: emaste, dim Approved by: markj (mentor) MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D19759 --- lib/clang/include/llvm/Config/AsmParsers.def | 3 + lib/clang/include/llvm/Config/AsmPrinters.def | 3 + .../include/llvm/Config/Disassemblers.def | 3 + lib/clang/include/llvm/Config/Targets.def | 3 + lib/clang/libllvm/Makefile | 56 +++++++++++++++++-- lib/clang/llvm.build.mk | 6 ++ share/man/man5/src.conf.5 | 20 ++++++- share/mk/src.opts.mk | 1 + tools/build/options/WITHOUT_LLVM_TARGET_RISCV | 5 ++ tools/build/options/WITH_LLVM_TARGET_RISCV | 5 ++ 10 files changed, 99 insertions(+), 6 deletions(-) create mode 100644 tools/build/options/WITHOUT_LLVM_TARGET_RISCV create mode 100644 tools/build/options/WITH_LLVM_TARGET_RISCV diff --git a/lib/clang/include/llvm/Config/AsmParsers.def b/lib/clang/include/llvm/Config/AsmParsers.def index 0447f34a52b..d0924c0914f 100644 --- a/lib/clang/include/llvm/Config/AsmParsers.def +++ b/lib/clang/include/llvm/Config/AsmParsers.def @@ -19,6 +19,9 @@ LLVM_ASM_PARSER(Mips) #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_ASM_PARSER(PowerPC) #endif +#ifdef LLVM_TARGET_ENABLE_RISCV +LLVM_ASM_PARSER(RISCV) +#endif #ifdef LLVM_TARGET_ENABLE_SPARC LLVM_ASM_PARSER(Sparc) #endif diff --git a/lib/clang/include/llvm/Config/AsmPrinters.def b/lib/clang/include/llvm/Config/AsmPrinters.def index 8c93cd08fff..2a335aa93b4 100644 --- a/lib/clang/include/llvm/Config/AsmPrinters.def +++ b/lib/clang/include/llvm/Config/AsmPrinters.def @@ -19,6 +19,9 @@ LLVM_ASM_PRINTER(Mips) #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_ASM_PRINTER(PowerPC) #endif +#ifdef LLVM_TARGET_ENABLE_RISCV +LLVM_ASM_PRINTER(RISCV) +#endif #ifdef LLVM_TARGET_ENABLE_SPARC LLVM_ASM_PRINTER(Sparc) #endif diff --git a/lib/clang/include/llvm/Config/Disassemblers.def b/lib/clang/include/llvm/Config/Disassemblers.def index af7ae59d3fe..756ff37b4bf 100644 --- a/lib/clang/include/llvm/Config/Disassemblers.def +++ b/lib/clang/include/llvm/Config/Disassemblers.def @@ -19,6 +19,9 @@ LLVM_DISASSEMBLER(Mips) #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_DISASSEMBLER(PowerPC) #endif +#ifdef LLVM_TARGET_ENABLE_RISCV +LLVM_DISASSEMBLER(RISCV) +#endif #ifdef LLVM_TARGET_ENABLE_SPARC LLVM_DISASSEMBLER(Sparc) #endif diff --git a/lib/clang/include/llvm/Config/Targets.def b/lib/clang/include/llvm/Config/Targets.def index 9be98faea61..b6cb6fee9dc 100644 --- a/lib/clang/include/llvm/Config/Targets.def +++ b/lib/clang/include/llvm/Config/Targets.def @@ -19,6 +19,9 @@ LLVM_TARGET(Mips) #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_TARGET(PowerPC) #endif +#ifdef LLVM_TARGET_ENABLE_RISCV +LLVM_TARGET(RISCV) +#endif #ifdef LLVM_TARGET_ENABLE_SPARC LLVM_TARGET(Sparc) #endif diff --git a/lib/clang/libllvm/Makefile b/lib/clang/libllvm/Makefile index 52e2d635599..23d13ef688b 100644 --- a/lib/clang/libllvm/Makefile +++ b/lib/clang/libllvm/Makefile @@ -10,14 +10,15 @@ CFLAGS+= -I${.OBJDIR} .if ${MK_LLVM_TARGET_AARCH64} == "no" && ${MK_LLVM_TARGET_ARM} == "no" && \ ${MK_LLVM_TARGET_BPF} == "no" && ${MK_LLVM_TARGET_MIPS} == "no" && \ - ${MK_LLVM_TARGET_POWERPC} == "no" && ${MK_LLVM_TARGET_SPARC} == "no" && \ - ${MK_LLVM_TARGET_X86} == "no" + ${MK_LLVM_TARGET_POWERPC} == "no" && ${MK_LLVM_TARGET_RISCV} == "no" && \ + ${MK_LLVM_TARGET_SPARC} == "no" && ${MK_LLVM_TARGET_X86} == "no" .error Please enable at least one of: MK_LLVM_TARGET_AARCH64,\ MK_LLVM_TARGET_ARM, MK_LLVM_TARGET_BPF, MK_LLVM_TARGET_MIPS, \ - MK_LLVM_TARGET_POWERPC, MK_LLVM_TARGET_SPARC, or MK_LLVM_TARGET_X86 + MK_LLVM_TARGET_POWERPC, MK_LLVM_TARGET_RISCV, MK_LLVM_TARGET_SPARC, \ + or MK_LLVM_TARGET_X86 .endif -.for arch in AArch64 ARM BPF Mips PowerPC Sparc X86 +.for arch in AArch64 ARM BPF Mips PowerPC RISCV Sparc X86 . if ${MK_LLVM_TARGET_${arch:tu}} != "no" CFLAGS+= -I${LLVM_SRCS}/lib/Target/${arch} . endif @@ -1128,6 +1129,34 @@ SRCS_MIN+= Target/PowerPC/PPCVSXFMAMutate.cpp SRCS_MIN+= Target/PowerPC/PPCVSXSwapRemoval.cpp SRCS_MIN+= Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp .endif # MK_LLVM_TARGET_POWERPC +.if ${MK_LLVM_TARGET_RISCV} != "no" +SRCS_MIN+= Target/RISCV/AsmParser/RISCVAsmParser.cpp +SRCS_MIN+= Target/RISCV/Disassembler/RISCVDisassembler.cpp +SRCS_MIN+= Target/RISCV/InstPrinter/RISCVInstPrinter.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +SRCS_MIN+= Target/RISCV/RISCVAsmPrinter.cpp +SRCS_MIN+= Target/RISCV/RISCVExpandPseudoInsts.cpp +SRCS_MIN+= Target/RISCV/RISCVFrameLowering.cpp +SRCS_MIN+= Target/RISCV/RISCVInstrInfo.cpp +SRCS_MIN+= Target/RISCV/RISCVISelDAGToDAG.cpp +SRCS_MIN+= Target/RISCV/RISCVISelLowering.cpp +SRCS_MIN+= Target/RISCV/RISCVMCInstLower.cpp +SRCS_MIN+= Target/RISCV/RISCVMergeBaseOffset.cpp +SRCS_MIN+= Target/RISCV/RISCVRegisterInfo.cpp +SRCS_MIN+= Target/RISCV/RISCVSubtarget.cpp +SRCS_MIN+= Target/RISCV/RISCVTargetMachine.cpp +SRCS_MIN+= Target/RISCV/RISCVTargetObjectFile.cpp +SRCS_MIN+= Target/RISCV/TargetInfo/RISCVTargetInfo.cpp +SRCS_MIN+= Target/RISCV/Utils/RISCVBaseInfo.cpp +SRCS_MIN+= Target/RISCV/Utils/RISCVMatInt.cpp +.endif # MK_LLVM_TARGET_RISCV .if ${MK_LLVM_TARGET_SPARC} != "no" SRCS_MIN+= Target/Sparc/AsmParser/SparcAsmParser.cpp SRCS_MIN+= Target/Sparc/DelaySlotFiller.cpp @@ -1545,13 +1574,15 @@ beforebuild: # Note: some rules are superfluous, not every combination is valid. .for arch in \ - AArch64/AArch64 ARM/ARM BPF/BPF Mips/Mips PowerPC/PPC Sparc/Sparc X86/X86 + AArch64/AArch64 ARM/ARM BPF/BPF Mips/Mips PowerPC/PPC Sparc/Sparc \ + RISCV/RISCV X86/X86 . for hdr in \ AsmMatcher/-gen-asm-matcher \ AsmWriter1/-gen-asm-writer,-asmwriternum=1 \ AsmWriter/-gen-asm-writer \ CallingConv/-gen-callingconv \ CodeEmitter/-gen-emitter \ + CompressInstEmitter/-gen-compress-inst-emitter \ DAGISel/-gen-dag-isel \ DisassemblerTables/-gen-disassembler \ EVEX2VEXTables/-gen-x86-EVEX2VEX-tables \ @@ -1643,6 +1674,21 @@ TGHDRS+= PPCGenMCCodeEmitter.inc TGHDRS+= PPCGenRegisterInfo.inc TGHDRS+= PPCGenSubtargetInfo.inc .endif # MK_LLVM_TARGET_POWERPC +.if ${MK_LLVM_TARGET_RISCV} != "no" +TGHDRS+= RISCVGenAsmMatcher.inc +TGHDRS+= RISCVGenAsmWriter.inc +TGHDRS+= RISCVGenCallingConv.inc +TGHDRS+= RISCVGenCompressInstEmitter.inc +TGHDRS+= RISCVGenDAGISel.inc +TGHDRS+= RISCVGenDisassemblerTables.inc +TGHDRS+= RISCVGenDAGISel.inc +TGHDRS+= RISCVGenInstrInfo.inc +TGHDRS+= RISCVGenMCCodeEmitter.inc +TGHDRS+= RISCVGenMCPseudoLowering.inc +TGHDRS+= RISCVGenRegisterInfo.inc +TGHDRS+= RISCVGenSubtargetInfo.inc +TGHDRS+= RISCVGenSystemOperands.inc +.endif # MK_LLVM_TARGET_RISCV .if ${MK_LLVM_TARGET_SPARC} != "no" TGHDRS+= SparcGenAsmMatcher.inc TGHDRS+= SparcGenAsmWriter.inc diff --git a/lib/clang/llvm.build.mk b/lib/clang/llvm.build.mk index 33357490441..24be5647e77 100644 --- a/lib/clang/llvm.build.mk +++ b/lib/clang/llvm.build.mk @@ -69,6 +69,12 @@ CFLAGS+= -DLLVM_TARGET_ENABLE_POWERPC LLVM_NATIVE_ARCH= PowerPC . endif .endif +.if ${MK_LLVM_TARGET_RISCV} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_RISCV +. if ${MACHINE_CPUARCH} == "riscv" +LLVM_NATIVE_ARCH= RISCV +. endif +.endif .if ${MK_LLVM_TARGET_SPARC} != "no" CFLAGS+= -DLLVM_TARGET_ENABLE_SPARC . if ${MACHINE_CPUARCH} == "sparc64" diff --git a/share/man/man5/src.conf.5 b/share/man/man5/src.conf.5 index 67360756c39..6d21a403468 100644 --- a/share/man/man5/src.conf.5 +++ b/share/man/man5/src.conf.5 @@ -1,6 +1,6 @@ .\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman. .\" $FreeBSD$ -.Dd March 16, 2019 +.Dd March 29, 2019 .Dt SRC.CONF 5 .Os .Sh NAME @@ -399,6 +399,10 @@ is set explicitly) (unless .Va WITH_LLVM_TARGET_POWERPC is set explicitly) +.It Va WITHOUT_LLVM_TARGET_RISCV +(unless +.Va WITH_LLVM_TARGET_RISCV +is set explicitly) .It Va WITHOUT_LLVM_TARGET_SPARC (unless .Va WITH_LLVM_TARGET_SPARC @@ -1210,6 +1214,20 @@ option should be used rather than this in most cases. .Pp This is a default setting on amd64/amd64, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and powerpc/powerpcspe. +.It Va WITHOUT_LLVM_TARGET_RISCV +Set to not build LLVM target support for RISC-V. +The +.Va LLVM_TARGET_ALL +option should be used rather than this in most cases. +.Pp +This is a default setting on +amd64/amd64, arm/arm, arm/armv6, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64, powerpc/powerpcspe, and sparc/sparc64. +.It Va WITH_LLVM_TARGET_RISCV +Set to build LLVM target support for RISC-V. +The +.Va LLVM_TARGET_ALL +option should be used rather than this in most cases. +.Pp .It Va WITHOUT_LLVM_TARGET_SPARC Set to not build LLVM target support for SPARC. The diff --git a/share/mk/src.opts.mk b/share/mk/src.opts.mk index 18262c48317..96e3c94a948 100644 --- a/share/mk/src.opts.mk +++ b/share/mk/src.opts.mk @@ -290,6 +290,7 @@ __DEFAULT_DEPENDENT_OPTIONS+= LLVM_TARGET_${__llt:${__LLVM_TARGET_FILT}:tu}/LLVM .endfor __DEFAULT_NO_OPTIONS+=LLVM_TARGET_BPF +__DEFAULT_NO_OPTIONS+=LLVM_TARGET_RISCV .include # If the compiler is not C++11 capable, disable Clang and use GCC instead. diff --git a/tools/build/options/WITHOUT_LLVM_TARGET_RISCV b/tools/build/options/WITHOUT_LLVM_TARGET_RISCV new file mode 100644 index 00000000000..d3895ca2087 --- /dev/null +++ b/tools/build/options/WITHOUT_LLVM_TARGET_RISCV @@ -0,0 +1,5 @@ +.\" $FreeBSD$ +Set to not build LLVM target support for RISC-V. +The +.Va LLVM_TARGET_ALL +option should be used rather than this in most cases. diff --git a/tools/build/options/WITH_LLVM_TARGET_RISCV b/tools/build/options/WITH_LLVM_TARGET_RISCV new file mode 100644 index 00000000000..673ba0bdce3 --- /dev/null +++ b/tools/build/options/WITH_LLVM_TARGET_RISCV @@ -0,0 +1,5 @@ +.\" $FreeBSD$ +Set to build LLVM target support for RISC-V. +The +.Va LLVM_TARGET_ALL +option should be used rather than this in most cases. -- 2.45.0