From 91e68110e47507a4cd3e895b651b840bb58a4623 Mon Sep 17 00:00:00 2001 From: dim Date: Sat, 23 Mar 2019 14:10:05 +0000 Subject: [PATCH] Pull in r356809 from upstream llvm trunk (by Eli Friedman): [ARM] Don't form "ands" when it isn't scheduled correctly. In r322972/r323136, the iteration here was changed to catch cases at the beginning of a basic block... but we accidentally deleted an important safety check. Restore that check to the way it was. Fixes https://bugs.llvm.org/show_bug.cgi?id=41116 Differential Revision: https://reviews.llvm.org/D59680 This should fix "Assertion failed: (LiveCPSR && "CPSR liveness tracking is wrong!"), function UpdateCPSRUse" errors when building the devel/xwpe port for armv7. PR: 236062, 236568 MFC after: 1 month X-MFC-With: r344779 --- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index bbebed59c85..34d501d1296 100644 --- a/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2824,7 +2824,15 @@ bool ARMBaseInstrInfo::optimizeCompareInstr( // change. We can't do this transformation. return false; - } while (I != B); + if (I == B) { + // In some cases, we scan the use-list of an instruction for an AND; + // that AND is in the same BB, but may not be scheduled before the + // corresponding TST. In that case, bail out. + // + // FIXME: We could try to reschedule the AND. + return false; + } + } while (true); // Return false if no candidates exist. if (!MI && !SubAdd) -- 2.45.2