From 9fc62ba649126f546c7d6bd09ab44d147b3d8ff6 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 9 Sep 2020 18:11:04 +0000 Subject: [PATCH] Merge commit e6bb4c8e7 from llvm git (by Craig Topper): [X86] SSE4_A should only imply SSE3 not SSSE3 in the frontend. SSE4_1 and SSE4_2 due imply SSSE3. So I guess I got confused when switching the code to being table based in D83273. Fixes PR47464 This should fix builds with -march=amdfam10 emitting SSSE3 instructions such as pshufb, which lead to programs crashing with SIGILL on such processors. Reported by: avg MFC after: 6 weeks X-MFC-With: r364284 --- contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp b/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp index c629f872df1..4c2d4efbfca 100644 --- a/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp +++ b/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp @@ -522,7 +522,7 @@ static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; // SSE4_A->FMA4->XOP chain. -static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSSE3; +static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3; static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; -- 2.45.0