From a50299d61935e901c70d21036d8e26898e1ae02e Mon Sep 17 00:00:00 2001 From: ian Date: Sat, 23 May 2015 17:30:30 +0000 Subject: [PATCH] MFC r278770, r279114, r279215, r279338, r279543: Add logic for handling new-style ARM cpu ID info. Correct a comment which was exactly backwards from reality. There is no reason to do i+dcache writeback and invalidate when changing the translation table (this may be left over from armv5 days). It's especially bad to do so using a cache operation that isn't coherent on SMP systems. Add casting to make atomic ops work for pointers. (Apparently nobody has ever done atomic ops on pointers before now on arm). Revert incorrect casting. git-svn-id: svn://svn.freebsd.org/base/stable/10@283317 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f --- sys/arm/arm/cpufunc_asm_armv7.S | 4 ---- sys/arm/arm/cpuinfo.c | 8 ++++++-- sys/arm/include/atomic.h | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 9fe6aa5c9..5d6907eee 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -66,11 +66,7 @@ __FBSDID("$FreeBSD$"); #endif ENTRY(armv7_setttb) - stmdb sp!, {r0, lr} - bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ - ldmia sp!, {r0, lr} dsb - orr r0, r0, #PT_ATTR mcr CP15_TTBR0(r0) isb diff --git a/sys/arm/arm/cpuinfo.c b/sys/arm/arm/cpuinfo.c index d20c5610a..b0b8a88f0 100644 --- a/sys/arm/arm/cpuinfo.c +++ b/sys/arm/arm/cpuinfo.c @@ -58,9 +58,13 @@ cpuinfo_init(void) /* ARMv4T CPU */ cpuinfo.architecture = 1; cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F; - } + } else { + /* ARM new id scheme */ + cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; + cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; + } } else { - /* must be new id scheme */ + /* non ARM -> must be new id scheme */ cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; } diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h index 5857f5d96..57fdf717a 100644 --- a/sys/arm/include/atomic.h +++ b/sys/arm/include/atomic.h @@ -582,8 +582,8 @@ atomic_load_64(volatile uint64_t *p) /* * The only way to atomically load 64 bits is with LDREXD which puts the - * exclusive monitor into the open state, so reset it with CLREX because - * we don't actually need to store anything. + * exclusive monitor into the exclusive state, so reset it to open state + * with CLREX because we don't actually need to store anything. */ __asm __volatile( "1: \n" -- 2.45.0