From b38336e008373176e1f0fd6658a12aecd5c9f9ea Mon Sep 17 00:00:00 2001 From: arybchik Date: Wed, 26 Dec 2018 09:33:26 +0000 Subject: [PATCH] MFC r340767 sfxge(4): limit max TXQ size on Medford to 2048 Queues with 4096 descriptors are not supported as the top bit is used for vfifo stuffing. Submitted by: Mark Spender Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D8948 git-svn-id: svn://svn.freebsd.org/base/stable/10@342480 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f --- sys/dev/sfxge/common/ef10_tx.c | 2 +- sys/dev/sfxge/common/efx.h | 7 +------ sys/dev/sfxge/common/efx_tx.c | 4 ++-- sys/dev/sfxge/common/hunt_nic.c | 6 ++++++ sys/dev/sfxge/common/medford_nic.c | 7 +++++++ sys/dev/sfxge/common/siena_nic.c | 2 ++ sys/dev/sfxge/sfxge.c | 4 ++-- 7 files changed, 21 insertions(+), 11 deletions(-) mode change 100755 => 100644 sys/dev/sfxge/common/ef10_tx.c diff --git a/sys/dev/sfxge/common/ef10_tx.c b/sys/dev/sfxge/common/ef10_tx.c old mode 100755 new mode 100644 index e39b27166..28182e37e --- a/sys/dev/sfxge/common/ef10_tx.c +++ b/sys/dev/sfxge/common/ef10_tx.c @@ -67,7 +67,7 @@ efx_mcdi_init_txq( efx_rc_t rc; EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >= - EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg))); + EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs)); npages = EFX_TXQ_NBUFS(size); if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) { diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h index 0f91b4fa6..1f93973c8 100644 --- a/sys/dev/sfxge/common/efx.h +++ b/sys/dev/sfxge/common/efx.h @@ -1105,6 +1105,7 @@ typedef struct efx_nic_cfg_s { uint32_t enc_evq_limit; uint32_t enc_txq_limit; uint32_t enc_rxq_limit; + uint32_t enc_txq_max_ndescs; uint32_t enc_buftbl_limit; uint32_t enc_piobuf_limit; uint32_t enc_piobuf_size; @@ -1975,12 +1976,6 @@ extern void efx_tx_fini( __in efx_nic_t *enp); -#define EFX_BUG35388_WORKAROUND(_encp) \ - (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) - -#define EFX_TXQ_MAXNDESCS(_encp) \ - ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) - #define EFX_TXQ_MINNDESCS 512 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) diff --git a/sys/dev/sfxge/common/efx_tx.c b/sys/dev/sfxge/common/efx_tx.c index cb976af2c..b088f892d 100644 --- a/sys/dev/sfxge/common/efx_tx.c +++ b/sys/dev/sfxge/common/efx_tx.c @@ -911,7 +911,7 @@ siena_tx_qcreate( (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH)); EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS); - EFSYS_ASSERT(ISP2(EFX_TXQ_MAXNDESCS(encp))); + EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs)); EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS)); if (!ISP2(n) || (n < EFX_TXQ_MINNDESCS) || (n > EFX_EVQ_MAXNEVS)) { @@ -923,7 +923,7 @@ siena_tx_qcreate( goto fail2; } for (size = 0; - (1 << size) <= (EFX_TXQ_MAXNDESCS(encp) / EFX_TXQ_MINNDESCS); + (1 << size) <= (int)(encp->enc_txq_max_ndescs / EFX_TXQ_MINNDESCS); size++) if ((1 << size) == (int)(n / EFX_TXQ_MINNDESCS)) break; diff --git a/sys/dev/sfxge/common/hunt_nic.c b/sys/dev/sfxge/common/hunt_nic.c index 477fa76da..b9be53445 100644 --- a/sys/dev/sfxge/common/hunt_nic.c +++ b/sys/dev/sfxge/common/hunt_nic.c @@ -318,6 +318,12 @@ hunt_board_cfg( encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; + /* + * The workaround for bug35388 uses the top bit of transmit queue + * descriptor writes, preventing the use of 4096 descriptor TXQs. + */ + encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096; + encp->enc_buftbl_limit = 0xFFFFFFFF; encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; diff --git a/sys/dev/sfxge/common/medford_nic.c b/sys/dev/sfxge/common/medford_nic.c index f883bf7af..3c54fcdbc 100644 --- a/sys/dev/sfxge/common/medford_nic.c +++ b/sys/dev/sfxge/common/medford_nic.c @@ -315,6 +315,13 @@ medford_board_cfg( encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; + /* + * The maximum supported transmit queue size is 2048. TXQs with 4096 + * descriptors are not supported as the top bit is used for vfifo + * stuffing. + */ + encp->enc_txq_max_ndescs = 2048; + encp->enc_buftbl_limit = 0xFFFFFFFF; encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS; diff --git a/sys/dev/sfxge/common/siena_nic.c b/sys/dev/sfxge/common/siena_nic.c index 39922a7dd..ad58eb06b 100644 --- a/sys/dev/sfxge/common/siena_nic.c +++ b/sys/dev/sfxge/common/siena_nic.c @@ -156,6 +156,8 @@ siena_board_cfg( encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq); encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq); + encp->enc_txq_max_ndescs = 4096; + encp->enc_buftbl_limit = SIENA_SRAM_ROWS - (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) - (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE)); diff --git a/sys/dev/sfxge/sfxge.c b/sys/dev/sfxge/sfxge.c index f91275ef1..cf4e37237 100644 --- a/sys/dev/sfxge/sfxge.c +++ b/sys/dev/sfxge/sfxge.c @@ -756,10 +756,10 @@ sfxge_create(struct sfxge_softc *sc) if (!ISP2(sfxge_tx_ring_entries) || (sfxge_tx_ring_entries < EFX_TXQ_MINNDESCS) || - (sfxge_tx_ring_entries > EFX_TXQ_MAXNDESCS(efx_nic_cfg_get(enp)))) { + (sfxge_tx_ring_entries > efx_nic_cfg_get(enp)->enc_txq_max_ndescs)) { log(LOG_ERR, "%s=%d must be power of 2 from %u to %u", SFXGE_PARAM_TX_RING, sfxge_tx_ring_entries, - EFX_TXQ_MINNDESCS, EFX_TXQ_MAXNDESCS(efx_nic_cfg_get(enp))); + EFX_TXQ_MINNDESCS, efx_nic_cfg_get(enp)->enc_txq_max_ndescs); error = EINVAL; goto fail_tx_ring_entries; } -- 2.45.0