From dae9df273726d3cc2824c1835e556ceea816b1d7 Mon Sep 17 00:00:00 2001 From: gonzo Date: Wed, 24 Jun 2009 22:42:52 +0000 Subject: [PATCH] - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu --- sys/mips/malta/malta_machdep.c | 88 ++++++++++++++++------------ sys/mips/malta/uart_cpu_maltausart.c | 2 +- 2 files changed, 50 insertions(+), 40 deletions(-) diff --git a/sys/mips/malta/malta_machdep.c b/sys/mips/malta/malta_machdep.c index c5c28af8b63..0f53f13fb47 100644 --- a/sys/mips/malta/malta_machdep.c +++ b/sys/mips/malta/malta_machdep.c @@ -226,6 +226,52 @@ platform_trap_exit(void) } +static uint64_t +malta_cpu_freq(void) +{ + uint64_t platform_counter_freq = 0; + +#if defined(TICK_USE_YAMON_FREQ) + /* + * If we are running on a board which uses YAMON firmware, + * then query CPU pipeline clock from the syscon object. + * If unsuccessful, use hard-coded default. + */ + platform_counter_freq = yamon_getcpufreq(); + +#elif defined(TICK_USE_MALTA_RTC) + /* + * If we are running on a board with the MC146818 RTC, + * use it to determine CPU pipeline clock frequency. + */ + u_int64_t counterval[2]; + + /* Set RTC to binary mode. */ + writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD)); + + /* Busy-wait for falling edge of RTC update. */ + while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) + ; + while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) + ; + counterval[0] = mips_rd_count(); + + /* Busy-wait for falling edge of RTC update. */ + while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) + ; + while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) + ; + counterval[1] = mips_rd_count(); + + platform_counter_freq = counterval[1] - counterval[0]; +#endif + + if (platform_counter_freq == 0) + platform_counter_freq = MIPS_DEFAULT_HZ; + + return (platform_counter_freq); +} + void platform_start(__register_t a0, __register_t a1, __register_t a2, __register_t a3) @@ -242,6 +288,9 @@ platform_start(__register_t a0, __register_t a1, __register_t a2, kernend = round_page((vm_offset_t)&end); memset(&edata, 0, kernend - (vm_offset_t)(&edata)); + platform_counter_freq = malta_cpu_freq(); + mips_timer_early_init(platform_counter_freq); + cninit(); printf("entry: platform_start()\n"); @@ -262,44 +311,5 @@ platform_start(__register_t a0, __register_t a1, __register_t a2, realmem = btoc(memsize); mips_init(); - do { -#if defined(TICK_USE_YAMON_FREQ) - /* - * If we are running on a board which uses YAMON firmware, - * then query CPU pipeline clock from the syscon object. - * If unsuccessful, use hard-coded default. - */ - platform_counter_freq = yamon_getcpufreq(); - if (platform_counter_freq == 0) - platform_counter_freq = MIPS_DEFAULT_HZ; - -#elif defined(TICK_USE_MALTA_RTC) - /* - * If we are running on a board with the MC146818 RTC, - * use it to determine CPU pipeline clock frequency. - */ - u_int64_t counterval[2]; - - /* Set RTC to binary mode. */ - writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD)); - - /* Busy-wait for falling edge of RTC update. */ - while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) - ; - while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) - ; - counterval[0] = mips_rd_count(); - - /* Busy-wait for falling edge of RTC update. */ - while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0)) - ; - while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0)) - ; - counterval[1] = mips_rd_count(); - - platform_counter_freq = counterval[1] - counterval[0]; -#endif - } while(0); - mips_timer_init_params(platform_counter_freq, 0); } diff --git a/sys/mips/malta/uart_cpu_maltausart.c b/sys/mips/malta/uart_cpu_maltausart.c index 01ef8db332d..d65ddfaffa1 100644 --- a/sys/mips/malta/uart_cpu_maltausart.c +++ b/sys/mips/malta/uart_cpu_maltausart.c @@ -71,7 +71,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); di->bas.regshft = 0; di->bas.rclk = 0; - di->baudrate = 115200; + di->baudrate = 0; /* retain the baudrate configured by YAMON */ di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; -- 2.45.2