From ec32fc2af52530e49d8a522ae29bf20b2e57603b Mon Sep 17 00:00:00 2001 From: "Bjoern A. Zeeb" Date: Tue, 5 Jul 2022 00:53:42 +0000 Subject: [PATCH] dwc3: fix from not working During the review of 09cdf4878c621be4cd229fa88cdccdcdc8c101f7 we switched from cached registers to reading them as needed. One read of the two reads was moved after the softreset got triggered and as a result returned 0 rather than the proper register value. Moving the read before the softreset gets initiated seems to make things work again and xhci.c no longer complains about "Controller does not support 4K page size.". MFC after: 10 days X-MFC with: 09cdf4878c621be4cd229fa88cdccdcdc8c101f7 Pointy hat to: bz --- sys/dev/usb/controller/dwc3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/dev/usb/controller/dwc3.c b/sys/dev/usb/controller/dwc3.c index da64512af64..a71f92abebd 100644 --- a/sys/dev/usb/controller/dwc3.c +++ b/sys/dev/usb/controller/dwc3.c @@ -207,11 +207,12 @@ snps_dwc3_reset(struct snps_dwc3_softc *sc) if (sc->usb3_phy) phy_enable(sc->usb3_phy); + ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); + gctl = DWC3_READ(sc, DWC3_GCTL); gctl |= DWC3_GCTL_CORESOFTRESET; DWC3_WRITE(sc, DWC3_GCTL, gctl); - ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST; if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == -- 2.45.0