/* * MPC8572 DS Device Tree Source * * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved * * Neither the name of Freescale Semiconductor, Inc nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * Freescale hereby publishes it under the following licenses: * * BSD License * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * GNU General Public License, version 2 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * MA 02110-1301, USA. * * You may select the license of your choice. *------------------------------------------------------------------ * * $FreeBSD$ */ /dts-v1/; / { model = "fsl,MPC8572DS"; compatible = "fsl,MPC8572DS"; #address-cells = <2>; #size-cells = <2>; aliases { ethernet0 = &enet0; ethernet1 = &enet1; ethernet2 = &enet2; ethernet3 = &enet3; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8572@0 { device_type = "cpu"; reg = <0x0>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <0x8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; next-level-cache = <&L2>; }; PowerPC,8572@1 { device_type = "cpu"; reg = <0x1>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <0x8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; next-level-cache = <&L2>; }; }; memory { device_type = "memory"; }; localbus@ffe05000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; reg = <0 0xffe05000 0 0x1000>; interrupts = <19 2>; interrupt-parent = <&mpic>; ranges = <0x0 0x0 0x0 0xe8000000 0x08000000>; nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; bank-width = <2>; device-width = <1>; partition@0 { reg = <0x0 0x03000000>; label = "ramdisk-nor"; read-only; }; partition@3000000 { reg = <0x03000000 0x00e00000>; label = "diagnostic-nor"; read-only; }; partition@3e00000 { reg = <0x03e00000 0x00200000>; label = "dink-nor"; read-only; }; partition@4000000 { reg = <0x04000000 0x00400000>; label = "kernel-nor"; read-only; }; partition@4400000 { reg = <0x04400000 0x03b00000>; label = "jffs2-nor"; }; partition@7f00000 { reg = <0x07f00000 0x00080000>; label = "dtb-nor"; read-only; }; partition@7f80000 { reg = <0x07f80000 0x00080000>; label = "u-boot-nor"; read-only; }; }; nand@2,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8572-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x2 0x0 0x40000>; partition@0 { reg = <0x0 0x02000000>; label = "u-boot-nand"; read-only; }; partition@2000000 { reg = <0x02000000 0x10000000>; label = "jffs2-nand"; }; partition@12000000 { reg = <0x12000000 0x08000000>; label = "ramdisk-nand"; read-only; }; partition@1a000000 { reg = <0x1a000000 0x04000000>; label = "kernel-nand"; }; partition@1e000000 { reg = <0x1e000000 0x01000000>; label = "dtb-nand"; read-only; }; partition@1f000000 { reg = <0x1f000000 0x21000000>; label = "reserved-nand"; }; }; nand@4,0 { compatible = "fsl,mpc8572-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x4 0x0 0x40000>; }; nand@5,0 { compatible = "fsl,mpc8572-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x5 0x0 0x40000>; }; nand@6,0 { compatible = "fsl,mpc8572-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x6 0x0 0x40000>; }; }; soc8572@ffe00000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0 0xffe00000 0x100000>; bus-frequency = <0>; // Filled out by uboot. ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <12>; }; ecm@1000 { compatible = "fsl,mpc8572-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; memory-controller@6000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x6000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,mpc8572-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x100000>; // L2, 1M interrupt-parent = <&mpic>; interrupts = <16 2>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; i2c@3100 { #address-cells = <1>; #size-cells = <0>; cell-index = <1>; compatible = "fsl-i2c"; reg = <0x3100 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; dma@c300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; reg = <0xc300 0x4>; ranges = <0x0 0xc100 0x200>; cell-index = <1>; dma-channel@0 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <76 2>; }; dma-channel@80 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <77 2>; }; dma-channel@100 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <78 2>; }; dma-channel@180 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <79 2>; }; }; dma@21300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8572-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <23 2>; }; }; ptp_timer: ptimer@24e00 { compatible = "fsl,gianfar-ptp-timer"; reg = <0x24e00 0xb0>; }; enet0: ethernet@24000 { #address-cells = <1>; #size-cells = <1>; cell-index = <0>; device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x24000 0x1000>; ranges = <0x0 0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; tbi-handle = <&tbi0>; phy-handle = <&phy0>; ptimer-handle = < &ptp_timer >; phy-connection-type = "rgmii-id"; mdio@520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; reg = <0x520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <10 1>; reg = <0x0>; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <10 1>; reg = <0x1>; }; phy2: ethernet-phy@2 { interrupt-parent = <&mpic>; interrupts = <10 1>; reg = <0x2>; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; interrupts = <10 1>; reg = <0x3>; }; tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; enet1: ethernet@25000 { #address-cells = <1>; #size-cells = <1>; cell-index = <1>; device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x25000 0x1000>; ranges = <0x0 0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; tbi-handle = <&tbi1>; phy-handle = <&phy1>; ptimer-handle = < &ptp_timer >; phy-connection-type = "rgmii-id"; mdio@520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-tbi"; reg = <0x520 0x20>; tbi1: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; enet2: ethernet@26000 { #address-cells = <1>; #size-cells = <1>; cell-index = <2>; device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x26000 0x1000>; ranges = <0x0 0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <31 2 32 2 33 2>; interrupt-parent = <&mpic>; tbi-handle = <&tbi2>; phy-handle = <&phy2>; ptimer-handle = < &ptp_timer >; phy-connection-type = "rgmii-id"; mdio@520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-tbi"; reg = <0x520 0x20>; tbi2: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; enet3: ethernet@27000 { #address-cells = <1>; #size-cells = <1>; cell-index = <3>; device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x27000 0x1000>; ranges = <0x0 0x27000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <37 2 38 2 39 2>; interrupt-parent = <&mpic>; tbi-handle = <&tbi3>; phy-handle = <&phy3>; phy-connection-type = "rgmii-id"; mdio@520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-tbi"; reg = <0x520 0x20>; tbi3: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "ns16550"; reg = <0x4500 0x100>; clock-frequency = <0>; interrupts = <42 2>; interrupt-parent = <&mpic>; }; serial1: serial@4600 { cell-index = <1>; device_type = "serial"; compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; interrupts = <42 2>; interrupt-parent = <&mpic>; }; global-utilities@e0000 { //global utilities block compatible = "fsl,mpc8572-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; power@e0070{ compatible = "fsl,mpc8548-pmc"; reg = <0xe0070 0x14>; }; timer@41100 { compatible = "fsl,mpic-global-timer"; reg = <0x41100 0x204>; interrupts = <0xf7 0x2>; interrupt-parent = <&mpic>; }; msi@41600 { compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; reg = <0x41600 0x80>; msi-available-ranges = <0 0x100>; interrupts = < 0xe0 0 0xe1 0 0xe2 0 0xe3 0 0xe4 0 0xe5 0 0xe6 0 0xe7 0>; interrupt-parent = <&mpic>; }; crypto@30000 { compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <45 2 58 2>; interrupt-parent = <&mpic>; fsl,num-channels = <4>; fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0x9fe>; fsl,descriptor-types-mask = <0x3ab0ebf>; }; /* PME (pattern-matcher) */ pme@10000 { device_type = "pme"; compatible = "pme8572"; reg = <0x10000 0x5000>; interrupts = <0x39 0x2 0x40 0x2 0x41 0x2 0x42 0x2 0x43 0x2>; interrupt-parent = <&mpic>; }; mpic: pic@40000 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; }; }; pci0: pcie@ffe08000 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0 0xffe08000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x00000000 0 0xfee20000 0x0 0x00010000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <24 2>; interrupt-map-mask = <0xff00 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x11 func 0 - PCI slot 1 */ 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 1 - PCI slot 1 */ 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 2 - PCI slot 1 */ 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 3 - PCI slot 1 */ 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 4 - PCI slot 1 */ 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 5 - PCI slot 1 */ 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 6 - PCI slot 1 */ 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 7 - PCI slot 1 */ 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x12 func 0 - PCI slot 2 */ 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 1 - PCI slot 2 */ 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 2 - PCI slot 2 */ 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 3 - PCI slot 2 */ 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 4 - PCI slot 2 */ 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 5 - PCI slot 2 */ 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 6 - PCI slot 2 */ 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 7 - PCI slot 2 */ 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 // IDSEL 0x1c USB 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 // IDSEL 0x1d Audio 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 // IDSEL 0x1e Legacy 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 // IDSEL 0x1f IDE/SATA 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 >; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x10000>; uli1575@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x10000>; isa@1e { device_type = "isa"; #interrupt-cells = <2>; #size-cells = <1>; #address-cells = <2>; reg = <0xf000 0x0 0x0 0x0 0x0>; ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; interrupt-parent = <&i8259>; i8259: interrupt-controller@20 { reg = <0x1 0x20 0x2 0x1 0xa0 0x2 0x1 0x4d0 0x2>; interrupt-controller; device_type = "interrupt-controller"; #address-cells = <0>; #interrupt-cells = <2>; compatible = "chrp,iic"; interrupts = <9 2>; interrupt-parent = <&mpic>; }; i8042@60 { #size-cells = <0>; #address-cells = <1>; reg = <0x1 0x60 0x1 0x1 0x64 0x1>; interrupts = <1 3 12 3>; interrupt-parent = <&i8259>; keyboard@0 { reg = <0x0>; compatible = "pnpPNP,303"; }; mouse@1 { reg = <0x1>; compatible = "pnpPNP,f03"; }; }; rtc@70 { compatible = "pnpPNP,b00"; reg = <0x1 0x70 0x2>; }; gpio@400 { reg = <0x1 0x400 0x80>; }; }; }; }; }; pci1: pcie@ffe09000 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0 0xffe09000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000 0x1000000 0x0 0x00000000 0 0xfee10000 0x0 0x00010000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <25 2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0000 0x0 0x0 0x4 &mpic 0x7 0x1 >; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x2000000 0x0 0x90000000 0x2000000 0x0 0x90000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x10000>; }; }; pci2: pcie@ffe0a000 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0 0xffe0a000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000 0x1000000 0x0 0x00000000 0 0xfee00000 0x0 0x00010000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <26 2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0000 0x0 0x0 0x4 &mpic 0x3 0x1 >; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x2000000 0x0 0x80000000 0x2000000 0x0 0x80000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x10000>; }; }; };