2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
130 #include <sys/turnstile.h>
131 #include <sys/vmem.h>
132 #include <sys/vmmeter.h>
133 #include <sys/sched.h>
134 #include <sys/sysctl.h>
142 #include <vm/vm_param.h>
143 #include <vm/vm_kern.h>
144 #include <vm/vm_page.h>
145 #include <vm/vm_map.h>
146 #include <vm/vm_object.h>
147 #include <vm/vm_extern.h>
148 #include <vm/vm_pageout.h>
149 #include <vm/vm_pager.h>
150 #include <vm/vm_phys.h>
151 #include <vm/vm_radix.h>
152 #include <vm/vm_reserv.h>
153 #include <vm/vm_dumpset.h>
156 #include <machine/intr_machdep.h>
157 #include <x86/apicvar.h>
158 #include <x86/ifunc.h>
159 #include <machine/cpu.h>
160 #include <machine/cputypes.h>
161 #include <machine/intr_machdep.h>
162 #include <machine/md_var.h>
163 #include <machine/pcb.h>
164 #include <machine/specialreg.h>
166 #include <machine/smp.h>
168 #include <machine/sysarch.h>
169 #include <machine/tss.h>
172 #define PMAP_MEMDOM MAXMEMDOM
174 #define PMAP_MEMDOM 1
177 static __inline boolean_t
178 pmap_type_guest(pmap_t pmap)
181 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
184 static __inline boolean_t
185 pmap_emulate_ad_bits(pmap_t pmap)
188 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
191 static __inline pt_entry_t
192 pmap_valid_bit(pmap_t pmap)
196 switch (pmap->pm_type) {
202 if (pmap_emulate_ad_bits(pmap))
203 mask = EPT_PG_EMUL_V;
208 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
214 static __inline pt_entry_t
215 pmap_rw_bit(pmap_t pmap)
219 switch (pmap->pm_type) {
225 if (pmap_emulate_ad_bits(pmap))
226 mask = EPT_PG_EMUL_RW;
231 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
237 static pt_entry_t pg_g;
239 static __inline pt_entry_t
240 pmap_global_bit(pmap_t pmap)
244 switch (pmap->pm_type) {
253 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
259 static __inline pt_entry_t
260 pmap_accessed_bit(pmap_t pmap)
264 switch (pmap->pm_type) {
270 if (pmap_emulate_ad_bits(pmap))
276 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
282 static __inline pt_entry_t
283 pmap_modified_bit(pmap_t pmap)
287 switch (pmap->pm_type) {
293 if (pmap_emulate_ad_bits(pmap))
299 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
305 static __inline pt_entry_t
306 pmap_pku_mask_bit(pmap_t pmap)
309 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
312 #if !defined(DIAGNOSTIC)
313 #ifdef __GNUC_GNU_INLINE__
314 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
316 #define PMAP_INLINE extern inline
323 #define PV_STAT(x) do { x ; } while (0)
325 #define PV_STAT(x) do { } while (0)
330 #define pa_index(pa) ({ \
331 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
332 ("address %lx beyond the last segment", (pa))); \
335 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
336 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
337 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
338 struct rwlock *_lock; \
339 if (__predict_false((pa) > pmap_last_pa)) \
340 _lock = &pv_dummy_large.pv_lock; \
342 _lock = &(pa_to_pmdp(pa)->pv_lock); \
346 #define pa_index(pa) ((pa) >> PDRSHIFT)
347 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
349 #define NPV_LIST_LOCKS MAXCPU
351 #define PHYS_TO_PV_LIST_LOCK(pa) \
352 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
355 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
356 struct rwlock **_lockp = (lockp); \
357 struct rwlock *_new_lock; \
359 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
360 if (_new_lock != *_lockp) { \
361 if (*_lockp != NULL) \
362 rw_wunlock(*_lockp); \
363 *_lockp = _new_lock; \
368 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
369 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
371 #define RELEASE_PV_LIST_LOCK(lockp) do { \
372 struct rwlock **_lockp = (lockp); \
374 if (*_lockp != NULL) { \
375 rw_wunlock(*_lockp); \
380 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
381 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
383 struct pmap kernel_pmap_store;
385 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
386 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
389 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
390 "Number of kernel page table pages allocated on bootup");
393 vm_paddr_t dmaplimit;
394 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
397 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
398 "VM/pmap parameters");
400 static int pg_ps_enabled = 1;
401 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
402 &pg_ps_enabled, 0, "Are large page mappings enabled?");
404 int __read_frequently la57 = 0;
405 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
407 "5-level paging for host is enabled");
410 pmap_is_la57(pmap_t pmap)
412 if (pmap->pm_type == PT_X86)
414 return (false); /* XXXKIB handle EPT */
417 #define PAT_INDEX_SIZE 8
418 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
420 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
421 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
422 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
423 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
424 u_int64_t KPML5phys; /* phys addr of kernel level 5,
427 static pml4_entry_t *kernel_pml4;
428 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
429 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
430 static int ndmpdpphys; /* number of DMPDPphys pages */
432 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
435 * pmap_mapdev support pre initialization (i.e. console)
437 #define PMAP_PREINIT_MAPPING_COUNT 8
438 static struct pmap_preinit_mapping {
443 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
444 static int pmap_initialized;
447 * Data for the pv entry allocation mechanism.
448 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
452 pc_to_domain(struct pv_chunk *pc)
455 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
459 pc_to_domain(struct pv_chunk *pc __unused)
466 struct pv_chunks_list {
468 TAILQ_HEAD(pch, pv_chunk) pvc_list;
470 } __aligned(CACHE_LINE_SIZE);
472 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
475 struct pmap_large_md_page {
476 struct rwlock pv_lock;
477 struct md_page pv_page;
480 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
481 #define pv_dummy pv_dummy_large.pv_page
482 __read_mostly static struct pmap_large_md_page *pv_table;
483 __read_mostly vm_paddr_t pmap_last_pa;
485 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
486 static u_long pv_invl_gen[NPV_LIST_LOCKS];
487 static struct md_page *pv_table;
488 static struct md_page pv_dummy;
492 * All those kernel PT submaps that BSD is so fond of
494 pt_entry_t *CMAP1 = NULL;
496 static vm_offset_t qframe = 0;
497 static struct mtx qframe_mtx;
499 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
501 static vmem_t *large_vmem;
502 static u_int lm_ents;
503 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
504 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
506 int pmap_pcid_enabled = 1;
507 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
508 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
509 int invpcid_works = 0;
510 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
511 "Is the invpcid instruction available ?");
513 int __read_frequently pti = 0;
514 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
516 "Page Table Isolation enabled");
517 static vm_object_t pti_obj;
518 static pml4_entry_t *pti_pml4;
519 static vm_pindex_t pti_pg_idx;
520 static bool pti_finalized;
522 struct pmap_pkru_range {
523 struct rs_el pkru_rs_el;
528 static uma_zone_t pmap_pkru_ranges_zone;
529 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
530 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
531 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
532 static void *pkru_dup_range(void *ctx, void *data);
533 static void pkru_free_range(void *ctx, void *node);
534 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
535 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
536 static void pmap_pkru_deassign_all(pmap_t pmap);
539 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
546 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
548 return (sysctl_handle_64(oidp, &res, 0, req));
550 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
551 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
552 "Count of saved TLB context on switch");
554 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
555 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
556 static struct mtx invl_gen_mtx;
557 /* Fake lock object to satisfy turnstiles interface. */
558 static struct lock_object invl_gen_ts = {
561 static struct pmap_invl_gen pmap_invl_gen_head = {
565 static u_long pmap_invl_gen = 1;
566 static int pmap_invl_waiters;
567 static struct callout pmap_invl_callout;
568 static bool pmap_invl_callout_inited;
570 #define PMAP_ASSERT_NOT_IN_DI() \
571 KASSERT(pmap_not_in_di(), ("DI already started"))
578 if ((cpu_feature2 & CPUID2_CX16) == 0)
581 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
586 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
590 locked = pmap_di_locked();
591 return (sysctl_handle_int(oidp, &locked, 0, req));
593 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
594 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
595 "Locked delayed invalidation");
597 static bool pmap_not_in_di_l(void);
598 static bool pmap_not_in_di_u(void);
599 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
602 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
606 pmap_not_in_di_l(void)
608 struct pmap_invl_gen *invl_gen;
610 invl_gen = &curthread->td_md.md_invl_gen;
611 return (invl_gen->gen == 0);
615 pmap_thread_init_invl_gen_l(struct thread *td)
617 struct pmap_invl_gen *invl_gen;
619 invl_gen = &td->td_md.md_invl_gen;
624 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
626 struct turnstile *ts;
628 ts = turnstile_trywait(&invl_gen_ts);
629 if (*m_gen > atomic_load_long(invl_gen))
630 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
632 turnstile_cancel(ts);
636 pmap_delayed_invl_finish_unblock(u_long new_gen)
638 struct turnstile *ts;
640 turnstile_chain_lock(&invl_gen_ts);
641 ts = turnstile_lookup(&invl_gen_ts);
643 pmap_invl_gen = new_gen;
645 turnstile_broadcast(ts, TS_SHARED_QUEUE);
646 turnstile_unpend(ts);
648 turnstile_chain_unlock(&invl_gen_ts);
652 * Start a new Delayed Invalidation (DI) block of code, executed by
653 * the current thread. Within a DI block, the current thread may
654 * destroy both the page table and PV list entries for a mapping and
655 * then release the corresponding PV list lock before ensuring that
656 * the mapping is flushed from the TLBs of any processors with the
660 pmap_delayed_invl_start_l(void)
662 struct pmap_invl_gen *invl_gen;
665 invl_gen = &curthread->td_md.md_invl_gen;
666 PMAP_ASSERT_NOT_IN_DI();
667 mtx_lock(&invl_gen_mtx);
668 if (LIST_EMPTY(&pmap_invl_gen_tracker))
669 currgen = pmap_invl_gen;
671 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
672 invl_gen->gen = currgen + 1;
673 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
674 mtx_unlock(&invl_gen_mtx);
678 * Finish the DI block, previously started by the current thread. All
679 * required TLB flushes for the pages marked by
680 * pmap_delayed_invl_page() must be finished before this function is
683 * This function works by bumping the global DI generation number to
684 * the generation number of the current thread's DI, unless there is a
685 * pending DI that started earlier. In the latter case, bumping the
686 * global DI generation number would incorrectly signal that the
687 * earlier DI had finished. Instead, this function bumps the earlier
688 * DI's generation number to match the generation number of the
689 * current thread's DI.
692 pmap_delayed_invl_finish_l(void)
694 struct pmap_invl_gen *invl_gen, *next;
696 invl_gen = &curthread->td_md.md_invl_gen;
697 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
698 mtx_lock(&invl_gen_mtx);
699 next = LIST_NEXT(invl_gen, link);
701 pmap_delayed_invl_finish_unblock(invl_gen->gen);
703 next->gen = invl_gen->gen;
704 LIST_REMOVE(invl_gen, link);
705 mtx_unlock(&invl_gen_mtx);
710 pmap_not_in_di_u(void)
712 struct pmap_invl_gen *invl_gen;
714 invl_gen = &curthread->td_md.md_invl_gen;
715 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
719 pmap_thread_init_invl_gen_u(struct thread *td)
721 struct pmap_invl_gen *invl_gen;
723 invl_gen = &td->td_md.md_invl_gen;
725 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
729 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
731 uint64_t new_high, new_low, old_high, old_low;
734 old_low = new_low = 0;
735 old_high = new_high = (uintptr_t)0;
737 __asm volatile("lock;cmpxchg16b\t%1"
738 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
739 : "b"(new_low), "c" (new_high)
742 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
745 out->next = (void *)old_high;
748 out->next = (void *)new_high;
754 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
755 struct pmap_invl_gen *new_val)
757 uint64_t new_high, new_low, old_high, old_low;
760 new_low = new_val->gen;
761 new_high = (uintptr_t)new_val->next;
762 old_low = old_val->gen;
763 old_high = (uintptr_t)old_val->next;
765 __asm volatile("lock;cmpxchg16b\t%1"
766 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
767 : "b"(new_low), "c" (new_high)
773 static long invl_start_restart;
774 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
775 &invl_start_restart, 0,
777 static long invl_finish_restart;
778 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
779 &invl_finish_restart, 0,
781 static int invl_max_qlen;
782 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
787 #define di_delay locks_delay
790 pmap_delayed_invl_start_u(void)
792 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
794 struct lock_delay_arg lda;
802 invl_gen = &td->td_md.md_invl_gen;
803 PMAP_ASSERT_NOT_IN_DI();
804 lock_delay_arg_init(&lda, &di_delay);
805 invl_gen->saved_pri = 0;
806 pri = td->td_base_pri;
809 pri = td->td_base_pri;
811 invl_gen->saved_pri = pri;
818 for (p = &pmap_invl_gen_head;; p = prev.next) {
820 prevl = (uintptr_t)atomic_load_ptr(&p->next);
821 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
822 PV_STAT(atomic_add_long(&invl_start_restart, 1));
828 prev.next = (void *)prevl;
831 if ((ii = invl_max_qlen) < i)
832 atomic_cmpset_int(&invl_max_qlen, ii, i);
835 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
836 PV_STAT(atomic_add_long(&invl_start_restart, 1));
841 new_prev.gen = prev.gen;
842 new_prev.next = invl_gen;
843 invl_gen->gen = prev.gen + 1;
845 /* Formal fence between store to invl->gen and updating *p. */
846 atomic_thread_fence_rel();
849 * After inserting an invl_gen element with invalid bit set,
850 * this thread blocks any other thread trying to enter the
851 * delayed invalidation block. Do not allow to remove us from
852 * the CPU, because it causes starvation for other threads.
857 * ABA for *p is not possible there, since p->gen can only
858 * increase. So if the *p thread finished its di, then
859 * started a new one and got inserted into the list at the
860 * same place, its gen will appear greater than the previously
863 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
865 PV_STAT(atomic_add_long(&invl_start_restart, 1));
871 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
872 * invl_gen->next, allowing other threads to iterate past us.
873 * pmap_di_store_invl() provides fence between the generation
874 * write and the update of next.
876 invl_gen->next = NULL;
881 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
882 struct pmap_invl_gen *p)
884 struct pmap_invl_gen prev, new_prev;
888 * Load invl_gen->gen after setting invl_gen->next
889 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
890 * generations to propagate to our invl_gen->gen. Lock prefix
891 * in atomic_set_ptr() worked as seq_cst fence.
893 mygen = atomic_load_long(&invl_gen->gen);
895 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
898 KASSERT(prev.gen < mygen,
899 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
900 new_prev.gen = mygen;
901 new_prev.next = (void *)((uintptr_t)invl_gen->next &
902 ~PMAP_INVL_GEN_NEXT_INVALID);
904 /* Formal fence between load of prev and storing update to it. */
905 atomic_thread_fence_rel();
907 return (pmap_di_store_invl(p, &prev, &new_prev));
911 pmap_delayed_invl_finish_u(void)
913 struct pmap_invl_gen *invl_gen, *p;
915 struct lock_delay_arg lda;
919 invl_gen = &td->td_md.md_invl_gen;
920 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
921 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
922 ("missed invl_start: INVALID"));
923 lock_delay_arg_init(&lda, &di_delay);
926 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
927 prevl = (uintptr_t)atomic_load_ptr(&p->next);
928 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
929 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
933 if ((void *)prevl == invl_gen)
938 * It is legitimate to not find ourself on the list if a
939 * thread before us finished its DI and started it again.
941 if (__predict_false(p == NULL)) {
942 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
948 atomic_set_ptr((uintptr_t *)&invl_gen->next,
949 PMAP_INVL_GEN_NEXT_INVALID);
950 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
951 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
952 PMAP_INVL_GEN_NEXT_INVALID);
954 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
959 if (atomic_load_int(&pmap_invl_waiters) > 0)
960 pmap_delayed_invl_finish_unblock(0);
961 if (invl_gen->saved_pri != 0) {
963 sched_prio(td, invl_gen->saved_pri);
969 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
971 struct pmap_invl_gen *p, *pn;
976 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
978 nextl = (uintptr_t)atomic_load_ptr(&p->next);
979 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
980 td = first ? NULL : __containerof(p, struct thread,
982 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
983 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
984 td != NULL ? td->td_tid : -1);
990 static long invl_wait;
991 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
992 "Number of times DI invalidation blocked pmap_remove_all/write");
993 static long invl_wait_slow;
994 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
995 "Number of slow invalidation waits for lockless DI");
1000 pmap_delayed_invl_genp(vm_page_t m)
1005 pa = VM_PAGE_TO_PHYS(m);
1006 if (__predict_false((pa) > pmap_last_pa))
1007 gen = &pv_dummy_large.pv_invl_gen;
1009 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1015 pmap_delayed_invl_genp(vm_page_t m)
1018 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1023 pmap_delayed_invl_callout_func(void *arg __unused)
1026 if (atomic_load_int(&pmap_invl_waiters) == 0)
1028 pmap_delayed_invl_finish_unblock(0);
1032 pmap_delayed_invl_callout_init(void *arg __unused)
1035 if (pmap_di_locked())
1037 callout_init(&pmap_invl_callout, 1);
1038 pmap_invl_callout_inited = true;
1040 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1041 pmap_delayed_invl_callout_init, NULL);
1044 * Ensure that all currently executing DI blocks, that need to flush
1045 * TLB for the given page m, actually flushed the TLB at the time the
1046 * function returned. If the page m has an empty PV list and we call
1047 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1048 * valid mapping for the page m in either its page table or TLB.
1050 * This function works by blocking until the global DI generation
1051 * number catches up with the generation number associated with the
1052 * given page m and its PV list. Since this function's callers
1053 * typically own an object lock and sometimes own a page lock, it
1054 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1058 pmap_delayed_invl_wait_l(vm_page_t m)
1062 bool accounted = false;
1065 m_gen = pmap_delayed_invl_genp(m);
1066 while (*m_gen > pmap_invl_gen) {
1069 atomic_add_long(&invl_wait, 1);
1073 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1078 pmap_delayed_invl_wait_u(vm_page_t m)
1081 struct lock_delay_arg lda;
1085 m_gen = pmap_delayed_invl_genp(m);
1086 lock_delay_arg_init(&lda, &di_delay);
1087 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1088 if (fast || !pmap_invl_callout_inited) {
1089 PV_STAT(atomic_add_long(&invl_wait, 1));
1094 * The page's invalidation generation number
1095 * is still below the current thread's number.
1096 * Prepare to block so that we do not waste
1097 * CPU cycles or worse, suffer livelock.
1099 * Since it is impossible to block without
1100 * racing with pmap_delayed_invl_finish_u(),
1101 * prepare for the race by incrementing
1102 * pmap_invl_waiters and arming a 1-tick
1103 * callout which will unblock us if we lose
1106 atomic_add_int(&pmap_invl_waiters, 1);
1109 * Re-check the current thread's invalidation
1110 * generation after incrementing
1111 * pmap_invl_waiters, so that there is no race
1112 * with pmap_delayed_invl_finish_u() setting
1113 * the page generation and checking
1114 * pmap_invl_waiters. The only race allowed
1115 * is for a missed unblock, which is handled
1119 atomic_load_long(&pmap_invl_gen_head.gen)) {
1120 callout_reset(&pmap_invl_callout, 1,
1121 pmap_delayed_invl_callout_func, NULL);
1122 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1123 pmap_delayed_invl_wait_block(m_gen,
1124 &pmap_invl_gen_head.gen);
1126 atomic_add_int(&pmap_invl_waiters, -1);
1131 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1134 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1135 pmap_thread_init_invl_gen_u);
1138 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1141 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1142 pmap_delayed_invl_start_u);
1145 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1148 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1149 pmap_delayed_invl_finish_u);
1152 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1155 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1156 pmap_delayed_invl_wait_u);
1160 * Mark the page m's PV list as participating in the current thread's
1161 * DI block. Any threads concurrently using m's PV list to remove or
1162 * restrict all mappings to m will wait for the current thread's DI
1163 * block to complete before proceeding.
1165 * The function works by setting the DI generation number for m's PV
1166 * list to at least the DI generation number of the current thread.
1167 * This forces a caller of pmap_delayed_invl_wait() to block until
1168 * current thread calls pmap_delayed_invl_finish().
1171 pmap_delayed_invl_page(vm_page_t m)
1175 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1176 gen = curthread->td_md.md_invl_gen.gen;
1179 m_gen = pmap_delayed_invl_genp(m);
1187 static caddr_t crashdumpmap;
1190 * Internal flags for pmap_enter()'s helper functions.
1192 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1193 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1196 * Internal flags for pmap_mapdev_internal() and
1197 * pmap_change_props_locked().
1199 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1200 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1201 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1203 TAILQ_HEAD(pv_chunklist, pv_chunk);
1205 static void free_pv_chunk(struct pv_chunk *pc);
1206 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1207 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1208 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1209 static int popcnt_pc_map_pq(uint64_t *map);
1210 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1211 static void reserve_pv_entries(pmap_t pmap, int needed,
1212 struct rwlock **lockp);
1213 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1214 struct rwlock **lockp);
1215 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1216 u_int flags, struct rwlock **lockp);
1217 #if VM_NRESERVLEVEL > 0
1218 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1219 struct rwlock **lockp);
1221 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1222 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1225 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1226 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1227 vm_prot_t prot, int mode, int flags);
1228 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1229 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1230 vm_offset_t va, struct rwlock **lockp);
1231 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1233 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1234 vm_prot_t prot, struct rwlock **lockp);
1235 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1236 u_int flags, vm_page_t m, struct rwlock **lockp);
1237 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1238 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1239 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1240 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1241 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1243 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1245 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1247 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1248 static vm_page_t pmap_large_map_getptp_unlocked(void);
1249 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1250 #if VM_NRESERVLEVEL > 0
1251 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1252 struct rwlock **lockp);
1254 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1256 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1257 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1259 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1260 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1261 static void pmap_pti_wire_pte(void *pte);
1262 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1263 struct spglist *free, struct rwlock **lockp);
1264 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1265 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1266 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1267 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1268 struct spglist *free);
1269 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1270 pd_entry_t *pde, struct spglist *free,
1271 struct rwlock **lockp);
1272 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1273 vm_page_t m, struct rwlock **lockp);
1274 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1276 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1278 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1279 struct rwlock **lockp, vm_offset_t va);
1280 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1281 struct rwlock **lockp);
1282 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1283 struct rwlock **lockp);
1285 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1286 struct spglist *free);
1287 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1289 /********************/
1290 /* Inline functions */
1291 /********************/
1294 * Return a non-clipped indexes for a given VA, which are page table
1295 * pages indexes at the corresponding level.
1297 static __inline vm_pindex_t
1298 pmap_pde_pindex(vm_offset_t va)
1300 return (va >> PDRSHIFT);
1303 static __inline vm_pindex_t
1304 pmap_pdpe_pindex(vm_offset_t va)
1306 return (NUPDE + (va >> PDPSHIFT));
1309 static __inline vm_pindex_t
1310 pmap_pml4e_pindex(vm_offset_t va)
1312 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1315 static __inline vm_pindex_t
1316 pmap_pml5e_pindex(vm_offset_t va)
1318 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1321 static __inline pml4_entry_t *
1322 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1325 MPASS(pmap_is_la57(pmap));
1326 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1329 static __inline pml4_entry_t *
1330 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1333 MPASS(pmap_is_la57(pmap));
1334 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1337 static __inline pml4_entry_t *
1338 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1340 pml4_entry_t *pml4e;
1342 /* XXX MPASS(pmap_is_la57(pmap); */
1343 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1344 return (&pml4e[pmap_pml4e_index(va)]);
1347 /* Return a pointer to the PML4 slot that corresponds to a VA */
1348 static __inline pml4_entry_t *
1349 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1351 pml5_entry_t *pml5e;
1352 pml4_entry_t *pml4e;
1355 if (pmap_is_la57(pmap)) {
1356 pml5e = pmap_pml5e(pmap, va);
1357 PG_V = pmap_valid_bit(pmap);
1358 if ((*pml5e & PG_V) == 0)
1360 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1362 pml4e = pmap->pm_pmltop;
1364 return (&pml4e[pmap_pml4e_index(va)]);
1367 static __inline pml4_entry_t *
1368 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1370 MPASS(!pmap_is_la57(pmap));
1371 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1374 /* Return a pointer to the PDP slot that corresponds to a VA */
1375 static __inline pdp_entry_t *
1376 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1380 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1381 return (&pdpe[pmap_pdpe_index(va)]);
1384 /* Return a pointer to the PDP slot that corresponds to a VA */
1385 static __inline pdp_entry_t *
1386 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1388 pml4_entry_t *pml4e;
1391 PG_V = pmap_valid_bit(pmap);
1392 pml4e = pmap_pml4e(pmap, va);
1393 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1395 return (pmap_pml4e_to_pdpe(pml4e, va));
1398 /* Return a pointer to the PD slot that corresponds to a VA */
1399 static __inline pd_entry_t *
1400 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1404 KASSERT((*pdpe & PG_PS) == 0,
1405 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1406 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1407 return (&pde[pmap_pde_index(va)]);
1410 /* Return a pointer to the PD slot that corresponds to a VA */
1411 static __inline pd_entry_t *
1412 pmap_pde(pmap_t pmap, vm_offset_t va)
1417 PG_V = pmap_valid_bit(pmap);
1418 pdpe = pmap_pdpe(pmap, va);
1419 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1421 KASSERT((*pdpe & PG_PS) == 0,
1422 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1423 return (pmap_pdpe_to_pde(pdpe, va));
1426 /* Return a pointer to the PT slot that corresponds to a VA */
1427 static __inline pt_entry_t *
1428 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1432 KASSERT((*pde & PG_PS) == 0,
1433 ("%s: pde %#lx is a leaf", __func__, *pde));
1434 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1435 return (&pte[pmap_pte_index(va)]);
1438 /* Return a pointer to the PT slot that corresponds to a VA */
1439 static __inline pt_entry_t *
1440 pmap_pte(pmap_t pmap, vm_offset_t va)
1445 PG_V = pmap_valid_bit(pmap);
1446 pde = pmap_pde(pmap, va);
1447 if (pde == NULL || (*pde & PG_V) == 0)
1449 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1450 return ((pt_entry_t *)pde);
1451 return (pmap_pde_to_pte(pde, va));
1454 static __inline void
1455 pmap_resident_count_inc(pmap_t pmap, int count)
1458 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1459 pmap->pm_stats.resident_count += count;
1462 static __inline void
1463 pmap_resident_count_dec(pmap_t pmap, int count)
1466 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1467 KASSERT(pmap->pm_stats.resident_count >= count,
1468 ("pmap %p resident count underflow %ld %d", pmap,
1469 pmap->pm_stats.resident_count, count));
1470 pmap->pm_stats.resident_count -= count;
1473 PMAP_INLINE pt_entry_t *
1474 vtopte(vm_offset_t va)
1478 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1481 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1482 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1483 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1485 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1486 NPML4EPGSHIFT)) - 1);
1487 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1491 static __inline pd_entry_t *
1492 vtopde(vm_offset_t va)
1496 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1499 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1500 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1501 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1503 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1504 NPML4EPGSHIFT)) - 1);
1505 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1510 allocpages(vm_paddr_t *firstaddr, int n)
1515 bzero((void *)ret, n * PAGE_SIZE);
1516 *firstaddr += n * PAGE_SIZE;
1520 CTASSERT(powerof2(NDMPML4E));
1522 /* number of kernel PDP slots */
1523 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1526 nkpt_init(vm_paddr_t addr)
1533 pt_pages = howmany(addr, 1 << PDRSHIFT);
1534 pt_pages += NKPDPE(pt_pages);
1537 * Add some slop beyond the bare minimum required for bootstrapping
1540 * This is quite important when allocating KVA for kernel modules.
1541 * The modules are required to be linked in the negative 2GB of
1542 * the address space. If we run out of KVA in this region then
1543 * pmap_growkernel() will need to allocate page table pages to map
1544 * the entire 512GB of KVA space which is an unnecessary tax on
1547 * Secondly, device memory mapped as part of setting up the low-
1548 * level console(s) is taken from KVA, starting at virtual_avail.
1549 * This is because cninit() is called after pmap_bootstrap() but
1550 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1553 pt_pages += 32; /* 64MB additional slop. */
1559 * Returns the proper write/execute permission for a physical page that is
1560 * part of the initial boot allocations.
1562 * If the page has kernel text, it is marked as read-only. If the page has
1563 * kernel read-only data, it is marked as read-only/not-executable. If the
1564 * page has only read-write data, it is marked as read-write/not-executable.
1565 * If the page is below/above the kernel range, it is marked as read-write.
1567 * This function operates on 2M pages, since we map the kernel space that
1570 static inline pt_entry_t
1571 bootaddr_rwx(vm_paddr_t pa)
1575 * The kernel is loaded at a 2MB-aligned address, and memory below that
1576 * need not be executable. The .bss section is padded to a 2MB
1577 * boundary, so memory following the kernel need not be executable
1578 * either. Preloaded kernel modules have their mapping permissions
1579 * fixed up by the linker.
1581 if (pa < trunc_2mpage(btext - KERNBASE) ||
1582 pa >= trunc_2mpage(_end - KERNBASE))
1583 return (X86_PG_RW | pg_nx);
1586 * The linker should ensure that the read-only and read-write
1587 * portions don't share the same 2M page, so this shouldn't
1588 * impact read-only data. However, in any case, any page with
1589 * read-write data needs to be read-write.
1591 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1592 return (X86_PG_RW | pg_nx);
1595 * Mark any 2M page containing kernel text as read-only. Mark
1596 * other pages with read-only data as read-only and not executable.
1597 * (It is likely a small portion of the read-only data section will
1598 * be marked as read-only, but executable. This should be acceptable
1599 * since the read-only protection will keep the data from changing.)
1600 * Note that fixups to the .text section will still work until we
1603 if (pa < round_2mpage(etext - KERNBASE))
1609 create_pagetables(vm_paddr_t *firstaddr)
1611 int i, j, ndm1g, nkpdpe, nkdmpde;
1615 uint64_t DMPDkernphys;
1617 /* Allocate page table pages for the direct map */
1618 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1619 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1621 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1622 if (ndmpdpphys > NDMPML4E) {
1624 * Each NDMPML4E allows 512 GB, so limit to that,
1625 * and then readjust ndmpdp and ndmpdpphys.
1627 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1628 Maxmem = atop(NDMPML4E * NBPML4);
1629 ndmpdpphys = NDMPML4E;
1630 ndmpdp = NDMPML4E * NPDEPG;
1632 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1634 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1636 * Calculate the number of 1G pages that will fully fit in
1639 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1642 * Allocate 2M pages for the kernel. These will be used in
1643 * place of the first one or more 1G pages from ndm1g.
1645 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1646 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1649 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1650 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1652 /* Allocate pages */
1653 KPML4phys = allocpages(firstaddr, 1);
1654 KPDPphys = allocpages(firstaddr, NKPML4E);
1657 * Allocate the initial number of kernel page table pages required to
1658 * bootstrap. We defer this until after all memory-size dependent
1659 * allocations are done (e.g. direct map), so that we don't have to
1660 * build in too much slop in our estimate.
1662 * Note that when NKPML4E > 1, we have an empty page underneath
1663 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1664 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1666 nkpt_init(*firstaddr);
1667 nkpdpe = NKPDPE(nkpt);
1669 KPTphys = allocpages(firstaddr, nkpt);
1670 KPDphys = allocpages(firstaddr, nkpdpe);
1673 * Connect the zero-filled PT pages to their PD entries. This
1674 * implicitly maps the PT pages at their correct locations within
1677 pd_p = (pd_entry_t *)KPDphys;
1678 for (i = 0; i < nkpt; i++)
1679 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1682 * Map from physical address zero to the end of loader preallocated
1683 * memory using 2MB pages. This replaces some of the PD entries
1686 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1687 /* Preset PG_M and PG_A because demotion expects it. */
1688 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1689 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1692 * Because we map the physical blocks in 2M pages, adjust firstaddr
1693 * to record the physical blocks we've actually mapped into kernel
1694 * virtual address space.
1696 if (*firstaddr < round_2mpage(KERNend))
1697 *firstaddr = round_2mpage(KERNend);
1699 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1700 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1701 for (i = 0; i < nkpdpe; i++)
1702 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1705 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1706 * the end of physical memory is not aligned to a 1GB page boundary,
1707 * then the residual physical memory is mapped with 2MB pages. Later,
1708 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1709 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1710 * that are partially used.
1712 pd_p = (pd_entry_t *)DMPDphys;
1713 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1714 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1715 /* Preset PG_M and PG_A because demotion expects it. */
1716 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1717 X86_PG_M | X86_PG_A | pg_nx;
1719 pdp_p = (pdp_entry_t *)DMPDPphys;
1720 for (i = 0; i < ndm1g; i++) {
1721 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1722 /* Preset PG_M and PG_A because demotion expects it. */
1723 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1724 X86_PG_M | X86_PG_A | pg_nx;
1726 for (j = 0; i < ndmpdp; i++, j++) {
1727 pdp_p[i] = DMPDphys + ptoa(j);
1728 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1732 * Instead of using a 1G page for the memory containing the kernel,
1733 * use 2M pages with read-only and no-execute permissions. (If using 1G
1734 * pages, this will partially overwrite the PDPEs above.)
1737 pd_p = (pd_entry_t *)DMPDkernphys;
1738 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1739 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1740 X86_PG_M | X86_PG_A | pg_nx |
1741 bootaddr_rwx(i << PDRSHIFT);
1742 for (i = 0; i < nkdmpde; i++)
1743 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1747 /* And recursively map PML4 to itself in order to get PTmap */
1748 p4_p = (pml4_entry_t *)KPML4phys;
1749 p4_p[PML4PML4I] = KPML4phys;
1750 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1752 /* Connect the Direct Map slot(s) up to the PML4. */
1753 for (i = 0; i < ndmpdpphys; i++) {
1754 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1755 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1758 /* Connect the KVA slots up to the PML4 */
1759 for (i = 0; i < NKPML4E; i++) {
1760 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1761 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1764 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1768 * Bootstrap the system enough to run with virtual memory.
1770 * On amd64 this is called after mapping has already been enabled
1771 * and just syncs the pmap module with what has already been done.
1772 * [We can't call it easily with mapping off since the kernel is not
1773 * mapped with PA == VA, hence we would have to relocate every address
1774 * from the linked base (virtual) address "KERNBASE" to the actual
1775 * (physical) address starting relative to 0]
1778 pmap_bootstrap(vm_paddr_t *firstaddr)
1781 pt_entry_t *pte, *pcpu_pte;
1782 struct region_descriptor r_gdt;
1783 uint64_t cr4, pcpu_phys;
1787 KERNend = *firstaddr;
1788 res = atop(KERNend - (vm_paddr_t)kernphys);
1794 * Create an initial set of page tables to run the kernel in.
1796 create_pagetables(firstaddr);
1798 pcpu_phys = allocpages(firstaddr, MAXCPU);
1801 * Add a physical memory segment (vm_phys_seg) corresponding to the
1802 * preallocated kernel page table pages so that vm_page structures
1803 * representing these pages will be created. The vm_page structures
1804 * are required for promotion of the corresponding kernel virtual
1805 * addresses to superpage mappings.
1807 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1810 * Account for the virtual addresses mapped by create_pagetables().
1812 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1813 virtual_end = VM_MAX_KERNEL_ADDRESS;
1816 * Enable PG_G global pages, then switch to the kernel page
1817 * table from the bootstrap page table. After the switch, it
1818 * is possible to enable SMEP and SMAP since PG_U bits are
1824 load_cr3(KPML4phys);
1825 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1827 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1832 * Initialize the kernel pmap (which is statically allocated).
1833 * Count bootstrap data as being resident in case any of this data is
1834 * later unmapped (using pmap_remove()) and freed.
1836 PMAP_LOCK_INIT(kernel_pmap);
1837 kernel_pmap->pm_pmltop = kernel_pml4;
1838 kernel_pmap->pm_cr3 = KPML4phys;
1839 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1840 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1841 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1842 kernel_pmap->pm_stats.resident_count = res;
1843 kernel_pmap->pm_flags = pmap_flags;
1846 * Initialize the TLB invalidations generation number lock.
1848 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1851 * Reserve some special page table entries/VA space for temporary
1854 #define SYSMAP(c, p, v, n) \
1855 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1861 * Crashdump maps. The first page is reused as CMAP1 for the
1864 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1865 CADDR1 = crashdumpmap;
1867 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1870 for (i = 0; i < MAXCPU; i++) {
1871 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1872 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1876 * Re-initialize PCPU area for BSP after switching.
1877 * Make hardware use gdt and common_tss from the new PCPU.
1879 STAILQ_INIT(&cpuhead);
1880 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1881 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1882 amd64_bsp_pcpu_init1(&__pcpu[0]);
1883 amd64_bsp_ist_init(&__pcpu[0]);
1884 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1886 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1887 sizeof(struct user_segment_descriptor));
1888 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1889 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1890 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1891 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1892 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1894 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1895 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1896 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1897 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1900 * Initialize the PAT MSR.
1901 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1902 * side-effect, invalidates stale PG_G TLB entries that might
1903 * have been created in our pre-boot environment.
1907 /* Initialize TLB Context Id. */
1908 if (pmap_pcid_enabled) {
1909 for (i = 0; i < MAXCPU; i++) {
1910 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1911 kernel_pmap->pm_pcids[i].pm_gen = 1;
1915 * PMAP_PCID_KERN + 1 is used for initialization of
1916 * proc0 pmap. The pmap' pcid state might be used by
1917 * EFIRT entry before first context switch, so it
1918 * needs to be valid.
1920 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1921 PCPU_SET(pcid_gen, 1);
1924 * pcpu area for APs is zeroed during AP startup.
1925 * pc_pcid_next and pc_pcid_gen are initialized by AP
1926 * during pcpu setup.
1928 load_cr4(rcr4() | CR4_PCIDE);
1933 * Setup the PAT MSR.
1942 /* Bail if this CPU doesn't implement PAT. */
1943 if ((cpu_feature & CPUID_PAT) == 0)
1946 /* Set default PAT index table. */
1947 for (i = 0; i < PAT_INDEX_SIZE; i++)
1949 pat_index[PAT_WRITE_BACK] = 0;
1950 pat_index[PAT_WRITE_THROUGH] = 1;
1951 pat_index[PAT_UNCACHEABLE] = 3;
1952 pat_index[PAT_WRITE_COMBINING] = 6;
1953 pat_index[PAT_WRITE_PROTECTED] = 5;
1954 pat_index[PAT_UNCACHED] = 2;
1957 * Initialize default PAT entries.
1958 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1959 * Program 5 and 6 as WP and WC.
1961 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1962 * mapping for a 2M page uses a PAT value with the bit 3 set due
1963 * to its overload with PG_PS.
1965 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1966 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1967 PAT_VALUE(2, PAT_UNCACHED) |
1968 PAT_VALUE(3, PAT_UNCACHEABLE) |
1969 PAT_VALUE(4, PAT_WRITE_BACK) |
1970 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1971 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1972 PAT_VALUE(7, PAT_UNCACHEABLE);
1976 load_cr4(cr4 & ~CR4_PGE);
1978 /* Disable caches (CD = 1, NW = 0). */
1980 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1982 /* Flushes caches and TLBs. */
1986 /* Update PAT and index table. */
1987 wrmsr(MSR_PAT, pat_msr);
1989 /* Flush caches and TLBs again. */
1993 /* Restore caches and PGE. */
1998 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
1999 la57_trampoline_gdt[], la57_trampoline_end[];
2002 pmap_bootstrap_la57(void *arg __unused)
2005 pml5_entry_t *v_pml5;
2006 pml4_entry_t *v_pml4;
2010 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2011 void (*la57_tramp)(uint64_t pml5);
2012 struct region_descriptor r_gdt;
2014 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2016 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2021 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2022 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2024 m_code = vm_page_alloc_contig(NULL, 0,
2025 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2026 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2027 if ((m_code->flags & PG_ZERO) == 0)
2028 pmap_zero_page(m_code);
2029 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2030 m_pml5 = vm_page_alloc_contig(NULL, 0,
2031 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2032 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2033 if ((m_pml5->flags & PG_ZERO) == 0)
2034 pmap_zero_page(m_pml5);
2035 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2036 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2037 m_pml4 = vm_page_alloc_contig(NULL, 0,
2038 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2039 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2040 if ((m_pml4->flags & PG_ZERO) == 0)
2041 pmap_zero_page(m_pml4);
2042 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2043 m_pdp = vm_page_alloc_contig(NULL, 0,
2044 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2045 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2046 if ((m_pdp->flags & PG_ZERO) == 0)
2047 pmap_zero_page(m_pdp);
2048 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2049 m_pd = vm_page_alloc_contig(NULL, 0,
2050 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2051 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2052 if ((m_pd->flags & PG_ZERO) == 0)
2053 pmap_zero_page(m_pd);
2054 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2055 m_pt = vm_page_alloc_contig(NULL, 0,
2056 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2057 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2058 if ((m_pt->flags & PG_ZERO) == 0)
2059 pmap_zero_page(m_pt);
2060 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2063 * Map m_code 1:1, it appears below 4G in KVA due to physical
2064 * address being below 4G. Since kernel KVA is in upper half,
2065 * the pml4e should be zero and free for temporary use.
2067 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2068 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2070 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2071 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2073 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2074 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2076 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2077 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2081 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2082 * entering all existing kernel mappings into level 5 table.
2084 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2085 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2088 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2090 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2091 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2093 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2094 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2098 * Copy and call the 48->57 trampoline, hope we return there, alive.
2100 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2101 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2102 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2103 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2104 la57_tramp(KPML5phys);
2107 * gdt was necessary reset, switch back to our gdt.
2110 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2114 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2115 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2116 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2119 * Now unmap the trampoline, and free the pages.
2120 * Clear pml5 entry used for 1:1 trampoline mapping.
2122 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2123 invlpg((vm_offset_t)v_code);
2124 vm_page_free(m_code);
2125 vm_page_free(m_pdp);
2130 * Recursively map PML5 to itself in order to get PTmap and
2133 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2135 kernel_pmap->pm_cr3 = KPML5phys;
2136 kernel_pmap->pm_pmltop = v_pml5;
2138 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2141 * Initialize a vm_page's machine-dependent fields.
2144 pmap_page_init(vm_page_t m)
2147 TAILQ_INIT(&m->md.pv_list);
2148 m->md.pat_mode = PAT_WRITE_BACK;
2151 static int pmap_allow_2m_x_ept;
2152 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2153 &pmap_allow_2m_x_ept, 0,
2154 "Allow executable superpage mappings in EPT");
2157 pmap_allow_2m_x_ept_recalculate(void)
2160 * SKL002, SKL012S. Since the EPT format is only used by
2161 * Intel CPUs, the vendor check is merely a formality.
2163 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2164 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2165 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2166 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2167 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2168 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2169 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2170 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2171 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2172 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2173 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2174 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2175 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2176 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2177 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2178 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2179 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2180 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2181 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2182 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2183 CPUID_TO_MODEL(cpu_id) == 0x85))))
2184 pmap_allow_2m_x_ept = 1;
2185 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2189 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2192 return (pmap->pm_type != PT_EPT || !executable ||
2193 !pmap_allow_2m_x_ept);
2198 pmap_init_pv_table(void)
2200 struct pmap_large_md_page *pvd;
2202 long start, end, highest, pv_npg;
2203 int domain, i, j, pages;
2206 * We strongly depend on the size being a power of two, so the assert
2207 * is overzealous. However, should the struct be resized to a
2208 * different power of two, the code below needs to be revisited.
2210 CTASSERT((sizeof(*pvd) == 64));
2213 * Calculate the size of the array.
2215 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2216 pv_npg = howmany(pmap_last_pa, NBPDR);
2217 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2219 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2220 if (pv_table == NULL)
2221 panic("%s: kva_alloc failed\n", __func__);
2224 * Iterate physical segments to allocate space for respective pages.
2228 for (i = 0; i < vm_phys_nsegs; i++) {
2229 end = vm_phys_segs[i].end / NBPDR;
2230 domain = vm_phys_segs[i].domain;
2235 start = highest + 1;
2236 pvd = &pv_table[start];
2238 pages = end - start + 1;
2239 s = round_page(pages * sizeof(*pvd));
2240 highest = start + (s / sizeof(*pvd)) - 1;
2242 for (j = 0; j < s; j += PAGE_SIZE) {
2243 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2244 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2246 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2247 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2250 for (j = 0; j < s / sizeof(*pvd); j++) {
2251 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2252 TAILQ_INIT(&pvd->pv_page.pv_list);
2253 pvd->pv_page.pv_gen = 0;
2254 pvd->pv_page.pat_mode = 0;
2255 pvd->pv_invl_gen = 0;
2259 pvd = &pv_dummy_large;
2260 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2261 TAILQ_INIT(&pvd->pv_page.pv_list);
2262 pvd->pv_page.pv_gen = 0;
2263 pvd->pv_page.pat_mode = 0;
2264 pvd->pv_invl_gen = 0;
2268 pmap_init_pv_table(void)
2274 * Initialize the pool of pv list locks.
2276 for (i = 0; i < NPV_LIST_LOCKS; i++)
2277 rw_init(&pv_list_locks[i], "pmap pv list");
2280 * Calculate the size of the pv head table for superpages.
2282 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2285 * Allocate memory for the pv head table for superpages.
2287 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2289 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2290 for (i = 0; i < pv_npg; i++)
2291 TAILQ_INIT(&pv_table[i].pv_list);
2292 TAILQ_INIT(&pv_dummy.pv_list);
2297 * Initialize the pmap module.
2298 * Called by vm_init, to initialize any structures that the pmap
2299 * system needs to map virtual memory.
2304 struct pmap_preinit_mapping *ppim;
2306 int error, i, ret, skz63;
2308 /* L1TF, reserve page @0 unconditionally */
2309 vm_page_blacklist_add(0, bootverbose);
2311 /* Detect bare-metal Skylake Server and Skylake-X. */
2312 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2313 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2315 * Skylake-X errata SKZ63. Processor May Hang When
2316 * Executing Code In an HLE Transaction Region between
2317 * 40000000H and 403FFFFFH.
2319 * Mark the pages in the range as preallocated. It
2320 * seems to be impossible to distinguish between
2321 * Skylake Server and Skylake X.
2324 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2327 printf("SKZ63: skipping 4M RAM starting "
2328 "at physical 1G\n");
2329 for (i = 0; i < atop(0x400000); i++) {
2330 ret = vm_page_blacklist_add(0x40000000 +
2332 if (!ret && bootverbose)
2333 printf("page at %#lx already used\n",
2334 0x40000000 + ptoa(i));
2340 pmap_allow_2m_x_ept_recalculate();
2343 * Initialize the vm page array entries for the kernel pmap's
2346 PMAP_LOCK(kernel_pmap);
2347 for (i = 0; i < nkpt; i++) {
2348 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2349 KASSERT(mpte >= vm_page_array &&
2350 mpte < &vm_page_array[vm_page_array_size],
2351 ("pmap_init: page table page is out of range"));
2352 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2353 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2354 mpte->ref_count = 1;
2357 * Collect the page table pages that were replaced by a 2MB
2358 * page in create_pagetables(). They are zero filled.
2360 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2361 pmap_insert_pt_page(kernel_pmap, mpte, false))
2362 panic("pmap_init: pmap_insert_pt_page failed");
2364 PMAP_UNLOCK(kernel_pmap);
2368 * If the kernel is running on a virtual machine, then it must assume
2369 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2370 * be prepared for the hypervisor changing the vendor and family that
2371 * are reported by CPUID. Consequently, the workaround for AMD Family
2372 * 10h Erratum 383 is enabled if the processor's feature set does not
2373 * include at least one feature that is only supported by older Intel
2374 * or newer AMD processors.
2376 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2377 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2378 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2380 workaround_erratum383 = 1;
2383 * Are large page mappings enabled?
2385 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2386 if (pg_ps_enabled) {
2387 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2388 ("pmap_init: can't assign to pagesizes[1]"));
2389 pagesizes[1] = NBPDR;
2390 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2391 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2392 ("pmap_init: can't assign to pagesizes[2]"));
2393 pagesizes[2] = NBPDP;
2398 * Initialize pv chunk lists.
2400 for (i = 0; i < PMAP_MEMDOM; i++) {
2401 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2402 TAILQ_INIT(&pv_chunks[i].pvc_list);
2404 pmap_init_pv_table();
2406 pmap_initialized = 1;
2407 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2408 ppim = pmap_preinit_mapping + i;
2411 /* Make the direct map consistent */
2412 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2413 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2414 ppim->sz, ppim->mode);
2418 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2419 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2422 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2423 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2424 (vmem_addr_t *)&qframe);
2426 panic("qframe allocation failed");
2429 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2430 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2431 lm_ents = LMEPML4I - LMSPML4I + 1;
2433 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2434 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2436 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2437 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2438 if (large_vmem == NULL) {
2439 printf("pmap: cannot create large map\n");
2442 for (i = 0; i < lm_ents; i++) {
2443 m = pmap_large_map_getptp_unlocked();
2445 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2446 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2452 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2453 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2454 "Maximum number of PML4 entries for use by large map (tunable). "
2455 "Each entry corresponds to 512GB of address space.");
2457 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2458 "2MB page mapping counters");
2460 static u_long pmap_pde_demotions;
2461 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2462 &pmap_pde_demotions, 0, "2MB page demotions");
2464 static u_long pmap_pde_mappings;
2465 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2466 &pmap_pde_mappings, 0, "2MB page mappings");
2468 static u_long pmap_pde_p_failures;
2469 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2470 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2472 static u_long pmap_pde_promotions;
2473 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2474 &pmap_pde_promotions, 0, "2MB page promotions");
2476 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2477 "1GB page mapping counters");
2479 static u_long pmap_pdpe_demotions;
2480 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2481 &pmap_pdpe_demotions, 0, "1GB page demotions");
2483 /***************************************************
2484 * Low level helper routines.....
2485 ***************************************************/
2488 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2490 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2492 switch (pmap->pm_type) {
2495 /* Verify that both PAT bits are not set at the same time */
2496 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2497 ("Invalid PAT bits in entry %#lx", entry));
2499 /* Swap the PAT bits if one of them is set */
2500 if ((entry & x86_pat_bits) != 0)
2501 entry ^= x86_pat_bits;
2505 * Nothing to do - the memory attributes are represented
2506 * the same way for regular pages and superpages.
2510 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2517 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2520 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2521 pat_index[(int)mode] >= 0);
2525 * Determine the appropriate bits to set in a PTE or PDE for a specified
2529 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2531 int cache_bits, pat_flag, pat_idx;
2533 if (!pmap_is_valid_memattr(pmap, mode))
2534 panic("Unknown caching mode %d\n", mode);
2536 switch (pmap->pm_type) {
2539 /* The PAT bit is different for PTE's and PDE's. */
2540 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2542 /* Map the caching mode to a PAT index. */
2543 pat_idx = pat_index[mode];
2545 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2548 cache_bits |= pat_flag;
2550 cache_bits |= PG_NC_PCD;
2552 cache_bits |= PG_NC_PWT;
2556 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2560 panic("unsupported pmap type %d", pmap->pm_type);
2563 return (cache_bits);
2567 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2571 switch (pmap->pm_type) {
2574 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2577 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2580 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2587 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2589 int pat_flag, pat_idx;
2592 switch (pmap->pm_type) {
2595 /* The PAT bit is different for PTE's and PDE's. */
2596 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2598 if ((pte & pat_flag) != 0)
2600 if ((pte & PG_NC_PCD) != 0)
2602 if ((pte & PG_NC_PWT) != 0)
2606 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2607 panic("EPT PTE %#lx has no PAT memory type", pte);
2608 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2612 /* See pmap_init_pat(). */
2622 pmap_ps_enabled(pmap_t pmap)
2625 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2629 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2632 switch (pmap->pm_type) {
2639 * This is a little bogus since the generation number is
2640 * supposed to be bumped up when a region of the address
2641 * space is invalidated in the page tables.
2643 * In this case the old PDE entry is valid but yet we want
2644 * to make sure that any mappings using the old entry are
2645 * invalidated in the TLB.
2647 * The reason this works as expected is because we rendezvous
2648 * "all" host cpus and force any vcpu context to exit as a
2651 atomic_add_long(&pmap->pm_eptgen, 1);
2654 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2656 pde_store(pde, newpde);
2660 * After changing the page size for the specified virtual address in the page
2661 * table, flush the corresponding entries from the processor's TLB. Only the
2662 * calling processor's TLB is affected.
2664 * The calling thread must be pinned to a processor.
2667 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2671 if (pmap_type_guest(pmap))
2674 KASSERT(pmap->pm_type == PT_X86,
2675 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2677 PG_G = pmap_global_bit(pmap);
2679 if ((newpde & PG_PS) == 0)
2680 /* Demotion: flush a specific 2MB page mapping. */
2682 else if ((newpde & PG_G) == 0)
2684 * Promotion: flush every 4KB page mapping from the TLB
2685 * because there are too many to flush individually.
2690 * Promotion: flush every 4KB page mapping from the TLB,
2691 * including any global (PG_G) mappings.
2699 * For SMP, these functions have to use the IPI mechanism for coherence.
2701 * N.B.: Before calling any of the following TLB invalidation functions,
2702 * the calling processor must ensure that all stores updating a non-
2703 * kernel page table are globally performed. Otherwise, another
2704 * processor could cache an old, pre-update entry without being
2705 * invalidated. This can happen one of two ways: (1) The pmap becomes
2706 * active on another processor after its pm_active field is checked by
2707 * one of the following functions but before a store updating the page
2708 * table is globally performed. (2) The pmap becomes active on another
2709 * processor before its pm_active field is checked but due to
2710 * speculative loads one of the following functions stills reads the
2711 * pmap as inactive on the other processor.
2713 * The kernel page table is exempt because its pm_active field is
2714 * immutable. The kernel page table is always active on every
2719 * Interrupt the cpus that are executing in the guest context.
2720 * This will force the vcpu to exit and the cached EPT mappings
2721 * will be invalidated by the host before the next vmresume.
2723 static __inline void
2724 pmap_invalidate_ept(pmap_t pmap)
2730 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2731 ("pmap_invalidate_ept: absurd pm_active"));
2734 * The TLB mappings associated with a vcpu context are not
2735 * flushed each time a different vcpu is chosen to execute.
2737 * This is in contrast with a process's vtop mappings that
2738 * are flushed from the TLB on each context switch.
2740 * Therefore we need to do more than just a TLB shootdown on
2741 * the active cpus in 'pmap->pm_active'. To do this we keep
2742 * track of the number of invalidations performed on this pmap.
2744 * Each vcpu keeps a cache of this counter and compares it
2745 * just before a vmresume. If the counter is out-of-date an
2746 * invept will be done to flush stale mappings from the TLB.
2748 * To ensure that all vCPU threads have observed the new counter
2749 * value before returning, we use SMR. Ordering is important here:
2750 * the VMM enters an SMR read section before loading the counter
2751 * and after updating the pm_active bit set. Thus, pm_active is
2752 * a superset of active readers, and any reader that has observed
2753 * the goal has observed the new counter value.
2755 atomic_add_long(&pmap->pm_eptgen, 1);
2757 goal = smr_advance(pmap->pm_eptsmr);
2760 * Force the vcpu to exit and trap back into the hypervisor.
2762 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2763 ipi_selected(pmap->pm_active, ipinum);
2767 * Ensure that all active vCPUs will observe the new generation counter
2768 * value before executing any more guest instructions.
2770 smr_wait(pmap->pm_eptsmr, goal);
2774 pmap_invalidate_cpu_mask(pmap_t pmap)
2776 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2780 pmap_invalidate_preipi_pcid(pmap_t pmap)
2786 cpuid = PCPU_GET(cpuid);
2787 if (pmap != PCPU_GET(curpmap))
2788 cpuid = 0xffffffff; /* An impossible value */
2792 pmap->pm_pcids[i].pm_gen = 0;
2796 * The fence is between stores to pm_gen and the read of the
2797 * pm_active mask. We need to ensure that it is impossible
2798 * for us to miss the bit update in pm_active and
2799 * simultaneously observe a non-zero pm_gen in
2800 * pmap_activate_sw(), otherwise TLB update is missed.
2801 * Without the fence, IA32 allows such an outcome. Note that
2802 * pm_active is updated by a locked operation, which provides
2803 * the reciprocal fence.
2805 atomic_thread_fence_seq_cst();
2809 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused)
2814 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t))
2816 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid :
2817 pmap_invalidate_preipi_nopcid);
2821 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va,
2822 const bool invpcid_works1)
2824 struct invpcid_descr d;
2825 uint64_t kcr3, ucr3;
2830 * Because pm_pcid is recalculated on a context switch, we
2831 * must ensure there is no preemption, not just pinning.
2832 * Otherwise, we might use a stale value below.
2834 CRITICAL_ASSERT(curthread);
2837 * No need to do anything with user page tables invalidation
2838 * if there is no user page table, or invalidation is deferred
2839 * until the return to userspace. ucr3_load_mask is stable
2840 * because we have preemption disabled.
2842 if (pmap->pm_ucr3 == PMAP_NO_CR3 ||
2843 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
2846 cpuid = PCPU_GET(cpuid);
2848 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2849 if (invpcid_works1) {
2850 d.pcid = pcid | PMAP_PCID_USER_PT;
2853 invpcid(&d, INVPCID_ADDR);
2855 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2856 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2857 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2862 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va)
2864 pmap_invalidate_page_pcid_cb(pmap, va, true);
2868 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va)
2870 pmap_invalidate_page_pcid_cb(pmap, va, false);
2874 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused)
2878 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t))
2880 if (pmap_pcid_enabled)
2881 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb :
2882 pmap_invalidate_page_pcid_noinvpcid_cb);
2883 return (pmap_invalidate_page_nopcid_cb);
2887 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2888 vm_offset_t addr2 __unused)
2890 if (pmap == kernel_pmap) {
2892 } else if (pmap == PCPU_GET(curpmap)) {
2894 pmap_invalidate_page_cb(pmap, va);
2899 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2901 if (pmap_type_guest(pmap)) {
2902 pmap_invalidate_ept(pmap);
2906 KASSERT(pmap->pm_type == PT_X86,
2907 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2909 pmap_invalidate_preipi(pmap);
2910 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2911 pmap_invalidate_page_curcpu_cb);
2914 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2915 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2918 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2919 const bool invpcid_works1)
2921 struct invpcid_descr d;
2922 uint64_t kcr3, ucr3;
2926 CRITICAL_ASSERT(curthread);
2928 if (pmap != PCPU_GET(curpmap) ||
2929 pmap->pm_ucr3 == PMAP_NO_CR3 ||
2930 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
2933 cpuid = PCPU_GET(cpuid);
2935 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2936 if (invpcid_works1) {
2937 d.pcid = pcid | PMAP_PCID_USER_PT;
2939 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE)
2940 invpcid(&d, INVPCID_ADDR);
2942 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2943 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2944 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2949 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva,
2952 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true);
2956 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva,
2959 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false);
2963 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused,
2964 vm_offset_t eva __unused)
2968 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t,
2971 if (pmap_pcid_enabled)
2972 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb :
2973 pmap_invalidate_range_pcid_noinvpcid_cb);
2974 return (pmap_invalidate_range_nopcid_cb);
2978 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2982 if (pmap == kernel_pmap) {
2983 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2985 } else if (pmap == PCPU_GET(curpmap)) {
2986 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2988 pmap_invalidate_range_cb(pmap, sva, eva);
2993 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2995 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2996 pmap_invalidate_all(pmap);
3000 if (pmap_type_guest(pmap)) {
3001 pmap_invalidate_ept(pmap);
3005 KASSERT(pmap->pm_type == PT_X86,
3006 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
3008 pmap_invalidate_preipi(pmap);
3009 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
3010 pmap_invalidate_range_curcpu_cb);
3014 pmap_invalidate_all_pcid_cb(pmap_t pmap, bool invpcid_works1)
3016 struct invpcid_descr d;
3021 if (pmap == kernel_pmap) {
3022 if (invpcid_works1) {
3023 bzero(&d, sizeof(d));
3024 invpcid(&d, INVPCID_CTXGLOB);
3028 } else if (pmap == PCPU_GET(curpmap)) {
3029 CRITICAL_ASSERT(curthread);
3030 cpuid = PCPU_GET(cpuid);
3032 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3033 if (invpcid_works1) {
3037 invpcid(&d, INVPCID_CTX);
3039 kcr3 = pmap->pm_cr3 | pcid;
3042 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3043 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3048 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap)
3050 pmap_invalidate_all_pcid_cb(pmap, true);
3054 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap)
3056 pmap_invalidate_all_pcid_cb(pmap, false);
3060 pmap_invalidate_all_nopcid_cb(pmap_t pmap)
3062 if (pmap == kernel_pmap)
3064 else if (pmap == PCPU_GET(curpmap))
3068 DEFINE_IFUNC(static, void, pmap_invalidate_all_cb, (pmap_t))
3070 if (pmap_pcid_enabled)
3071 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb :
3072 pmap_invalidate_all_pcid_noinvpcid_cb);
3073 return (pmap_invalidate_all_nopcid_cb);
3077 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3078 vm_offset_t addr2 __unused)
3080 pmap_invalidate_all_cb(pmap);
3084 pmap_invalidate_all(pmap_t pmap)
3086 if (pmap_type_guest(pmap)) {
3087 pmap_invalidate_ept(pmap);
3091 KASSERT(pmap->pm_type == PT_X86,
3092 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3094 pmap_invalidate_preipi(pmap);
3095 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3096 pmap_invalidate_all_curcpu_cb);
3100 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3101 vm_offset_t addr2 __unused)
3107 pmap_invalidate_cache(void)
3110 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3114 cpuset_t invalidate; /* processors that invalidate their TLB */
3119 u_int store; /* processor that updates the PDE */
3123 pmap_update_pde_action(void *arg)
3125 struct pde_action *act = arg;
3127 if (act->store == PCPU_GET(cpuid))
3128 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3132 pmap_update_pde_teardown(void *arg)
3134 struct pde_action *act = arg;
3136 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3137 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3141 * Change the page size for the specified virtual address in a way that
3142 * prevents any possibility of the TLB ever having two entries that map the
3143 * same virtual address using different page sizes. This is the recommended
3144 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3145 * machine check exception for a TLB state that is improperly diagnosed as a
3149 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3151 struct pde_action act;
3152 cpuset_t active, other_cpus;
3156 cpuid = PCPU_GET(cpuid);
3157 other_cpus = all_cpus;
3158 CPU_CLR(cpuid, &other_cpus);
3159 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3162 active = pmap->pm_active;
3164 if (CPU_OVERLAP(&active, &other_cpus)) {
3166 act.invalidate = active;
3170 act.newpde = newpde;
3171 CPU_SET(cpuid, &active);
3172 smp_rendezvous_cpus(active,
3173 smp_no_rendezvous_barrier, pmap_update_pde_action,
3174 pmap_update_pde_teardown, &act);
3176 pmap_update_pde_store(pmap, pde, newpde);
3177 if (CPU_ISSET(cpuid, &active))
3178 pmap_update_pde_invalidate(pmap, va, newpde);
3184 * Normal, non-SMP, invalidation functions.
3187 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3189 struct invpcid_descr d;
3190 uint64_t kcr3, ucr3;
3193 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3197 KASSERT(pmap->pm_type == PT_X86,
3198 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3200 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3202 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3203 pmap->pm_ucr3 != PMAP_NO_CR3) {
3205 pcid = pmap->pm_pcids[0].pm_pcid;
3206 if (invpcid_works) {
3207 d.pcid = pcid | PMAP_PCID_USER_PT;
3210 invpcid(&d, INVPCID_ADDR);
3212 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3213 ucr3 = pmap->pm_ucr3 | pcid |
3214 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3215 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3219 } else if (pmap_pcid_enabled)
3220 pmap->pm_pcids[0].pm_gen = 0;
3224 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3226 struct invpcid_descr d;
3228 uint64_t kcr3, ucr3;
3230 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3234 KASSERT(pmap->pm_type == PT_X86,
3235 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3237 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3238 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3240 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3241 pmap->pm_ucr3 != PMAP_NO_CR3) {
3243 if (invpcid_works) {
3244 d.pcid = pmap->pm_pcids[0].pm_pcid |
3248 for (; d.addr < eva; d.addr += PAGE_SIZE)
3249 invpcid(&d, INVPCID_ADDR);
3251 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3252 pm_pcid | CR3_PCID_SAVE;
3253 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3254 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3255 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3259 } else if (pmap_pcid_enabled) {
3260 pmap->pm_pcids[0].pm_gen = 0;
3265 pmap_invalidate_all(pmap_t pmap)
3267 struct invpcid_descr d;
3268 uint64_t kcr3, ucr3;
3270 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3274 KASSERT(pmap->pm_type == PT_X86,
3275 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3277 if (pmap == kernel_pmap) {
3278 if (pmap_pcid_enabled && invpcid_works) {
3279 bzero(&d, sizeof(d));
3280 invpcid(&d, INVPCID_CTXGLOB);
3284 } else if (pmap == PCPU_GET(curpmap)) {
3285 if (pmap_pcid_enabled) {
3287 if (invpcid_works) {
3288 d.pcid = pmap->pm_pcids[0].pm_pcid;
3291 invpcid(&d, INVPCID_CTX);
3292 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3293 d.pcid |= PMAP_PCID_USER_PT;
3294 invpcid(&d, INVPCID_CTX);
3297 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3298 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3299 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3300 0].pm_pcid | PMAP_PCID_USER_PT;
3301 pmap_pti_pcid_invalidate(ucr3, kcr3);
3309 } else if (pmap_pcid_enabled) {
3310 pmap->pm_pcids[0].pm_gen = 0;
3315 pmap_invalidate_cache(void)
3322 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3325 pmap_update_pde_store(pmap, pde, newpde);
3326 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3327 pmap_update_pde_invalidate(pmap, va, newpde);
3329 pmap->pm_pcids[0].pm_gen = 0;
3334 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3338 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3339 * by a promotion that did not invalidate the 512 4KB page mappings
3340 * that might exist in the TLB. Consequently, at this point, the TLB
3341 * may hold both 4KB and 2MB page mappings for the address range [va,
3342 * va + NBPDR). Therefore, the entire range must be invalidated here.
3343 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3344 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3345 * single INVLPG suffices to invalidate the 2MB page mapping from the
3348 if ((pde & PG_PROMOTED) != 0)
3349 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3351 pmap_invalidate_page(pmap, va);
3354 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3355 (vm_offset_t sva, vm_offset_t eva))
3358 if ((cpu_feature & CPUID_SS) != 0)
3359 return (pmap_invalidate_cache_range_selfsnoop);
3360 if ((cpu_feature & CPUID_CLFSH) != 0)
3361 return (pmap_force_invalidate_cache_range);
3362 return (pmap_invalidate_cache_range_all);
3365 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3368 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3371 KASSERT((sva & PAGE_MASK) == 0,
3372 ("pmap_invalidate_cache_range: sva not page-aligned"));
3373 KASSERT((eva & PAGE_MASK) == 0,
3374 ("pmap_invalidate_cache_range: eva not page-aligned"));
3378 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3381 pmap_invalidate_cache_range_check_align(sva, eva);
3385 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3388 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3391 * XXX: Some CPUs fault, hang, or trash the local APIC
3392 * registers if we use CLFLUSH on the local APIC range. The
3393 * local APIC is always uncached, so we don't need to flush
3394 * for that range anyway.
3396 if (pmap_kextract(sva) == lapic_paddr)
3399 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3401 * Do per-cache line flush. Use a locked
3402 * instruction to insure that previous stores are
3403 * included in the write-back. The processor
3404 * propagates flush to other processors in the cache
3407 atomic_thread_fence_seq_cst();
3408 for (; sva < eva; sva += cpu_clflush_line_size)
3410 atomic_thread_fence_seq_cst();
3413 * Writes are ordered by CLFLUSH on Intel CPUs.
3415 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3417 for (; sva < eva; sva += cpu_clflush_line_size)
3419 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3425 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3428 pmap_invalidate_cache_range_check_align(sva, eva);
3429 pmap_invalidate_cache();
3433 * Remove the specified set of pages from the data and instruction caches.
3435 * In contrast to pmap_invalidate_cache_range(), this function does not
3436 * rely on the CPU's self-snoop feature, because it is intended for use
3437 * when moving pages into a different cache domain.
3440 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3442 vm_offset_t daddr, eva;
3446 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3447 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3448 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3449 pmap_invalidate_cache();
3452 atomic_thread_fence_seq_cst();
3453 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3455 for (i = 0; i < count; i++) {
3456 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3457 eva = daddr + PAGE_SIZE;
3458 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3466 atomic_thread_fence_seq_cst();
3467 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3473 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3476 pmap_invalidate_cache_range_check_align(sva, eva);
3478 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3479 pmap_force_invalidate_cache_range(sva, eva);
3483 /* See comment in pmap_force_invalidate_cache_range(). */
3484 if (pmap_kextract(sva) == lapic_paddr)
3487 atomic_thread_fence_seq_cst();
3488 for (; sva < eva; sva += cpu_clflush_line_size)
3490 atomic_thread_fence_seq_cst();
3494 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3498 int error, pte_bits;
3500 KASSERT((spa & PAGE_MASK) == 0,
3501 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3502 KASSERT((epa & PAGE_MASK) == 0,
3503 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3505 if (spa < dmaplimit) {
3506 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3508 if (dmaplimit >= epa)
3513 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3515 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3517 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3518 pte = vtopte(vaddr);
3519 for (; spa < epa; spa += PAGE_SIZE) {
3521 pte_store(pte, spa | pte_bits);
3523 /* XXXKIB atomic inside flush_cache_range are excessive */
3524 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3527 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3531 * Routine: pmap_extract
3533 * Extract the physical page address associated
3534 * with the given map/virtual_address pair.
3537 pmap_extract(pmap_t pmap, vm_offset_t va)
3541 pt_entry_t *pte, PG_V;
3545 PG_V = pmap_valid_bit(pmap);
3547 pdpe = pmap_pdpe(pmap, va);
3548 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3549 if ((*pdpe & PG_PS) != 0)
3550 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3552 pde = pmap_pdpe_to_pde(pdpe, va);
3553 if ((*pde & PG_V) != 0) {
3554 if ((*pde & PG_PS) != 0) {
3555 pa = (*pde & PG_PS_FRAME) |
3558 pte = pmap_pde_to_pte(pde, va);
3559 pa = (*pte & PG_FRAME) |
3570 * Routine: pmap_extract_and_hold
3572 * Atomically extract and hold the physical page
3573 * with the given pmap and virtual address pair
3574 * if that mapping permits the given protection.
3577 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3579 pdp_entry_t pdpe, *pdpep;
3580 pd_entry_t pde, *pdep;
3581 pt_entry_t pte, PG_RW, PG_V;
3585 PG_RW = pmap_rw_bit(pmap);
3586 PG_V = pmap_valid_bit(pmap);
3589 pdpep = pmap_pdpe(pmap, va);
3590 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3592 if ((pdpe & PG_PS) != 0) {
3593 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3595 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3599 pdep = pmap_pdpe_to_pde(pdpep, va);
3600 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3602 if ((pde & PG_PS) != 0) {
3603 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3605 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3609 pte = *pmap_pde_to_pte(pdep, va);
3610 if ((pte & PG_V) == 0 ||
3611 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3613 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3616 if (m != NULL && !vm_page_wire_mapped(m))
3624 pmap_kextract(vm_offset_t va)
3629 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3630 pa = DMAP_TO_PHYS(va);
3631 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3632 pa = pmap_large_map_kextract(va);
3636 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3639 * Beware of a concurrent promotion that changes the
3640 * PDE at this point! For example, vtopte() must not
3641 * be used to access the PTE because it would use the
3642 * new PDE. It is, however, safe to use the old PDE
3643 * because the page table page is preserved by the
3646 pa = *pmap_pde_to_pte(&pde, va);
3647 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3653 /***************************************************
3654 * Low level mapping routines.....
3655 ***************************************************/
3658 * Add a wired page to the kva.
3659 * Note: not SMP coherent.
3662 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3667 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3670 static __inline void
3671 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3677 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3678 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3682 * Remove a page from the kernel pagetables.
3683 * Note: not SMP coherent.
3686 pmap_kremove(vm_offset_t va)
3695 * Used to map a range of physical addresses into kernel
3696 * virtual address space.
3698 * The value passed in '*virt' is a suggested virtual address for
3699 * the mapping. Architectures which can support a direct-mapped
3700 * physical to virtual region can return the appropriate address
3701 * within that region, leaving '*virt' unchanged. Other
3702 * architectures should map the pages starting at '*virt' and
3703 * update '*virt' with the first usable address after the mapped
3707 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3709 return PHYS_TO_DMAP(start);
3713 * Add a list of wired pages to the kva
3714 * this routine is only used for temporary
3715 * kernel mappings that do not need to have
3716 * page modification or references recorded.
3717 * Note that old mappings are simply written
3718 * over. The page *must* be wired.
3719 * Note: SMP coherent. Uses a ranged shootdown IPI.
3722 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3724 pt_entry_t *endpte, oldpte, pa, *pte;
3730 endpte = pte + count;
3731 while (pte < endpte) {
3733 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3734 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3735 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3737 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3741 if (__predict_false((oldpte & X86_PG_V) != 0))
3742 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3747 * This routine tears out page mappings from the
3748 * kernel -- it is meant only for temporary mappings.
3749 * Note: SMP coherent. Uses a ranged shootdown IPI.
3752 pmap_qremove(vm_offset_t sva, int count)
3757 while (count-- > 0) {
3758 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3762 pmap_invalidate_range(kernel_pmap, sva, va);
3765 /***************************************************
3766 * Page table page management routines.....
3767 ***************************************************/
3769 * Schedule the specified unused page table page to be freed. Specifically,
3770 * add the page to the specified list of pages that will be released to the
3771 * physical memory manager after the TLB has been updated.
3773 static __inline void
3774 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3775 boolean_t set_PG_ZERO)
3779 m->flags |= PG_ZERO;
3781 m->flags &= ~PG_ZERO;
3782 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3786 * Inserts the specified page table page into the specified pmap's collection
3787 * of idle page table pages. Each of a pmap's page table pages is responsible
3788 * for mapping a distinct range of virtual addresses. The pmap's collection is
3789 * ordered by this virtual address range.
3791 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3794 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3798 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3799 return (vm_radix_insert(&pmap->pm_root, mpte));
3803 * Removes the page table page mapping the specified virtual address from the
3804 * specified pmap's collection of idle page table pages, and returns it.
3805 * Otherwise, returns NULL if there is no page table page corresponding to the
3806 * specified virtual address.
3808 static __inline vm_page_t
3809 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3813 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3817 * Decrements a page table page's reference count, which is used to record the
3818 * number of valid page table entries within the page. If the reference count
3819 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3820 * page table page was unmapped and FALSE otherwise.
3822 static inline boolean_t
3823 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3827 if (m->ref_count == 0) {
3828 _pmap_unwire_ptp(pmap, va, m, free);
3835 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3841 vm_page_t pdpg, pdppg, pml4pg;
3843 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3846 * unmap the page table page
3848 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3850 MPASS(pmap_is_la57(pmap));
3851 pml5 = pmap_pml5e(pmap, va);
3853 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3854 pml5 = pmap_pml5e_u(pmap, va);
3857 } else if (m->pindex >= NUPDE + NUPDPE) {
3859 pml4 = pmap_pml4e(pmap, va);
3861 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3862 va <= VM_MAXUSER_ADDRESS) {
3863 pml4 = pmap_pml4e_u(pmap, va);
3866 } else if (m->pindex >= NUPDE) {
3868 pdp = pmap_pdpe(pmap, va);
3872 pd = pmap_pde(pmap, va);
3875 pmap_resident_count_dec(pmap, 1);
3876 if (m->pindex < NUPDE) {
3877 /* We just released a PT, unhold the matching PD */
3878 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3879 pmap_unwire_ptp(pmap, va, pdpg, free);
3880 } else if (m->pindex < NUPDE + NUPDPE) {
3881 /* We just released a PD, unhold the matching PDP */
3882 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3883 pmap_unwire_ptp(pmap, va, pdppg, free);
3884 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
3885 /* We just released a PDP, unhold the matching PML4 */
3886 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
3887 pmap_unwire_ptp(pmap, va, pml4pg, free);
3891 * Put page on a list so that it is released after
3892 * *ALL* TLB shootdown is done
3894 pmap_add_delayed_free_list(m, free, TRUE);
3898 * After removing a page table entry, this routine is used to
3899 * conditionally free the page, and manage the reference count.
3902 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3903 struct spglist *free)
3907 if (va >= VM_MAXUSER_ADDRESS)
3909 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3910 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3911 return (pmap_unwire_ptp(pmap, va, mpte, free));
3915 * Release a page table page reference after a failed attempt to create a
3919 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3921 struct spglist free;
3924 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3926 * Although "va" was never mapped, paging-structure caches
3927 * could nonetheless have entries that refer to the freed
3928 * page table pages. Invalidate those entries.
3930 pmap_invalidate_page(pmap, va);
3931 vm_page_free_pages_toq(&free, true);
3936 pmap_pinit0(pmap_t pmap)
3942 PMAP_LOCK_INIT(pmap);
3943 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
3944 pmap->pm_pmltopu = NULL;
3945 pmap->pm_cr3 = kernel_pmap->pm_cr3;
3946 /* hack to keep pmap_pti_pcid_invalidate() alive */
3947 pmap->pm_ucr3 = PMAP_NO_CR3;
3948 pmap->pm_root.rt_root = 0;
3949 CPU_ZERO(&pmap->pm_active);
3950 TAILQ_INIT(&pmap->pm_pvchunk);
3951 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3952 pmap->pm_flags = pmap_flags;
3954 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3955 pmap->pm_pcids[i].pm_gen = 1;
3957 pmap_activate_boot(pmap);
3962 p->p_md.md_flags |= P_MD_KPTI;
3965 pmap_thread_init_invl_gen(td);
3967 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3968 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3969 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3975 pmap_pinit_pml4(vm_page_t pml4pg)
3977 pml4_entry_t *pm_pml4;
3980 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3982 /* Wire in kernel global address entries. */
3983 for (i = 0; i < NKPML4E; i++) {
3984 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3987 for (i = 0; i < ndmpdpphys; i++) {
3988 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3992 /* install self-referential address mapping entry(s) */
3993 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3994 X86_PG_A | X86_PG_M;
3996 /* install large map entries if configured */
3997 for (i = 0; i < lm_ents; i++)
3998 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4002 pmap_pinit_pml5(vm_page_t pml5pg)
4004 pml5_entry_t *pm_pml5;
4006 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4009 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4010 * entering all existing kernel mappings into level 5 table.
4012 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4013 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4014 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4017 * Install self-referential address mapping entry.
4019 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4020 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4021 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4025 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4027 pml4_entry_t *pm_pml4u;
4030 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4031 for (i = 0; i < NPML4EPG; i++)
4032 pm_pml4u[i] = pti_pml4[i];
4036 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4038 pml5_entry_t *pm_pml5u;
4040 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4043 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4044 * table, entering all kernel mappings needed for usermode
4045 * into level 5 table.
4047 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4048 pmap_kextract((vm_offset_t)pti_pml4) |
4049 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4050 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4054 * Initialize a preallocated and zeroed pmap structure,
4055 * such as one in a vmspace structure.
4058 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4060 vm_page_t pmltop_pg, pmltop_pgu;
4061 vm_paddr_t pmltop_phys;
4065 * allocate the page directory page
4067 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4068 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4070 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4071 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4074 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4075 pmap->pm_pcids[i].pm_gen = 0;
4077 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4078 pmap->pm_ucr3 = PMAP_NO_CR3;
4079 pmap->pm_pmltopu = NULL;
4081 pmap->pm_type = pm_type;
4082 if ((pmltop_pg->flags & PG_ZERO) == 0)
4083 pagezero(pmap->pm_pmltop);
4086 * Do not install the host kernel mappings in the nested page
4087 * tables. These mappings are meaningless in the guest physical
4089 * Install minimal kernel mappings in PTI case.
4093 pmap->pm_cr3 = pmltop_phys;
4094 if (pmap_is_la57(pmap))
4095 pmap_pinit_pml5(pmltop_pg);
4097 pmap_pinit_pml4(pmltop_pg);
4098 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4099 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4100 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4101 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4102 VM_PAGE_TO_PHYS(pmltop_pgu));
4103 if (pmap_is_la57(pmap))
4104 pmap_pinit_pml5_pti(pmltop_pgu);
4106 pmap_pinit_pml4_pti(pmltop_pgu);
4107 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4109 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4110 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4111 pkru_free_range, pmap, M_NOWAIT);
4116 pmap->pm_eptsmr = smr_create("pmap", 0, 0);
4120 pmap->pm_root.rt_root = 0;
4121 CPU_ZERO(&pmap->pm_active);
4122 TAILQ_INIT(&pmap->pm_pvchunk);
4123 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4124 pmap->pm_flags = flags;
4125 pmap->pm_eptgen = 0;
4131 pmap_pinit(pmap_t pmap)
4134 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4138 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4141 struct spglist free;
4143 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4144 if (mpg->ref_count != 0)
4147 _pmap_unwire_ptp(pmap, va, mpg, &free);
4148 pmap_invalidate_page(pmap, va);
4149 vm_page_free_pages_toq(&free, true);
4152 static pml4_entry_t *
4153 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4156 vm_pindex_t pml5index;
4163 if (!pmap_is_la57(pmap))
4164 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4166 PG_V = pmap_valid_bit(pmap);
4167 pml5index = pmap_pml5e_index(va);
4168 pml5 = &pmap->pm_pmltop[pml5index];
4169 if ((*pml5 & PG_V) == 0) {
4170 if (_pmap_allocpte(pmap, pmap_pml5e_pindex(va), lockp, va) ==
4177 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4178 pml4 = &pml4[pmap_pml4e_index(va)];
4179 if ((*pml4 & PG_V) == 0) {
4180 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4181 if (allocated && !addref)
4182 pml4pg->ref_count--;
4183 else if (!allocated && addref)
4184 pml4pg->ref_count++;
4189 static pdp_entry_t *
4190 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4199 PG_V = pmap_valid_bit(pmap);
4201 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4205 if ((*pml4 & PG_V) == 0) {
4206 /* Have to allocate a new pdp, recurse */
4207 if (_pmap_allocpte(pmap, pmap_pml4e_pindex(va), lockp, va) ==
4209 if (pmap_is_la57(pmap))
4210 pmap_allocpte_free_unref(pmap, va,
4211 pmap_pml5e(pmap, va));
4218 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4219 pdp = &pdp[pmap_pdpe_index(va)];
4220 if ((*pdp & PG_V) == 0) {
4221 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4222 if (allocated && !addref)
4224 else if (!allocated && addref)
4231 * This routine is called if the desired page table page does not exist.
4233 * If page table page allocation fails, this routine may sleep before
4234 * returning NULL. It sleeps only if a lock pointer was given.
4236 * Note: If a page allocation fails at page table level two, three, or four,
4237 * up to three pages may be held during the wait, only to be released
4238 * afterwards. This conservative approach is easily argued to avoid
4241 * The ptepindexes, i.e. page indices, of the page table pages encountered
4242 * while translating virtual address va are defined as follows:
4243 * - for the page table page (last level),
4244 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4245 * in other words, it is just the index of the PDE that maps the page
4247 * - for the page directory page,
4248 * ptepindex = NUPDE (number of userland PD entries) +
4249 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4250 * i.e. index of PDPE is put after the last index of PDE,
4251 * - for the page directory pointer page,
4252 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4254 * i.e. index of pml4e is put after the last index of PDPE,
4255 * - for the PML4 page (if LA57 mode is enabled),
4256 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4257 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4258 * i.e. index of pml5e is put after the last index of PML4E.
4260 * Define an order on the paging entries, where all entries of the
4261 * same height are put together, then heights are put from deepest to
4262 * root. Then ptexpindex is the sequential number of the
4263 * corresponding paging entry in this order.
4265 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4266 * LA57 paging structures even in LA48 paging mode. Moreover, the
4267 * ptepindexes are calculated as if the paging structures were 5-level
4268 * regardless of the actual mode of operation.
4270 * The root page at PML4/PML5 does not participate in this indexing scheme,
4271 * since it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
4274 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4275 vm_offset_t va __unused)
4277 vm_pindex_t pml5index, pml4index;
4278 pml5_entry_t *pml5, *pml5u;
4279 pml4_entry_t *pml4, *pml4u;
4283 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4285 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4287 PG_A = pmap_accessed_bit(pmap);
4288 PG_M = pmap_modified_bit(pmap);
4289 PG_V = pmap_valid_bit(pmap);
4290 PG_RW = pmap_rw_bit(pmap);
4293 * Allocate a page table page.
4295 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4296 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
4297 if (lockp != NULL) {
4298 RELEASE_PV_LIST_LOCK(lockp);
4300 PMAP_ASSERT_NOT_IN_DI();
4306 * Indicate the need to retry. While waiting, the page table
4307 * page may have been allocated.
4311 if ((m->flags & PG_ZERO) == 0)
4315 * Map the pagetable page into the process address space, if
4316 * it isn't already there.
4318 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4319 MPASS(pmap_is_la57(pmap));
4321 pml5index = pmap_pml5e_index(va);
4322 pml5 = &pmap->pm_pmltop[pml5index];
4323 KASSERT((*pml5 & PG_V) == 0,
4324 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4325 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4327 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4328 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4331 pml5u = &pmap->pm_pmltopu[pml5index];
4332 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4335 } else if (ptepindex >= NUPDE + NUPDPE) {
4336 pml4index = pmap_pml4e_index(va);
4337 /* Wire up a new PDPE page */
4338 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4340 vm_page_unwire_noq(m);
4341 vm_page_free_zero(m);
4344 KASSERT((*pml4 & PG_V) == 0,
4345 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4346 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4348 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4349 pml4index < NUPML4E) {
4351 * PTI: Make all user-space mappings in the
4352 * kernel-mode page table no-execute so that
4353 * we detect any programming errors that leave
4354 * the kernel-mode page table active on return
4357 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4360 pml4u = &pmap->pm_pmltopu[pml4index];
4361 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4364 } else if (ptepindex >= NUPDE) {
4365 /* Wire up a new PDE page */
4366 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4368 vm_page_unwire_noq(m);
4369 vm_page_free_zero(m);
4372 KASSERT((*pdp & PG_V) == 0,
4373 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4374 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4376 /* Wire up a new PTE page */
4377 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4379 vm_page_unwire_noq(m);
4380 vm_page_free_zero(m);
4383 if ((*pdp & PG_V) == 0) {
4384 /* Have to allocate a new pd, recurse */
4385 if (_pmap_allocpte(pmap, pmap_pdpe_pindex(va),
4386 lockp, va) == NULL) {
4387 pmap_allocpte_free_unref(pmap, va,
4388 pmap_pml4e(pmap, va));
4389 vm_page_unwire_noq(m);
4390 vm_page_free_zero(m);
4394 /* Add reference to the pd page */
4395 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4398 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4400 /* Now we know where the page directory page is */
4401 pd = &pd[pmap_pde_index(va)];
4402 KASSERT((*pd & PG_V) == 0,
4403 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4404 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4407 pmap_resident_count_inc(pmap, 1);
4413 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4414 struct rwlock **lockp)
4416 pdp_entry_t *pdpe, PG_V;
4419 vm_pindex_t pdpindex;
4421 PG_V = pmap_valid_bit(pmap);
4424 pdpe = pmap_pdpe(pmap, va);
4425 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4426 pde = pmap_pdpe_to_pde(pdpe, va);
4427 if (va < VM_MAXUSER_ADDRESS) {
4428 /* Add a reference to the pd page. */
4429 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4433 } else if (va < VM_MAXUSER_ADDRESS) {
4434 /* Allocate a pd page. */
4435 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4436 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp, va);
4443 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4444 pde = &pde[pmap_pde_index(va)];
4446 panic("pmap_alloc_pde: missing page table page for va %#lx",
4453 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4455 vm_pindex_t ptepindex;
4456 pd_entry_t *pd, PG_V;
4459 PG_V = pmap_valid_bit(pmap);
4462 * Calculate pagetable page index
4464 ptepindex = pmap_pde_pindex(va);
4467 * Get the page directory entry
4469 pd = pmap_pde(pmap, va);
4472 * This supports switching from a 2MB page to a
4475 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4476 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4478 * Invalidation of the 2MB page mapping may have caused
4479 * the deallocation of the underlying PD page.
4486 * If the page table page is mapped, we just increment the
4487 * hold count, and activate it.
4489 if (pd != NULL && (*pd & PG_V) != 0) {
4490 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4494 * Here if the pte page isn't mapped, or if it has been
4497 m = _pmap_allocpte(pmap, ptepindex, lockp, va);
4498 if (m == NULL && lockp != NULL)
4504 /***************************************************
4505 * Pmap allocation/deallocation routines.
4506 ***************************************************/
4509 * Release any resources held by the given physical map.
4510 * Called when a pmap initialized by pmap_pinit is being released.
4511 * Should only be called if the map contains no valid mappings.
4514 pmap_release(pmap_t pmap)
4519 KASSERT(pmap->pm_stats.resident_count == 0,
4520 ("pmap_release: pmap %p resident count %ld != 0",
4521 pmap, pmap->pm_stats.resident_count));
4522 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4523 ("pmap_release: pmap %p has reserved page table page(s)",
4525 KASSERT(CPU_EMPTY(&pmap->pm_active),
4526 ("releasing active pmap %p", pmap));
4528 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4530 if (pmap_is_la57(pmap)) {
4531 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4532 pmap->pm_pmltop[PML5PML5I] = 0;
4534 for (i = 0; i < NKPML4E; i++) /* KVA */
4535 pmap->pm_pmltop[KPML4BASE + i] = 0;
4536 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4537 pmap->pm_pmltop[DMPML4I + i] = 0;
4538 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4539 for (i = 0; i < lm_ents; i++) /* Large Map */
4540 pmap->pm_pmltop[LMSPML4I + i] = 0;
4543 vm_page_unwire_noq(m);
4544 vm_page_free_zero(m);
4546 if (pmap->pm_pmltopu != NULL) {
4547 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4549 vm_page_unwire_noq(m);
4552 if (pmap->pm_type == PT_X86 &&
4553 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4554 rangeset_fini(&pmap->pm_pkru);
4558 kvm_size(SYSCTL_HANDLER_ARGS)
4560 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4562 return sysctl_handle_long(oidp, &ksize, 0, req);
4564 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4565 0, 0, kvm_size, "LU",
4569 kvm_free(SYSCTL_HANDLER_ARGS)
4571 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4573 return sysctl_handle_long(oidp, &kfree, 0, req);
4575 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4576 0, 0, kvm_free, "LU",
4577 "Amount of KVM free");
4580 * Allocate physical memory for the vm_page array and map it into KVA,
4581 * attempting to back the vm_pages with domain-local memory.
4584 pmap_page_array_startup(long pages)
4587 pd_entry_t *pde, newpdir;
4588 vm_offset_t va, start, end;
4593 vm_page_array_size = pages;
4595 start = VM_MIN_KERNEL_ADDRESS;
4596 end = start + pages * sizeof(struct vm_page);
4597 for (va = start; va < end; va += NBPDR) {
4598 pfn = first_page + (va - start) / sizeof(struct vm_page);
4599 domain = vm_phys_domain(ptoa(pfn));
4600 pdpe = pmap_pdpe(kernel_pmap, va);
4601 if ((*pdpe & X86_PG_V) == 0) {
4602 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4604 pagezero((void *)PHYS_TO_DMAP(pa));
4605 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4606 X86_PG_A | X86_PG_M);
4608 pde = pmap_pdpe_to_pde(pdpe, va);
4609 if ((*pde & X86_PG_V) != 0)
4610 panic("Unexpected pde");
4611 pa = vm_phys_early_alloc(domain, NBPDR);
4612 for (i = 0; i < NPDEPG; i++)
4613 dump_add_page(pa + i * PAGE_SIZE);
4614 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4615 X86_PG_M | PG_PS | pg_g | pg_nx);
4616 pde_store(pde, newpdir);
4618 vm_page_array = (vm_page_t)start;
4622 * grow the number of kernel page table entries, if needed
4625 pmap_growkernel(vm_offset_t addr)
4629 pd_entry_t *pde, newpdir;
4632 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4635 * Return if "addr" is within the range of kernel page table pages
4636 * that were preallocated during pmap bootstrap. Moreover, leave
4637 * "kernel_vm_end" and the kernel page table as they were.
4639 * The correctness of this action is based on the following
4640 * argument: vm_map_insert() allocates contiguous ranges of the
4641 * kernel virtual address space. It calls this function if a range
4642 * ends after "kernel_vm_end". If the kernel is mapped between
4643 * "kernel_vm_end" and "addr", then the range cannot begin at
4644 * "kernel_vm_end". In fact, its beginning address cannot be less
4645 * than the kernel. Thus, there is no immediate need to allocate
4646 * any new kernel page table pages between "kernel_vm_end" and
4649 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4652 addr = roundup2(addr, NBPDR);
4653 if (addr - 1 >= vm_map_max(kernel_map))
4654 addr = vm_map_max(kernel_map);
4655 while (kernel_vm_end < addr) {
4656 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4657 if ((*pdpe & X86_PG_V) == 0) {
4658 /* We need a new PDP entry */
4659 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4660 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4661 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4663 panic("pmap_growkernel: no memory to grow kernel");
4664 if ((nkpg->flags & PG_ZERO) == 0)
4665 pmap_zero_page(nkpg);
4666 paddr = VM_PAGE_TO_PHYS(nkpg);
4667 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4668 X86_PG_A | X86_PG_M);
4669 continue; /* try again */
4671 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4672 if ((*pde & X86_PG_V) != 0) {
4673 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4674 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4675 kernel_vm_end = vm_map_max(kernel_map);
4681 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4682 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4685 panic("pmap_growkernel: no memory to grow kernel");
4686 if ((nkpg->flags & PG_ZERO) == 0)
4687 pmap_zero_page(nkpg);
4688 paddr = VM_PAGE_TO_PHYS(nkpg);
4689 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4690 pde_store(pde, newpdir);
4692 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4693 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4694 kernel_vm_end = vm_map_max(kernel_map);
4700 /***************************************************
4701 * page management routines.
4702 ***************************************************/
4704 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4705 CTASSERT(_NPCM == 3);
4706 CTASSERT(_NPCPV == 168);
4708 static __inline struct pv_chunk *
4709 pv_to_chunk(pv_entry_t pv)
4712 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4715 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4717 #define PC_FREE0 0xfffffffffffffffful
4718 #define PC_FREE1 0xfffffffffffffffful
4719 #define PC_FREE2 0x000000fffffffffful
4721 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4724 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4726 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4727 "Current number of pv entry chunks");
4728 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4729 "Current number of pv entry chunks allocated");
4730 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4731 "Current number of pv entry chunks frees");
4732 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4733 "Number of times tried to get a chunk page but failed.");
4735 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4736 static int pv_entry_spare;
4738 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4739 "Current number of pv entry frees");
4740 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4741 "Current number of pv entry allocs");
4742 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4743 "Current number of pv entries");
4744 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4745 "Current number of spare pv entries");
4749 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4754 pmap_invalidate_all(pmap);
4755 if (pmap != locked_pmap)
4758 pmap_delayed_invl_finish();
4762 * We are in a serious low memory condition. Resort to
4763 * drastic measures to free some pages so we can allocate
4764 * another pv entry chunk.
4766 * Returns NULL if PV entries were reclaimed from the specified pmap.
4768 * We do not, however, unmap 2mpages because subsequent accesses will
4769 * allocate per-page pv entries until repromotion occurs, thereby
4770 * exacerbating the shortage of free pv entries.
4773 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4775 struct pv_chunks_list *pvc;
4776 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4777 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4778 struct md_page *pvh;
4780 pmap_t next_pmap, pmap;
4781 pt_entry_t *pte, tpte;
4782 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4786 struct spglist free;
4788 int bit, field, freed;
4789 bool start_di, restart;
4791 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4792 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4795 PG_G = PG_A = PG_M = PG_RW = 0;
4797 bzero(&pc_marker_b, sizeof(pc_marker_b));
4798 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4799 pc_marker = (struct pv_chunk *)&pc_marker_b;
4800 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4803 * A delayed invalidation block should already be active if
4804 * pmap_advise() or pmap_remove() called this function by way
4805 * of pmap_demote_pde_locked().
4807 start_di = pmap_not_in_di();
4809 pvc = &pv_chunks[domain];
4810 mtx_lock(&pvc->pvc_lock);
4811 pvc->active_reclaims++;
4812 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4813 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4814 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4815 SLIST_EMPTY(&free)) {
4816 next_pmap = pc->pc_pmap;
4817 if (next_pmap == NULL) {
4819 * The next chunk is a marker. However, it is
4820 * not our marker, so active_reclaims must be
4821 * > 1. Consequently, the next_chunk code
4822 * will not rotate the pv_chunks list.
4826 mtx_unlock(&pvc->pvc_lock);
4829 * A pv_chunk can only be removed from the pc_lru list
4830 * when both pc_chunks_mutex is owned and the
4831 * corresponding pmap is locked.
4833 if (pmap != next_pmap) {
4835 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4838 /* Avoid deadlock and lock recursion. */
4839 if (pmap > locked_pmap) {
4840 RELEASE_PV_LIST_LOCK(lockp);
4843 pmap_delayed_invl_start();
4844 mtx_lock(&pvc->pvc_lock);
4846 } else if (pmap != locked_pmap) {
4847 if (PMAP_TRYLOCK(pmap)) {
4849 pmap_delayed_invl_start();
4850 mtx_lock(&pvc->pvc_lock);
4853 pmap = NULL; /* pmap is not locked */
4854 mtx_lock(&pvc->pvc_lock);
4855 pc = TAILQ_NEXT(pc_marker, pc_lru);
4857 pc->pc_pmap != next_pmap)
4861 } else if (start_di)
4862 pmap_delayed_invl_start();
4863 PG_G = pmap_global_bit(pmap);
4864 PG_A = pmap_accessed_bit(pmap);
4865 PG_M = pmap_modified_bit(pmap);
4866 PG_RW = pmap_rw_bit(pmap);
4872 * Destroy every non-wired, 4 KB page mapping in the chunk.
4875 for (field = 0; field < _NPCM; field++) {
4876 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4877 inuse != 0; inuse &= ~(1UL << bit)) {
4879 pv = &pc->pc_pventry[field * 64 + bit];
4881 pde = pmap_pde(pmap, va);
4882 if ((*pde & PG_PS) != 0)
4884 pte = pmap_pde_to_pte(pde, va);
4885 if ((*pte & PG_W) != 0)
4887 tpte = pte_load_clear(pte);
4888 if ((tpte & PG_G) != 0)
4889 pmap_invalidate_page(pmap, va);
4890 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4891 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4893 if ((tpte & PG_A) != 0)
4894 vm_page_aflag_set(m, PGA_REFERENCED);
4895 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4896 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4898 if (TAILQ_EMPTY(&m->md.pv_list) &&
4899 (m->flags & PG_FICTITIOUS) == 0) {
4900 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4901 if (TAILQ_EMPTY(&pvh->pv_list)) {
4902 vm_page_aflag_clear(m,
4906 pmap_delayed_invl_page(m);
4907 pc->pc_map[field] |= 1UL << bit;
4908 pmap_unuse_pt(pmap, va, *pde, &free);
4913 mtx_lock(&pvc->pvc_lock);
4916 /* Every freed mapping is for a 4 KB page. */
4917 pmap_resident_count_dec(pmap, freed);
4918 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4919 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4920 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4921 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4922 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4923 pc->pc_map[2] == PC_FREE2) {
4924 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4925 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4926 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4927 /* Entire chunk is free; return it. */
4928 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4929 dump_drop_page(m_pc->phys_addr);
4930 mtx_lock(&pvc->pvc_lock);
4931 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4934 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4935 mtx_lock(&pvc->pvc_lock);
4936 /* One freed pv entry in locked_pmap is sufficient. */
4937 if (pmap == locked_pmap)
4940 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4941 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4942 if (pvc->active_reclaims == 1 && pmap != NULL) {
4944 * Rotate the pv chunks list so that we do not
4945 * scan the same pv chunks that could not be
4946 * freed (because they contained a wired
4947 * and/or superpage mapping) on every
4948 * invocation of reclaim_pv_chunk().
4950 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4951 MPASS(pc->pc_pmap != NULL);
4952 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4953 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4957 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4958 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4959 pvc->active_reclaims--;
4960 mtx_unlock(&pvc->pvc_lock);
4961 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4962 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4963 m_pc = SLIST_FIRST(&free);
4964 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4965 /* Recycle a freed page table page. */
4966 m_pc->ref_count = 1;
4968 vm_page_free_pages_toq(&free, true);
4973 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4978 domain = PCPU_GET(domain);
4979 for (i = 0; i < vm_ndomains; i++) {
4980 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4983 domain = (domain + 1) % vm_ndomains;
4990 * free the pv_entry back to the free list
4993 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4995 struct pv_chunk *pc;
4996 int idx, field, bit;
4998 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4999 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
5000 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
5001 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
5002 pc = pv_to_chunk(pv);
5003 idx = pv - &pc->pc_pventry[0];
5006 pc->pc_map[field] |= 1ul << bit;
5007 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5008 pc->pc_map[2] != PC_FREE2) {
5009 /* 98% of the time, pc is already at the head of the list. */
5010 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5011 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5012 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5016 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5021 free_pv_chunk_dequeued(struct pv_chunk *pc)
5025 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
5026 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
5027 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
5028 /* entire chunk is free, return it */
5029 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5030 dump_drop_page(m->phys_addr);
5031 vm_page_unwire_noq(m);
5036 free_pv_chunk(struct pv_chunk *pc)
5038 struct pv_chunks_list *pvc;
5040 pvc = &pv_chunks[pc_to_domain(pc)];
5041 mtx_lock(&pvc->pvc_lock);
5042 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5043 mtx_unlock(&pvc->pvc_lock);
5044 free_pv_chunk_dequeued(pc);
5048 free_pv_chunk_batch(struct pv_chunklist *batch)
5050 struct pv_chunks_list *pvc;
5051 struct pv_chunk *pc, *npc;
5054 for (i = 0; i < vm_ndomains; i++) {
5055 if (TAILQ_EMPTY(&batch[i]))
5057 pvc = &pv_chunks[i];
5058 mtx_lock(&pvc->pvc_lock);
5059 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5060 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5062 mtx_unlock(&pvc->pvc_lock);
5065 for (i = 0; i < vm_ndomains; i++) {
5066 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5067 free_pv_chunk_dequeued(pc);
5073 * Returns a new PV entry, allocating a new PV chunk from the system when
5074 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5075 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5078 * The given PV list lock may be released.
5081 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5083 struct pv_chunks_list *pvc;
5086 struct pv_chunk *pc;
5089 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5090 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
5092 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5094 for (field = 0; field < _NPCM; field++) {
5095 if (pc->pc_map[field]) {
5096 bit = bsfq(pc->pc_map[field]);
5100 if (field < _NPCM) {
5101 pv = &pc->pc_pventry[field * 64 + bit];
5102 pc->pc_map[field] &= ~(1ul << bit);
5103 /* If this was the last item, move it to tail */
5104 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5105 pc->pc_map[2] == 0) {
5106 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5107 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5110 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5111 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
5115 /* No free items, allocate another chunk */
5116 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5119 if (lockp == NULL) {
5120 PV_STAT(pc_chunk_tryfail++);
5123 m = reclaim_pv_chunk(pmap, lockp);
5127 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5128 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5129 dump_add_page(m->phys_addr);
5130 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5132 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5133 pc->pc_map[1] = PC_FREE1;
5134 pc->pc_map[2] = PC_FREE2;
5135 pvc = &pv_chunks[vm_phys_domain(m->phys_addr)];
5136 mtx_lock(&pvc->pvc_lock);
5137 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5138 mtx_unlock(&pvc->pvc_lock);
5139 pv = &pc->pc_pventry[0];
5140 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5141 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5142 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
5147 * Returns the number of one bits within the given PV chunk map.
5149 * The erratas for Intel processors state that "POPCNT Instruction May
5150 * Take Longer to Execute Than Expected". It is believed that the
5151 * issue is the spurious dependency on the destination register.
5152 * Provide a hint to the register rename logic that the destination
5153 * value is overwritten, by clearing it, as suggested in the
5154 * optimization manual. It should be cheap for unaffected processors
5157 * Reference numbers for erratas are
5158 * 4th Gen Core: HSD146
5159 * 5th Gen Core: BDM85
5160 * 6th Gen Core: SKL029
5163 popcnt_pc_map_pq(uint64_t *map)
5167 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5168 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5169 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5170 : "=&r" (result), "=&r" (tmp)
5171 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5176 * Ensure that the number of spare PV entries in the specified pmap meets or
5177 * exceeds the given count, "needed".
5179 * The given PV list lock may be released.
5182 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5184 struct pv_chunks_list *pvc;
5185 struct pch new_tail[PMAP_MEMDOM];
5186 struct pv_chunk *pc;
5191 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5192 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5195 * Newly allocated PV chunks must be stored in a private list until
5196 * the required number of PV chunks have been allocated. Otherwise,
5197 * reclaim_pv_chunk() could recycle one of these chunks. In
5198 * contrast, these chunks must be added to the pmap upon allocation.
5200 for (i = 0; i < PMAP_MEMDOM; i++)
5201 TAILQ_INIT(&new_tail[i]);
5204 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5206 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5207 bit_count((bitstr_t *)pc->pc_map, 0,
5208 sizeof(pc->pc_map) * NBBY, &free);
5211 free = popcnt_pc_map_pq(pc->pc_map);
5215 if (avail >= needed)
5218 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5219 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5222 m = reclaim_pv_chunk(pmap, lockp);
5227 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5228 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5229 dump_add_page(m->phys_addr);
5230 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5232 pc->pc_map[0] = PC_FREE0;
5233 pc->pc_map[1] = PC_FREE1;
5234 pc->pc_map[2] = PC_FREE2;
5235 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5236 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
5237 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
5240 * The reclaim might have freed a chunk from the current pmap.
5241 * If that chunk contained available entries, we need to
5242 * re-count the number of available entries.
5247 for (i = 0; i < vm_ndomains; i++) {
5248 if (TAILQ_EMPTY(&new_tail[i]))
5250 pvc = &pv_chunks[i];
5251 mtx_lock(&pvc->pvc_lock);
5252 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5253 mtx_unlock(&pvc->pvc_lock);
5258 * First find and then remove the pv entry for the specified pmap and virtual
5259 * address from the specified pv list. Returns the pv entry if found and NULL
5260 * otherwise. This operation can be performed on pv lists for either 4KB or
5261 * 2MB page mappings.
5263 static __inline pv_entry_t
5264 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5268 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5269 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5270 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5279 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5280 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5281 * entries for each of the 4KB page mappings.
5284 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5285 struct rwlock **lockp)
5287 struct md_page *pvh;
5288 struct pv_chunk *pc;
5290 vm_offset_t va_last;
5294 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5295 KASSERT((pa & PDRMASK) == 0,
5296 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5297 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5300 * Transfer the 2mpage's pv entry for this mapping to the first
5301 * page's pv list. Once this transfer begins, the pv list lock
5302 * must not be released until the last pv entry is reinstantiated.
5304 pvh = pa_to_pvh(pa);
5305 va = trunc_2mpage(va);
5306 pv = pmap_pvh_remove(pvh, pmap, va);
5307 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5308 m = PHYS_TO_VM_PAGE(pa);
5309 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5311 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5312 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
5313 va_last = va + NBPDR - PAGE_SIZE;
5315 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5316 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5317 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5318 for (field = 0; field < _NPCM; field++) {
5319 while (pc->pc_map[field]) {
5320 bit = bsfq(pc->pc_map[field]);
5321 pc->pc_map[field] &= ~(1ul << bit);
5322 pv = &pc->pc_pventry[field * 64 + bit];
5326 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5327 ("pmap_pv_demote_pde: page %p is not managed", m));
5328 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5334 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5335 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5338 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5339 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5340 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5342 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
5343 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
5346 #if VM_NRESERVLEVEL > 0
5348 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5349 * replace the many pv entries for the 4KB page mappings by a single pv entry
5350 * for the 2MB page mapping.
5353 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5354 struct rwlock **lockp)
5356 struct md_page *pvh;
5358 vm_offset_t va_last;
5361 KASSERT((pa & PDRMASK) == 0,
5362 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5363 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5366 * Transfer the first page's pv entry for this mapping to the 2mpage's
5367 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5368 * a transfer avoids the possibility that get_pv_entry() calls
5369 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5370 * mappings that is being promoted.
5372 m = PHYS_TO_VM_PAGE(pa);
5373 va = trunc_2mpage(va);
5374 pv = pmap_pvh_remove(&m->md, pmap, va);
5375 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5376 pvh = pa_to_pvh(pa);
5377 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5379 /* Free the remaining NPTEPG - 1 pv entries. */
5380 va_last = va + NBPDR - PAGE_SIZE;
5384 pmap_pvh_free(&m->md, pmap, va);
5385 } while (va < va_last);
5387 #endif /* VM_NRESERVLEVEL > 0 */
5390 * First find and then destroy the pv entry for the specified pmap and virtual
5391 * address. This operation can be performed on pv lists for either 4KB or 2MB
5395 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5399 pv = pmap_pvh_remove(pvh, pmap, va);
5400 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5401 free_pv_entry(pmap, pv);
5405 * Conditionally create the PV entry for a 4KB page mapping if the required
5406 * memory can be allocated without resorting to reclamation.
5409 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5410 struct rwlock **lockp)
5414 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5415 /* Pass NULL instead of the lock pointer to disable reclamation. */
5416 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5418 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5419 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5427 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5428 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5429 * false if the PV entry cannot be allocated without resorting to reclamation.
5432 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5433 struct rwlock **lockp)
5435 struct md_page *pvh;
5439 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5440 /* Pass NULL instead of the lock pointer to disable reclamation. */
5441 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5442 NULL : lockp)) == NULL)
5445 pa = pde & PG_PS_FRAME;
5446 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5447 pvh = pa_to_pvh(pa);
5448 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5454 * Fills a page table page with mappings to consecutive physical pages.
5457 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5461 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5463 newpte += PAGE_SIZE;
5468 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5469 * mapping is invalidated.
5472 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5474 struct rwlock *lock;
5478 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5485 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5489 pt_entry_t *xpte, *ypte;
5491 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5492 xpte++, newpte += PAGE_SIZE) {
5493 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5494 printf("pmap_demote_pde: xpte %zd and newpte map "
5495 "different pages: found %#lx, expected %#lx\n",
5496 xpte - firstpte, *xpte, newpte);
5497 printf("page table dump\n");
5498 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5499 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5504 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5505 ("pmap_demote_pde: firstpte and newpte map different physical"
5512 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5513 pd_entry_t oldpde, struct rwlock **lockp)
5515 struct spglist free;
5519 sva = trunc_2mpage(va);
5520 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5521 if ((oldpde & pmap_global_bit(pmap)) == 0)
5522 pmap_invalidate_pde_page(pmap, sva, oldpde);
5523 vm_page_free_pages_toq(&free, true);
5524 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5529 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5530 struct rwlock **lockp)
5532 pd_entry_t newpde, oldpde;
5533 pt_entry_t *firstpte, newpte;
5534 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5540 PG_A = pmap_accessed_bit(pmap);
5541 PG_G = pmap_global_bit(pmap);
5542 PG_M = pmap_modified_bit(pmap);
5543 PG_RW = pmap_rw_bit(pmap);
5544 PG_V = pmap_valid_bit(pmap);
5545 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5546 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5548 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5549 in_kernel = va >= VM_MAXUSER_ADDRESS;
5551 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5552 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5555 * Invalidate the 2MB page mapping and return "failure" if the
5556 * mapping was never accessed.
5558 if ((oldpde & PG_A) == 0) {
5559 KASSERT((oldpde & PG_W) == 0,
5560 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5561 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5565 mpte = pmap_remove_pt_page(pmap, va);
5567 KASSERT((oldpde & PG_W) == 0,
5568 ("pmap_demote_pde: page table page for a wired mapping"
5572 * If the page table page is missing and the mapping
5573 * is for a kernel address, the mapping must belong to
5574 * the direct map. Page table pages are preallocated
5575 * for every other part of the kernel address space,
5576 * so the direct map region is the only part of the
5577 * kernel address space that must be handled here.
5579 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5580 va < DMAP_MAX_ADDRESS),
5581 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5584 * If the 2MB page mapping belongs to the direct map
5585 * region of the kernel's address space, then the page
5586 * allocation request specifies the highest possible
5587 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5588 * priority is normal.
5590 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5591 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5592 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5595 * If the allocation of the new page table page fails,
5596 * invalidate the 2MB page mapping and return "failure".
5599 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5604 mpte->ref_count = NPTEPG;
5605 pmap_resident_count_inc(pmap, 1);
5608 mptepa = VM_PAGE_TO_PHYS(mpte);
5609 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5610 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5611 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5612 ("pmap_demote_pde: oldpde is missing PG_M"));
5613 newpte = oldpde & ~PG_PS;
5614 newpte = pmap_swap_pat(pmap, newpte);
5617 * If the page table page is not leftover from an earlier promotion,
5620 if (mpte->valid == 0)
5621 pmap_fill_ptp(firstpte, newpte);
5623 pmap_demote_pde_check(firstpte, newpte);
5626 * If the mapping has changed attributes, update the page table
5629 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5630 pmap_fill_ptp(firstpte, newpte);
5633 * The spare PV entries must be reserved prior to demoting the
5634 * mapping, that is, prior to changing the PDE. Otherwise, the state
5635 * of the PDE and the PV lists will be inconsistent, which can result
5636 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5637 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5638 * PV entry for the 2MB page mapping that is being demoted.
5640 if ((oldpde & PG_MANAGED) != 0)
5641 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5644 * Demote the mapping. This pmap is locked. The old PDE has
5645 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5646 * set. Thus, there is no danger of a race with another
5647 * processor changing the setting of PG_A and/or PG_M between
5648 * the read above and the store below.
5650 if (workaround_erratum383)
5651 pmap_update_pde(pmap, va, pde, newpde);
5653 pde_store(pde, newpde);
5656 * Invalidate a stale recursive mapping of the page table page.
5659 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5662 * Demote the PV entry.
5664 if ((oldpde & PG_MANAGED) != 0)
5665 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5667 atomic_add_long(&pmap_pde_demotions, 1);
5668 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5674 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5677 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5683 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5684 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5685 mpte = pmap_remove_pt_page(pmap, va);
5687 panic("pmap_remove_kernel_pde: Missing pt page.");
5689 mptepa = VM_PAGE_TO_PHYS(mpte);
5690 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5693 * If this page table page was unmapped by a promotion, then it
5694 * contains valid mappings. Zero it to invalidate those mappings.
5696 if (mpte->valid != 0)
5697 pagezero((void *)PHYS_TO_DMAP(mptepa));
5700 * Demote the mapping.
5702 if (workaround_erratum383)
5703 pmap_update_pde(pmap, va, pde, newpde);
5705 pde_store(pde, newpde);
5708 * Invalidate a stale recursive mapping of the page table page.
5710 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5714 * pmap_remove_pde: do the things to unmap a superpage in a process
5717 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5718 struct spglist *free, struct rwlock **lockp)
5720 struct md_page *pvh;
5722 vm_offset_t eva, va;
5724 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5726 PG_G = pmap_global_bit(pmap);
5727 PG_A = pmap_accessed_bit(pmap);
5728 PG_M = pmap_modified_bit(pmap);
5729 PG_RW = pmap_rw_bit(pmap);
5731 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5732 KASSERT((sva & PDRMASK) == 0,
5733 ("pmap_remove_pde: sva is not 2mpage aligned"));
5734 oldpde = pte_load_clear(pdq);
5736 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5737 if ((oldpde & PG_G) != 0)
5738 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5739 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5740 if (oldpde & PG_MANAGED) {
5741 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5742 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5743 pmap_pvh_free(pvh, pmap, sva);
5745 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5746 va < eva; va += PAGE_SIZE, m++) {
5747 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5750 vm_page_aflag_set(m, PGA_REFERENCED);
5751 if (TAILQ_EMPTY(&m->md.pv_list) &&
5752 TAILQ_EMPTY(&pvh->pv_list))
5753 vm_page_aflag_clear(m, PGA_WRITEABLE);
5754 pmap_delayed_invl_page(m);
5757 if (pmap == kernel_pmap) {
5758 pmap_remove_kernel_pde(pmap, pdq, sva);
5760 mpte = pmap_remove_pt_page(pmap, sva);
5762 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5763 ("pmap_remove_pde: pte page not promoted"));
5764 pmap_resident_count_dec(pmap, 1);
5765 KASSERT(mpte->ref_count == NPTEPG,
5766 ("pmap_remove_pde: pte page ref count error"));
5767 mpte->ref_count = 0;
5768 pmap_add_delayed_free_list(mpte, free, FALSE);
5771 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5775 * pmap_remove_pte: do the things to unmap a page in a process
5778 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5779 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5781 struct md_page *pvh;
5782 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5785 PG_A = pmap_accessed_bit(pmap);
5786 PG_M = pmap_modified_bit(pmap);
5787 PG_RW = pmap_rw_bit(pmap);
5789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5790 oldpte = pte_load_clear(ptq);
5792 pmap->pm_stats.wired_count -= 1;
5793 pmap_resident_count_dec(pmap, 1);
5794 if (oldpte & PG_MANAGED) {
5795 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5796 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5799 vm_page_aflag_set(m, PGA_REFERENCED);
5800 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5801 pmap_pvh_free(&m->md, pmap, va);
5802 if (TAILQ_EMPTY(&m->md.pv_list) &&
5803 (m->flags & PG_FICTITIOUS) == 0) {
5804 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5805 if (TAILQ_EMPTY(&pvh->pv_list))
5806 vm_page_aflag_clear(m, PGA_WRITEABLE);
5808 pmap_delayed_invl_page(m);
5810 return (pmap_unuse_pt(pmap, va, ptepde, free));
5814 * Remove a single page from a process address space
5817 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5818 struct spglist *free)
5820 struct rwlock *lock;
5821 pt_entry_t *pte, PG_V;
5823 PG_V = pmap_valid_bit(pmap);
5824 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5825 if ((*pde & PG_V) == 0)
5827 pte = pmap_pde_to_pte(pde, va);
5828 if ((*pte & PG_V) == 0)
5831 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5834 pmap_invalidate_page(pmap, va);
5838 * Removes the specified range of addresses from the page table page.
5841 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5842 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5844 pt_entry_t PG_G, *pte;
5848 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5849 PG_G = pmap_global_bit(pmap);
5852 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5856 pmap_invalidate_range(pmap, va, sva);
5861 if ((*pte & PG_G) == 0)
5865 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5871 pmap_invalidate_range(pmap, va, sva);
5876 * Remove the given range of addresses from the specified map.
5878 * It is assumed that the start and end are properly
5879 * rounded to the page size.
5882 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5884 struct rwlock *lock;
5886 vm_offset_t va_next;
5887 pml5_entry_t *pml5e;
5888 pml4_entry_t *pml4e;
5890 pd_entry_t ptpaddr, *pde;
5891 pt_entry_t PG_G, PG_V;
5892 struct spglist free;
5895 PG_G = pmap_global_bit(pmap);
5896 PG_V = pmap_valid_bit(pmap);
5899 * Perform an unsynchronized read. This is, however, safe.
5901 if (pmap->pm_stats.resident_count == 0)
5907 pmap_delayed_invl_start();
5909 pmap_pkru_on_remove(pmap, sva, eva);
5912 * special handling of removing one page. a very
5913 * common operation and easy to short circuit some
5916 if (sva + PAGE_SIZE == eva) {
5917 pde = pmap_pde(pmap, sva);
5918 if (pde && (*pde & PG_PS) == 0) {
5919 pmap_remove_page(pmap, sva, pde, &free);
5925 for (; sva < eva; sva = va_next) {
5926 if (pmap->pm_stats.resident_count == 0)
5929 if (pmap_is_la57(pmap)) {
5930 pml5e = pmap_pml5e(pmap, sva);
5931 if ((*pml5e & PG_V) == 0) {
5932 va_next = (sva + NBPML5) & ~PML5MASK;
5937 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
5939 pml4e = pmap_pml4e(pmap, sva);
5941 if ((*pml4e & PG_V) == 0) {
5942 va_next = (sva + NBPML4) & ~PML4MASK;
5948 va_next = (sva + NBPDP) & ~PDPMASK;
5951 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5952 if ((*pdpe & PG_V) == 0)
5954 if ((*pdpe & PG_PS) != 0) {
5955 KASSERT(va_next <= eva,
5956 ("partial update of non-transparent 1G mapping "
5957 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
5958 *pdpe, sva, eva, va_next));
5959 MPASS(pmap != kernel_pmap); /* XXXKIB */
5960 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
5963 pmap_resident_count_dec(pmap, NBPDP / PAGE_SIZE);
5964 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
5965 pmap_unwire_ptp(pmap, sva, mt, &free);
5970 * Calculate index for next page table.
5972 va_next = (sva + NBPDR) & ~PDRMASK;
5976 pde = pmap_pdpe_to_pde(pdpe, sva);
5980 * Weed out invalid mappings.
5986 * Check for large page.
5988 if ((ptpaddr & PG_PS) != 0) {
5990 * Are we removing the entire large page? If not,
5991 * demote the mapping and fall through.
5993 if (sva + NBPDR == va_next && eva >= va_next) {
5995 * The TLB entry for a PG_G mapping is
5996 * invalidated by pmap_remove_pde().
5998 if ((ptpaddr & PG_G) == 0)
6000 pmap_remove_pde(pmap, pde, sva, &free, &lock);
6002 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
6004 /* The large page mapping was destroyed. */
6011 * Limit our scan to either the end of the va represented
6012 * by the current page table page, or to the end of the
6013 * range being removed.
6018 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6025 pmap_invalidate_all(pmap);
6027 pmap_delayed_invl_finish();
6028 vm_page_free_pages_toq(&free, true);
6032 * Routine: pmap_remove_all
6034 * Removes this physical page from
6035 * all physical maps in which it resides.
6036 * Reflects back modify bits to the pager.
6039 * Original versions of this routine were very
6040 * inefficient because they iteratively called
6041 * pmap_remove (slow...)
6045 pmap_remove_all(vm_page_t m)
6047 struct md_page *pvh;
6050 struct rwlock *lock;
6051 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6054 struct spglist free;
6055 int pvh_gen, md_gen;
6057 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6058 ("pmap_remove_all: page %p is not managed", m));
6060 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6061 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6062 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6065 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6067 if (!PMAP_TRYLOCK(pmap)) {
6068 pvh_gen = pvh->pv_gen;
6072 if (pvh_gen != pvh->pv_gen) {
6079 pde = pmap_pde(pmap, va);
6080 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6083 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6085 if (!PMAP_TRYLOCK(pmap)) {
6086 pvh_gen = pvh->pv_gen;
6087 md_gen = m->md.pv_gen;
6091 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6097 PG_A = pmap_accessed_bit(pmap);
6098 PG_M = pmap_modified_bit(pmap);
6099 PG_RW = pmap_rw_bit(pmap);
6100 pmap_resident_count_dec(pmap, 1);
6101 pde = pmap_pde(pmap, pv->pv_va);
6102 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6103 " a 2mpage in page %p's pv list", m));
6104 pte = pmap_pde_to_pte(pde, pv->pv_va);
6105 tpte = pte_load_clear(pte);
6107 pmap->pm_stats.wired_count--;
6109 vm_page_aflag_set(m, PGA_REFERENCED);
6112 * Update the vm_page_t clean and reference bits.
6114 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6116 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6117 pmap_invalidate_page(pmap, pv->pv_va);
6118 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6120 free_pv_entry(pmap, pv);
6123 vm_page_aflag_clear(m, PGA_WRITEABLE);
6125 pmap_delayed_invl_wait(m);
6126 vm_page_free_pages_toq(&free, true);
6130 * pmap_protect_pde: do the things to protect a 2mpage in a process
6133 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6135 pd_entry_t newpde, oldpde;
6137 boolean_t anychanged;
6138 pt_entry_t PG_G, PG_M, PG_RW;
6140 PG_G = pmap_global_bit(pmap);
6141 PG_M = pmap_modified_bit(pmap);
6142 PG_RW = pmap_rw_bit(pmap);
6144 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6145 KASSERT((sva & PDRMASK) == 0,
6146 ("pmap_protect_pde: sva is not 2mpage aligned"));
6149 oldpde = newpde = *pde;
6150 if ((prot & VM_PROT_WRITE) == 0) {
6151 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6152 (PG_MANAGED | PG_M | PG_RW)) {
6153 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6154 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6157 newpde &= ~(PG_RW | PG_M);
6159 if ((prot & VM_PROT_EXECUTE) == 0)
6161 if (newpde != oldpde) {
6163 * As an optimization to future operations on this PDE, clear
6164 * PG_PROMOTED. The impending invalidation will remove any
6165 * lingering 4KB page mappings from the TLB.
6167 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6169 if ((oldpde & PG_G) != 0)
6170 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6174 return (anychanged);
6178 * Set the physical protection on the
6179 * specified range of this map as requested.
6182 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6185 vm_offset_t va_next;
6186 pml4_entry_t *pml4e;
6188 pd_entry_t ptpaddr, *pde;
6189 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6190 pt_entry_t obits, pbits;
6191 boolean_t anychanged;
6193 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6194 if (prot == VM_PROT_NONE) {
6195 pmap_remove(pmap, sva, eva);
6199 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6200 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6203 PG_G = pmap_global_bit(pmap);
6204 PG_M = pmap_modified_bit(pmap);
6205 PG_V = pmap_valid_bit(pmap);
6206 PG_RW = pmap_rw_bit(pmap);
6210 * Although this function delays and batches the invalidation
6211 * of stale TLB entries, it does not need to call
6212 * pmap_delayed_invl_start() and
6213 * pmap_delayed_invl_finish(), because it does not
6214 * ordinarily destroy mappings. Stale TLB entries from
6215 * protection-only changes need only be invalidated before the
6216 * pmap lock is released, because protection-only changes do
6217 * not destroy PV entries. Even operations that iterate over
6218 * a physical page's PV list of mappings, like
6219 * pmap_remove_write(), acquire the pmap lock for each
6220 * mapping. Consequently, for protection-only changes, the
6221 * pmap lock suffices to synchronize both page table and TLB
6224 * This function only destroys a mapping if pmap_demote_pde()
6225 * fails. In that case, stale TLB entries are immediately
6230 for (; sva < eva; sva = va_next) {
6231 pml4e = pmap_pml4e(pmap, sva);
6232 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6233 va_next = (sva + NBPML4) & ~PML4MASK;
6239 va_next = (sva + NBPDP) & ~PDPMASK;
6242 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6243 if ((*pdpe & PG_V) == 0)
6245 if ((*pdpe & PG_PS) != 0) {
6246 KASSERT(va_next <= eva,
6247 ("partial update of non-transparent 1G mapping "
6248 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6249 *pdpe, sva, eva, va_next));
6251 obits = pbits = *pdpe;
6252 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6253 MPASS(pmap != kernel_pmap); /* XXXKIB */
6254 if ((prot & VM_PROT_WRITE) == 0)
6255 pbits &= ~(PG_RW | PG_M);
6256 if ((prot & VM_PROT_EXECUTE) == 0)
6259 if (pbits != obits) {
6260 if (!atomic_cmpset_long(pdpe, obits, pbits))
6261 /* PG_PS cannot be cleared under us, */
6268 va_next = (sva + NBPDR) & ~PDRMASK;
6272 pde = pmap_pdpe_to_pde(pdpe, sva);
6276 * Weed out invalid mappings.
6282 * Check for large page.
6284 if ((ptpaddr & PG_PS) != 0) {
6286 * Are we protecting the entire large page? If not,
6287 * demote the mapping and fall through.
6289 if (sva + NBPDR == va_next && eva >= va_next) {
6291 * The TLB entry for a PG_G mapping is
6292 * invalidated by pmap_protect_pde().
6294 if (pmap_protect_pde(pmap, pde, sva, prot))
6297 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6299 * The large page mapping was destroyed.
6308 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6311 obits = pbits = *pte;
6312 if ((pbits & PG_V) == 0)
6315 if ((prot & VM_PROT_WRITE) == 0) {
6316 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6317 (PG_MANAGED | PG_M | PG_RW)) {
6318 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6321 pbits &= ~(PG_RW | PG_M);
6323 if ((prot & VM_PROT_EXECUTE) == 0)
6326 if (pbits != obits) {
6327 if (!atomic_cmpset_long(pte, obits, pbits))
6330 pmap_invalidate_page(pmap, sva);
6337 pmap_invalidate_all(pmap);
6341 #if VM_NRESERVLEVEL > 0
6343 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6346 if (pmap->pm_type != PT_EPT)
6348 return ((pde & EPT_PG_EXECUTE) != 0);
6352 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6353 * single page table page (PTP) to a single 2MB page mapping. For promotion
6354 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6355 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6356 * identical characteristics.
6359 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6360 struct rwlock **lockp)
6363 pt_entry_t *firstpte, oldpte, pa, *pte;
6364 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6368 PG_A = pmap_accessed_bit(pmap);
6369 PG_G = pmap_global_bit(pmap);
6370 PG_M = pmap_modified_bit(pmap);
6371 PG_V = pmap_valid_bit(pmap);
6372 PG_RW = pmap_rw_bit(pmap);
6373 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6374 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6376 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6379 * Examine the first PTE in the specified PTP. Abort if this PTE is
6380 * either invalid, unused, or does not map the first 4KB physical page
6381 * within a 2MB page.
6383 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6386 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6387 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6389 atomic_add_long(&pmap_pde_p_failures, 1);
6390 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6391 " in pmap %p", va, pmap);
6394 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6396 * When PG_M is already clear, PG_RW can be cleared without
6397 * a TLB invalidation.
6399 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6405 * Examine each of the other PTEs in the specified PTP. Abort if this
6406 * PTE maps an unexpected 4KB physical page or does not have identical
6407 * characteristics to the first PTE.
6409 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6410 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6413 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6414 atomic_add_long(&pmap_pde_p_failures, 1);
6415 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6416 " in pmap %p", va, pmap);
6419 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6421 * When PG_M is already clear, PG_RW can be cleared
6422 * without a TLB invalidation.
6424 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6427 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6428 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6429 (va & ~PDRMASK), pmap);
6431 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6432 atomic_add_long(&pmap_pde_p_failures, 1);
6433 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6434 " in pmap %p", va, pmap);
6441 * Save the page table page in its current state until the PDE
6442 * mapping the superpage is demoted by pmap_demote_pde() or
6443 * destroyed by pmap_remove_pde().
6445 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6446 KASSERT(mpte >= vm_page_array &&
6447 mpte < &vm_page_array[vm_page_array_size],
6448 ("pmap_promote_pde: page table page is out of range"));
6449 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6450 ("pmap_promote_pde: page table page's pindex is wrong"));
6451 if (pmap_insert_pt_page(pmap, mpte, true)) {
6452 atomic_add_long(&pmap_pde_p_failures, 1);
6454 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6460 * Promote the pv entries.
6462 if ((newpde & PG_MANAGED) != 0)
6463 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6466 * Propagate the PAT index to its proper position.
6468 newpde = pmap_swap_pat(pmap, newpde);
6471 * Map the superpage.
6473 if (workaround_erratum383)
6474 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6476 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6478 atomic_add_long(&pmap_pde_promotions, 1);
6479 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6480 " in pmap %p", va, pmap);
6482 #endif /* VM_NRESERVLEVEL > 0 */
6485 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6489 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6491 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6492 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6493 ("psind %d unexpected", psind));
6494 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6495 ("unaligned phys address %#lx newpte %#lx psind %d",
6496 newpte & PG_FRAME, newpte, psind));
6497 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6498 ("unaligned va %#lx psind %d", va, psind));
6499 KASSERT(va < VM_MAXUSER_ADDRESS,
6500 ("kernel mode non-transparent superpage")); /* XXXKIB */
6501 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6502 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6504 PG_V = pmap_valid_bit(pmap);
6507 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6508 return (KERN_PROTECTION_FAILURE);
6510 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6511 pten |= pmap_pkru_get(pmap, va);
6513 if (psind == 2) { /* 1G */
6514 pml4e = pmap_pml4e(pmap, va);
6515 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6516 mp = _pmap_allocpte(pmap, pmap_pml4e_pindex(va),
6520 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6521 pdpe = &pdpe[pmap_pdpe_index(va)];
6523 MPASS(origpte == 0);
6525 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6526 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6528 if ((origpte & PG_V) == 0) {
6529 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6534 } else /* (psind == 1) */ { /* 2M */
6535 pde = pmap_pde(pmap, va);
6537 mp = _pmap_allocpte(pmap, pmap_pdpe_pindex(va),
6541 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6542 pde = &pde[pmap_pde_index(va)];
6544 MPASS(origpte == 0);
6547 if ((origpte & PG_V) == 0) {
6548 pdpe = pmap_pdpe(pmap, va);
6549 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6550 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6556 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6557 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6558 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6559 va, psind == 2 ? "1G" : "2M", origpte, pten));
6560 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6561 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6562 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6563 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6564 if ((origpte & PG_V) == 0)
6565 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
6567 return (KERN_SUCCESS);
6570 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6571 return (KERN_RESOURCE_SHORTAGE);
6579 * Insert the given physical page (p) at
6580 * the specified virtual address (v) in the
6581 * target physical map with the protection requested.
6583 * If specified, the page will be wired down, meaning
6584 * that the related pte can not be reclaimed.
6586 * NB: This is the only routine which MAY NOT lazy-evaluate
6587 * or lose information. That is, this routine must actually
6588 * insert this page into the given map NOW.
6590 * When destroying both a page table and PV entry, this function
6591 * performs the TLB invalidation before releasing the PV list
6592 * lock, so we do not need pmap_delayed_invl_page() calls here.
6595 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6596 u_int flags, int8_t psind)
6598 struct rwlock *lock;
6600 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6601 pt_entry_t newpte, origpte;
6608 PG_A = pmap_accessed_bit(pmap);
6609 PG_G = pmap_global_bit(pmap);
6610 PG_M = pmap_modified_bit(pmap);
6611 PG_V = pmap_valid_bit(pmap);
6612 PG_RW = pmap_rw_bit(pmap);
6614 va = trunc_page(va);
6615 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6616 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6617 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6619 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6620 va >= kmi.clean_eva,
6621 ("pmap_enter: managed mapping within the clean submap"));
6622 if ((m->oflags & VPO_UNMANAGED) == 0)
6623 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6624 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6625 ("pmap_enter: flags %u has reserved bits set", flags));
6626 pa = VM_PAGE_TO_PHYS(m);
6627 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6628 if ((flags & VM_PROT_WRITE) != 0)
6630 if ((prot & VM_PROT_WRITE) != 0)
6632 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6633 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6634 if ((prot & VM_PROT_EXECUTE) == 0)
6636 if ((flags & PMAP_ENTER_WIRED) != 0)
6638 if (va < VM_MAXUSER_ADDRESS)
6640 if (pmap == kernel_pmap)
6642 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6645 * Set modified bit gratuitously for writeable mappings if
6646 * the page is unmanaged. We do not want to take a fault
6647 * to do the dirty bit accounting for these mappings.
6649 if ((m->oflags & VPO_UNMANAGED) != 0) {
6650 if ((newpte & PG_RW) != 0)
6653 newpte |= PG_MANAGED;
6657 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6658 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6659 ("managed largepage va %#lx flags %#x", va, flags));
6660 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6665 /* Assert the required virtual and physical alignment. */
6666 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6667 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6668 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6674 * In the case that a page table page is not
6675 * resident, we are creating it here.
6678 pde = pmap_pde(pmap, va);
6679 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6680 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6681 pte = pmap_pde_to_pte(pde, va);
6682 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6683 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6686 } else if (va < VM_MAXUSER_ADDRESS) {
6688 * Here if the pte page isn't mapped, or if it has been
6691 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6692 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6693 nosleep ? NULL : &lock, va);
6694 if (mpte == NULL && nosleep) {
6695 rv = KERN_RESOURCE_SHORTAGE;
6700 panic("pmap_enter: invalid page directory va=%#lx", va);
6704 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6705 newpte |= pmap_pkru_get(pmap, va);
6708 * Is the specified virtual address already mapped?
6710 if ((origpte & PG_V) != 0) {
6712 * Wiring change, just update stats. We don't worry about
6713 * wiring PT pages as they remain resident as long as there
6714 * are valid mappings in them. Hence, if a user page is wired,
6715 * the PT page will be also.
6717 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6718 pmap->pm_stats.wired_count++;
6719 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6720 pmap->pm_stats.wired_count--;
6723 * Remove the extra PT page reference.
6727 KASSERT(mpte->ref_count > 0,
6728 ("pmap_enter: missing reference to page table page,"
6733 * Has the physical page changed?
6735 opa = origpte & PG_FRAME;
6738 * No, might be a protection or wiring change.
6740 if ((origpte & PG_MANAGED) != 0 &&
6741 (newpte & PG_RW) != 0)
6742 vm_page_aflag_set(m, PGA_WRITEABLE);
6743 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6749 * The physical page has changed. Temporarily invalidate
6750 * the mapping. This ensures that all threads sharing the
6751 * pmap keep a consistent view of the mapping, which is
6752 * necessary for the correct handling of COW faults. It
6753 * also permits reuse of the old mapping's PV entry,
6754 * avoiding an allocation.
6756 * For consistency, handle unmanaged mappings the same way.
6758 origpte = pte_load_clear(pte);
6759 KASSERT((origpte & PG_FRAME) == opa,
6760 ("pmap_enter: unexpected pa update for %#lx", va));
6761 if ((origpte & PG_MANAGED) != 0) {
6762 om = PHYS_TO_VM_PAGE(opa);
6765 * The pmap lock is sufficient to synchronize with
6766 * concurrent calls to pmap_page_test_mappings() and
6767 * pmap_ts_referenced().
6769 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6771 if ((origpte & PG_A) != 0) {
6772 pmap_invalidate_page(pmap, va);
6773 vm_page_aflag_set(om, PGA_REFERENCED);
6775 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6776 pv = pmap_pvh_remove(&om->md, pmap, va);
6778 ("pmap_enter: no PV entry for %#lx", va));
6779 if ((newpte & PG_MANAGED) == 0)
6780 free_pv_entry(pmap, pv);
6781 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6782 TAILQ_EMPTY(&om->md.pv_list) &&
6783 ((om->flags & PG_FICTITIOUS) != 0 ||
6784 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6785 vm_page_aflag_clear(om, PGA_WRITEABLE);
6788 * Since this mapping is unmanaged, assume that PG_A
6791 pmap_invalidate_page(pmap, va);
6796 * Increment the counters.
6798 if ((newpte & PG_W) != 0)
6799 pmap->pm_stats.wired_count++;
6800 pmap_resident_count_inc(pmap, 1);
6804 * Enter on the PV list if part of our managed memory.
6806 if ((newpte & PG_MANAGED) != 0) {
6808 pv = get_pv_entry(pmap, &lock);
6811 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6812 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6814 if ((newpte & PG_RW) != 0)
6815 vm_page_aflag_set(m, PGA_WRITEABLE);
6821 if ((origpte & PG_V) != 0) {
6823 origpte = pte_load_store(pte, newpte);
6824 KASSERT((origpte & PG_FRAME) == pa,
6825 ("pmap_enter: unexpected pa update for %#lx", va));
6826 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6828 if ((origpte & PG_MANAGED) != 0)
6832 * Although the PTE may still have PG_RW set, TLB
6833 * invalidation may nonetheless be required because
6834 * the PTE no longer has PG_M set.
6836 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6838 * This PTE change does not require TLB invalidation.
6842 if ((origpte & PG_A) != 0)
6843 pmap_invalidate_page(pmap, va);
6845 pte_store(pte, newpte);
6849 #if VM_NRESERVLEVEL > 0
6851 * If both the page table page and the reservation are fully
6852 * populated, then attempt promotion.
6854 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6855 pmap_ps_enabled(pmap) &&
6856 (m->flags & PG_FICTITIOUS) == 0 &&
6857 vm_reserv_level_iffullpop(m) == 0)
6858 pmap_promote_pde(pmap, pde, va, &lock);
6870 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6871 * if successful. Returns false if (1) a page table page cannot be allocated
6872 * without sleeping, (2) a mapping already exists at the specified virtual
6873 * address, or (3) a PV entry cannot be allocated without reclaiming another
6877 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6878 struct rwlock **lockp)
6883 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6884 PG_V = pmap_valid_bit(pmap);
6885 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6887 if ((m->oflags & VPO_UNMANAGED) == 0)
6888 newpde |= PG_MANAGED;
6889 if ((prot & VM_PROT_EXECUTE) == 0)
6891 if (va < VM_MAXUSER_ADDRESS)
6893 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6894 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6899 * Returns true if every page table entry in the specified page table page is
6903 pmap_every_pte_zero(vm_paddr_t pa)
6905 pt_entry_t *pt_end, *pte;
6907 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6908 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6909 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6917 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6918 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6919 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6920 * a mapping already exists at the specified virtual address. Returns
6921 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6922 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6923 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6925 * The parameter "m" is only used when creating a managed, writeable mapping.
6928 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6929 vm_page_t m, struct rwlock **lockp)
6931 struct spglist free;
6932 pd_entry_t oldpde, *pde;
6933 pt_entry_t PG_G, PG_RW, PG_V;
6936 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6937 ("pmap_enter_pde: cannot create wired user mapping"));
6938 PG_G = pmap_global_bit(pmap);
6939 PG_RW = pmap_rw_bit(pmap);
6940 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6941 ("pmap_enter_pde: newpde is missing PG_M"));
6942 PG_V = pmap_valid_bit(pmap);
6943 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6945 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6947 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6948 " in pmap %p", va, pmap);
6949 return (KERN_FAILURE);
6951 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6952 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6953 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6954 " in pmap %p", va, pmap);
6955 return (KERN_RESOURCE_SHORTAGE);
6959 * If pkru is not same for the whole pde range, return failure
6960 * and let vm_fault() cope. Check after pde allocation, since
6963 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6964 pmap_abort_ptp(pmap, va, pdpg);
6965 return (KERN_FAILURE);
6967 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6968 newpde &= ~X86_PG_PKU_MASK;
6969 newpde |= pmap_pkru_get(pmap, va);
6973 * If there are existing mappings, either abort or remove them.
6976 if ((oldpde & PG_V) != 0) {
6977 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6978 ("pmap_enter_pde: pdpg's reference count is too low"));
6979 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6980 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6981 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6984 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6985 " in pmap %p", va, pmap);
6986 return (KERN_FAILURE);
6988 /* Break the existing mapping(s). */
6990 if ((oldpde & PG_PS) != 0) {
6992 * The reference to the PD page that was acquired by
6993 * pmap_alloc_pde() ensures that it won't be freed.
6994 * However, if the PDE resulted from a promotion, then
6995 * a reserved PT page could be freed.
6997 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6998 if ((oldpde & PG_G) == 0)
6999 pmap_invalidate_pde_page(pmap, va, oldpde);
7001 pmap_delayed_invl_start();
7002 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
7004 pmap_invalidate_all(pmap);
7005 pmap_delayed_invl_finish();
7007 if (va < VM_MAXUSER_ADDRESS) {
7008 vm_page_free_pages_toq(&free, true);
7009 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7012 KASSERT(SLIST_EMPTY(&free),
7013 ("pmap_enter_pde: freed kernel page table page"));
7016 * Both pmap_remove_pde() and pmap_remove_ptes() will
7017 * leave the kernel page table page zero filled.
7019 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7020 if (pmap_insert_pt_page(pmap, mt, false))
7021 panic("pmap_enter_pde: trie insert failed");
7025 if ((newpde & PG_MANAGED) != 0) {
7027 * Abort this mapping if its PV entry could not be created.
7029 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7031 pmap_abort_ptp(pmap, va, pdpg);
7032 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7033 " in pmap %p", va, pmap);
7034 return (KERN_RESOURCE_SHORTAGE);
7036 if ((newpde & PG_RW) != 0) {
7037 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7038 vm_page_aflag_set(mt, PGA_WRITEABLE);
7043 * Increment counters.
7045 if ((newpde & PG_W) != 0)
7046 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7047 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7050 * Map the superpage. (This is not a promoted mapping; there will not
7051 * be any lingering 4KB page mappings in the TLB.)
7053 pde_store(pde, newpde);
7055 atomic_add_long(&pmap_pde_mappings, 1);
7056 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7058 return (KERN_SUCCESS);
7062 * Maps a sequence of resident pages belonging to the same object.
7063 * The sequence begins with the given page m_start. This page is
7064 * mapped at the given virtual address start. Each subsequent page is
7065 * mapped at a virtual address that is offset from start by the same
7066 * amount as the page is offset from m_start within the object. The
7067 * last page in the sequence is the page with the largest offset from
7068 * m_start that can be mapped at a virtual address less than the given
7069 * virtual address end. Not every virtual page between start and end
7070 * is mapped; only those for which a resident page exists with the
7071 * corresponding offset from m_start are mapped.
7074 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7075 vm_page_t m_start, vm_prot_t prot)
7077 struct rwlock *lock;
7080 vm_pindex_t diff, psize;
7082 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7084 psize = atop(end - start);
7089 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7090 va = start + ptoa(diff);
7091 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7092 m->psind == 1 && pmap_ps_enabled(pmap) &&
7093 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
7094 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7095 m = &m[NBPDR / PAGE_SIZE - 1];
7097 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7099 m = TAILQ_NEXT(m, listq);
7107 * this code makes some *MAJOR* assumptions:
7108 * 1. Current pmap & pmap exists.
7111 * 4. No page table pages.
7112 * but is *MUCH* faster than pmap_enter...
7116 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7118 struct rwlock *lock;
7122 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7129 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7130 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7132 pt_entry_t newpte, *pte, PG_V;
7134 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
7135 (m->oflags & VPO_UNMANAGED) != 0,
7136 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7137 PG_V = pmap_valid_bit(pmap);
7138 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7141 * In the case that a page table page is not
7142 * resident, we are creating it here.
7144 if (va < VM_MAXUSER_ADDRESS) {
7145 vm_pindex_t ptepindex;
7149 * Calculate pagetable page index
7151 ptepindex = pmap_pde_pindex(va);
7152 if (mpte && (mpte->pindex == ptepindex)) {
7156 * Get the page directory entry
7158 ptepa = pmap_pde(pmap, va);
7161 * If the page table page is mapped, we just increment
7162 * the hold count, and activate it. Otherwise, we
7163 * attempt to allocate a page table page. If this
7164 * attempt fails, we don't retry. Instead, we give up.
7166 if (ptepa && (*ptepa & PG_V) != 0) {
7169 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7173 * Pass NULL instead of the PV list lock
7174 * pointer, because we don't intend to sleep.
7176 mpte = _pmap_allocpte(pmap, ptepindex, NULL,
7182 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7183 pte = &pte[pmap_pte_index(va)];
7195 * Enter on the PV list if part of our managed memory.
7197 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7198 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7200 pmap_abort_ptp(pmap, va, mpte);
7205 * Increment counters
7207 pmap_resident_count_inc(pmap, 1);
7209 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7210 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7211 if ((m->oflags & VPO_UNMANAGED) == 0)
7212 newpte |= PG_MANAGED;
7213 if ((prot & VM_PROT_EXECUTE) == 0)
7215 if (va < VM_MAXUSER_ADDRESS)
7216 newpte |= PG_U | pmap_pkru_get(pmap, va);
7217 pte_store(pte, newpte);
7222 * Make a temporary mapping for a physical address. This is only intended
7223 * to be used for panic dumps.
7226 pmap_kenter_temporary(vm_paddr_t pa, int i)
7230 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7231 pmap_kenter(va, pa);
7233 return ((void *)crashdumpmap);
7237 * This code maps large physical mmap regions into the
7238 * processor address space. Note that some shortcuts
7239 * are taken, but the code works.
7242 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7243 vm_pindex_t pindex, vm_size_t size)
7246 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7247 vm_paddr_t pa, ptepa;
7251 PG_A = pmap_accessed_bit(pmap);
7252 PG_M = pmap_modified_bit(pmap);
7253 PG_V = pmap_valid_bit(pmap);
7254 PG_RW = pmap_rw_bit(pmap);
7256 VM_OBJECT_ASSERT_WLOCKED(object);
7257 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7258 ("pmap_object_init_pt: non-device object"));
7259 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7260 if (!pmap_ps_enabled(pmap))
7262 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7264 p = vm_page_lookup(object, pindex);
7265 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7266 ("pmap_object_init_pt: invalid page %p", p));
7267 pat_mode = p->md.pat_mode;
7270 * Abort the mapping if the first page is not physically
7271 * aligned to a 2MB page boundary.
7273 ptepa = VM_PAGE_TO_PHYS(p);
7274 if (ptepa & (NBPDR - 1))
7278 * Skip the first page. Abort the mapping if the rest of
7279 * the pages are not physically contiguous or have differing
7280 * memory attributes.
7282 p = TAILQ_NEXT(p, listq);
7283 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7285 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7286 ("pmap_object_init_pt: invalid page %p", p));
7287 if (pa != VM_PAGE_TO_PHYS(p) ||
7288 pat_mode != p->md.pat_mode)
7290 p = TAILQ_NEXT(p, listq);
7294 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7295 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7296 * will not affect the termination of this loop.
7299 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7300 pa < ptepa + size; pa += NBPDR) {
7301 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7304 * The creation of mappings below is only an
7305 * optimization. If a page directory page
7306 * cannot be allocated without blocking,
7307 * continue on to the next mapping rather than
7313 if ((*pde & PG_V) == 0) {
7314 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7315 PG_U | PG_RW | PG_V);
7316 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7317 atomic_add_long(&pmap_pde_mappings, 1);
7319 /* Continue on if the PDE is already valid. */
7321 KASSERT(pdpg->ref_count > 0,
7322 ("pmap_object_init_pt: missing reference "
7323 "to page directory page, va: 0x%lx", addr));
7332 * Clear the wired attribute from the mappings for the specified range of
7333 * addresses in the given pmap. Every valid mapping within that range
7334 * must have the wired attribute set. In contrast, invalid mappings
7335 * cannot have the wired attribute set, so they are ignored.
7337 * The wired attribute of the page table entry is not a hardware
7338 * feature, so there is no need to invalidate any TLB entries.
7339 * Since pmap_demote_pde() for the wired entry must never fail,
7340 * pmap_delayed_invl_start()/finish() calls around the
7341 * function are not needed.
7344 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7346 vm_offset_t va_next;
7347 pml4_entry_t *pml4e;
7350 pt_entry_t *pte, PG_V, PG_G;
7352 PG_V = pmap_valid_bit(pmap);
7353 PG_G = pmap_global_bit(pmap);
7355 for (; sva < eva; sva = va_next) {
7356 pml4e = pmap_pml4e(pmap, sva);
7357 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7358 va_next = (sva + NBPML4) & ~PML4MASK;
7364 va_next = (sva + NBPDP) & ~PDPMASK;
7367 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7368 if ((*pdpe & PG_V) == 0)
7370 if ((*pdpe & PG_PS) != 0) {
7371 KASSERT(va_next <= eva,
7372 ("partial update of non-transparent 1G mapping "
7373 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7374 *pdpe, sva, eva, va_next));
7375 MPASS(pmap != kernel_pmap); /* XXXKIB */
7376 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7377 atomic_clear_long(pdpe, PG_W);
7378 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7382 va_next = (sva + NBPDR) & ~PDRMASK;
7385 pde = pmap_pdpe_to_pde(pdpe, sva);
7386 if ((*pde & PG_V) == 0)
7388 if ((*pde & PG_PS) != 0) {
7389 if ((*pde & PG_W) == 0)
7390 panic("pmap_unwire: pde %#jx is missing PG_W",
7394 * Are we unwiring the entire large page? If not,
7395 * demote the mapping and fall through.
7397 if (sva + NBPDR == va_next && eva >= va_next) {
7398 atomic_clear_long(pde, PG_W);
7399 pmap->pm_stats.wired_count -= NBPDR /
7402 } else if (!pmap_demote_pde(pmap, pde, sva))
7403 panic("pmap_unwire: demotion failed");
7407 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7409 if ((*pte & PG_V) == 0)
7411 if ((*pte & PG_W) == 0)
7412 panic("pmap_unwire: pte %#jx is missing PG_W",
7416 * PG_W must be cleared atomically. Although the pmap
7417 * lock synchronizes access to PG_W, another processor
7418 * could be setting PG_M and/or PG_A concurrently.
7420 atomic_clear_long(pte, PG_W);
7421 pmap->pm_stats.wired_count--;
7428 * Copy the range specified by src_addr/len
7429 * from the source map to the range dst_addr/len
7430 * in the destination map.
7432 * This routine is only advisory and need not do anything.
7435 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7436 vm_offset_t src_addr)
7438 struct rwlock *lock;
7439 pml4_entry_t *pml4e;
7441 pd_entry_t *pde, srcptepaddr;
7442 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7443 vm_offset_t addr, end_addr, va_next;
7444 vm_page_t dst_pdpg, dstmpte, srcmpte;
7446 if (dst_addr != src_addr)
7449 if (dst_pmap->pm_type != src_pmap->pm_type)
7453 * EPT page table entries that require emulation of A/D bits are
7454 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7455 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7456 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7457 * implementations flag an EPT misconfiguration for exec-only
7458 * mappings we skip this function entirely for emulated pmaps.
7460 if (pmap_emulate_ad_bits(dst_pmap))
7463 end_addr = src_addr + len;
7465 if (dst_pmap < src_pmap) {
7466 PMAP_LOCK(dst_pmap);
7467 PMAP_LOCK(src_pmap);
7469 PMAP_LOCK(src_pmap);
7470 PMAP_LOCK(dst_pmap);
7473 PG_A = pmap_accessed_bit(dst_pmap);
7474 PG_M = pmap_modified_bit(dst_pmap);
7475 PG_V = pmap_valid_bit(dst_pmap);
7477 for (addr = src_addr; addr < end_addr; addr = va_next) {
7478 KASSERT(addr < UPT_MIN_ADDRESS,
7479 ("pmap_copy: invalid to pmap_copy page tables"));
7481 pml4e = pmap_pml4e(src_pmap, addr);
7482 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7483 va_next = (addr + NBPML4) & ~PML4MASK;
7489 va_next = (addr + NBPDP) & ~PDPMASK;
7492 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7493 if ((*pdpe & PG_V) == 0)
7495 if ((*pdpe & PG_PS) != 0) {
7496 KASSERT(va_next <= end_addr,
7497 ("partial update of non-transparent 1G mapping "
7498 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7499 *pdpe, addr, end_addr, va_next));
7500 MPASS((addr & PDPMASK) == 0);
7501 MPASS((*pdpe & PG_MANAGED) == 0);
7502 srcptepaddr = *pdpe;
7503 pdpe = pmap_pdpe(dst_pmap, addr);
7505 if (_pmap_allocpte(dst_pmap,
7506 pmap_pml4e_pindex(addr), NULL, addr) ==
7509 pdpe = pmap_pdpe(dst_pmap, addr);
7511 pml4e = pmap_pml4e(dst_pmap, addr);
7512 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7513 dst_pdpg->ref_count++;
7516 ("1G mapping present in dst pmap "
7517 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7518 *pdpe, addr, end_addr, va_next));
7519 *pdpe = srcptepaddr & ~PG_W;
7520 pmap_resident_count_inc(dst_pmap, NBPDP / PAGE_SIZE);
7524 va_next = (addr + NBPDR) & ~PDRMASK;
7528 pde = pmap_pdpe_to_pde(pdpe, addr);
7530 if (srcptepaddr == 0)
7533 if (srcptepaddr & PG_PS) {
7534 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7536 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7539 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7540 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7541 PMAP_ENTER_NORECLAIM, &lock))) {
7542 *pde = srcptepaddr & ~PG_W;
7543 pmap_resident_count_inc(dst_pmap, NBPDR /
7545 atomic_add_long(&pmap_pde_mappings, 1);
7547 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7551 srcptepaddr &= PG_FRAME;
7552 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7553 KASSERT(srcmpte->ref_count > 0,
7554 ("pmap_copy: source page table page is unused"));
7556 if (va_next > end_addr)
7559 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7560 src_pte = &src_pte[pmap_pte_index(addr)];
7562 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7566 * We only virtual copy managed pages.
7568 if ((ptetemp & PG_MANAGED) == 0)
7571 if (dstmpte != NULL) {
7572 KASSERT(dstmpte->pindex ==
7573 pmap_pde_pindex(addr),
7574 ("dstmpte pindex/addr mismatch"));
7575 dstmpte->ref_count++;
7576 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7579 dst_pte = (pt_entry_t *)
7580 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7581 dst_pte = &dst_pte[pmap_pte_index(addr)];
7582 if (*dst_pte == 0 &&
7583 pmap_try_insert_pv_entry(dst_pmap, addr,
7584 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7586 * Clear the wired, modified, and accessed
7587 * (referenced) bits during the copy.
7589 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7590 pmap_resident_count_inc(dst_pmap, 1);
7592 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7595 /* Have we copied all of the valid mappings? */
7596 if (dstmpte->ref_count >= srcmpte->ref_count)
7603 PMAP_UNLOCK(src_pmap);
7604 PMAP_UNLOCK(dst_pmap);
7608 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7612 if (dst_pmap->pm_type != src_pmap->pm_type ||
7613 dst_pmap->pm_type != PT_X86 ||
7614 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7617 if (dst_pmap < src_pmap) {
7618 PMAP_LOCK(dst_pmap);
7619 PMAP_LOCK(src_pmap);
7621 PMAP_LOCK(src_pmap);
7622 PMAP_LOCK(dst_pmap);
7624 error = pmap_pkru_copy(dst_pmap, src_pmap);
7625 /* Clean up partial copy on failure due to no memory. */
7626 if (error == ENOMEM)
7627 pmap_pkru_deassign_all(dst_pmap);
7628 PMAP_UNLOCK(src_pmap);
7629 PMAP_UNLOCK(dst_pmap);
7630 if (error != ENOMEM)
7638 * Zero the specified hardware page.
7641 pmap_zero_page(vm_page_t m)
7643 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7645 pagezero((void *)va);
7649 * Zero an an area within a single hardware page. off and size must not
7650 * cover an area beyond a single hardware page.
7653 pmap_zero_page_area(vm_page_t m, int off, int size)
7655 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7657 if (off == 0 && size == PAGE_SIZE)
7658 pagezero((void *)va);
7660 bzero((char *)va + off, size);
7664 * Copy 1 specified hardware page to another.
7667 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7669 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7670 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7672 pagecopy((void *)src, (void *)dst);
7675 int unmapped_buf_allowed = 1;
7678 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7679 vm_offset_t b_offset, int xfersize)
7683 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7687 while (xfersize > 0) {
7688 a_pg_offset = a_offset & PAGE_MASK;
7689 pages[0] = ma[a_offset >> PAGE_SHIFT];
7690 b_pg_offset = b_offset & PAGE_MASK;
7691 pages[1] = mb[b_offset >> PAGE_SHIFT];
7692 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7693 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7694 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7695 a_cp = (char *)vaddr[0] + a_pg_offset;
7696 b_cp = (char *)vaddr[1] + b_pg_offset;
7697 bcopy(a_cp, b_cp, cnt);
7698 if (__predict_false(mapped))
7699 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7707 * Returns true if the pmap's pv is one of the first
7708 * 16 pvs linked to from this page. This count may
7709 * be changed upwards or downwards in the future; it
7710 * is only necessary that true be returned for a small
7711 * subset of pmaps for proper page aging.
7714 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7716 struct md_page *pvh;
7717 struct rwlock *lock;
7722 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7723 ("pmap_page_exists_quick: page %p is not managed", m));
7725 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7727 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7728 if (PV_PMAP(pv) == pmap) {
7736 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7737 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7738 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7739 if (PV_PMAP(pv) == pmap) {
7753 * pmap_page_wired_mappings:
7755 * Return the number of managed mappings to the given physical page
7759 pmap_page_wired_mappings(vm_page_t m)
7761 struct rwlock *lock;
7762 struct md_page *pvh;
7766 int count, md_gen, pvh_gen;
7768 if ((m->oflags & VPO_UNMANAGED) != 0)
7770 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7774 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7776 if (!PMAP_TRYLOCK(pmap)) {
7777 md_gen = m->md.pv_gen;
7781 if (md_gen != m->md.pv_gen) {
7786 pte = pmap_pte(pmap, pv->pv_va);
7787 if ((*pte & PG_W) != 0)
7791 if ((m->flags & PG_FICTITIOUS) == 0) {
7792 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7793 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7795 if (!PMAP_TRYLOCK(pmap)) {
7796 md_gen = m->md.pv_gen;
7797 pvh_gen = pvh->pv_gen;
7801 if (md_gen != m->md.pv_gen ||
7802 pvh_gen != pvh->pv_gen) {
7807 pte = pmap_pde(pmap, pv->pv_va);
7808 if ((*pte & PG_W) != 0)
7818 * Returns TRUE if the given page is mapped individually or as part of
7819 * a 2mpage. Otherwise, returns FALSE.
7822 pmap_page_is_mapped(vm_page_t m)
7824 struct rwlock *lock;
7827 if ((m->oflags & VPO_UNMANAGED) != 0)
7829 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7831 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7832 ((m->flags & PG_FICTITIOUS) == 0 &&
7833 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7839 * Destroy all managed, non-wired mappings in the given user-space
7840 * pmap. This pmap cannot be active on any processor besides the
7843 * This function cannot be applied to the kernel pmap. Moreover, it
7844 * is not intended for general use. It is only to be used during
7845 * process termination. Consequently, it can be implemented in ways
7846 * that make it faster than pmap_remove(). First, it can more quickly
7847 * destroy mappings by iterating over the pmap's collection of PV
7848 * entries, rather than searching the page table. Second, it doesn't
7849 * have to test and clear the page table entries atomically, because
7850 * no processor is currently accessing the user address space. In
7851 * particular, a page table entry's dirty bit won't change state once
7852 * this function starts.
7854 * Although this function destroys all of the pmap's managed,
7855 * non-wired mappings, it can delay and batch the invalidation of TLB
7856 * entries without calling pmap_delayed_invl_start() and
7857 * pmap_delayed_invl_finish(). Because the pmap is not active on
7858 * any other processor, none of these TLB entries will ever be used
7859 * before their eventual invalidation. Consequently, there is no need
7860 * for either pmap_remove_all() or pmap_remove_write() to wait for
7861 * that eventual TLB invalidation.
7864 pmap_remove_pages(pmap_t pmap)
7867 pt_entry_t *pte, tpte;
7868 pt_entry_t PG_M, PG_RW, PG_V;
7869 struct spglist free;
7870 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7871 vm_page_t m, mpte, mt;
7873 struct md_page *pvh;
7874 struct pv_chunk *pc, *npc;
7875 struct rwlock *lock;
7877 uint64_t inuse, bitmask;
7878 int allfree, field, freed, i, idx;
7879 boolean_t superpage;
7883 * Assert that the given pmap is only active on the current
7884 * CPU. Unfortunately, we cannot block another CPU from
7885 * activating the pmap while this function is executing.
7887 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7890 cpuset_t other_cpus;
7892 other_cpus = all_cpus;
7894 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7895 CPU_AND(&other_cpus, &pmap->pm_active);
7897 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7902 PG_M = pmap_modified_bit(pmap);
7903 PG_V = pmap_valid_bit(pmap);
7904 PG_RW = pmap_rw_bit(pmap);
7906 for (i = 0; i < PMAP_MEMDOM; i++)
7907 TAILQ_INIT(&free_chunks[i]);
7910 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7913 for (field = 0; field < _NPCM; field++) {
7914 inuse = ~pc->pc_map[field] & pc_freemask[field];
7915 while (inuse != 0) {
7917 bitmask = 1UL << bit;
7918 idx = field * 64 + bit;
7919 pv = &pc->pc_pventry[idx];
7922 pte = pmap_pdpe(pmap, pv->pv_va);
7924 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7926 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7929 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7931 pte = &pte[pmap_pte_index(pv->pv_va)];
7935 * Keep track whether 'tpte' is a
7936 * superpage explicitly instead of
7937 * relying on PG_PS being set.
7939 * This is because PG_PS is numerically
7940 * identical to PG_PTE_PAT and thus a
7941 * regular page could be mistaken for
7947 if ((tpte & PG_V) == 0) {
7948 panic("bad pte va %lx pte %lx",
7953 * We cannot remove wired pages from a process' mapping at this time
7961 pa = tpte & PG_PS_FRAME;
7963 pa = tpte & PG_FRAME;
7965 m = PHYS_TO_VM_PAGE(pa);
7966 KASSERT(m->phys_addr == pa,
7967 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7968 m, (uintmax_t)m->phys_addr,
7971 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7972 m < &vm_page_array[vm_page_array_size],
7973 ("pmap_remove_pages: bad tpte %#jx",
7979 * Update the vm_page_t clean/reference bits.
7981 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7983 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7989 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7992 pc->pc_map[field] |= bitmask;
7994 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7995 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7996 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7998 if (TAILQ_EMPTY(&pvh->pv_list)) {
7999 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8000 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
8001 TAILQ_EMPTY(&mt->md.pv_list))
8002 vm_page_aflag_clear(mt, PGA_WRITEABLE);
8004 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
8006 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
8007 ("pmap_remove_pages: pte page not promoted"));
8008 pmap_resident_count_dec(pmap, 1);
8009 KASSERT(mpte->ref_count == NPTEPG,
8010 ("pmap_remove_pages: pte page reference count error"));
8011 mpte->ref_count = 0;
8012 pmap_add_delayed_free_list(mpte, &free, FALSE);
8015 pmap_resident_count_dec(pmap, 1);
8016 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8018 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8019 TAILQ_EMPTY(&m->md.pv_list) &&
8020 (m->flags & PG_FICTITIOUS) == 0) {
8021 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8022 if (TAILQ_EMPTY(&pvh->pv_list))
8023 vm_page_aflag_clear(m, PGA_WRITEABLE);
8026 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8030 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
8031 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
8032 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
8034 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8035 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8040 pmap_invalidate_all(pmap);
8041 pmap_pkru_deassign_all(pmap);
8042 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8044 vm_page_free_pages_toq(&free, true);
8048 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8050 struct rwlock *lock;
8052 struct md_page *pvh;
8053 pt_entry_t *pte, mask;
8054 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8056 int md_gen, pvh_gen;
8060 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8063 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8065 if (!PMAP_TRYLOCK(pmap)) {
8066 md_gen = m->md.pv_gen;
8070 if (md_gen != m->md.pv_gen) {
8075 pte = pmap_pte(pmap, pv->pv_va);
8078 PG_M = pmap_modified_bit(pmap);
8079 PG_RW = pmap_rw_bit(pmap);
8080 mask |= PG_RW | PG_M;
8083 PG_A = pmap_accessed_bit(pmap);
8084 PG_V = pmap_valid_bit(pmap);
8085 mask |= PG_V | PG_A;
8087 rv = (*pte & mask) == mask;
8092 if ((m->flags & PG_FICTITIOUS) == 0) {
8093 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8094 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8096 if (!PMAP_TRYLOCK(pmap)) {
8097 md_gen = m->md.pv_gen;
8098 pvh_gen = pvh->pv_gen;
8102 if (md_gen != m->md.pv_gen ||
8103 pvh_gen != pvh->pv_gen) {
8108 pte = pmap_pde(pmap, pv->pv_va);
8111 PG_M = pmap_modified_bit(pmap);
8112 PG_RW = pmap_rw_bit(pmap);
8113 mask |= PG_RW | PG_M;
8116 PG_A = pmap_accessed_bit(pmap);
8117 PG_V = pmap_valid_bit(pmap);
8118 mask |= PG_V | PG_A;
8120 rv = (*pte & mask) == mask;
8134 * Return whether or not the specified physical page was modified
8135 * in any physical maps.
8138 pmap_is_modified(vm_page_t m)
8141 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8142 ("pmap_is_modified: page %p is not managed", m));
8145 * If the page is not busied then this check is racy.
8147 if (!pmap_page_is_write_mapped(m))
8149 return (pmap_page_test_mappings(m, FALSE, TRUE));
8153 * pmap_is_prefaultable:
8155 * Return whether or not the specified virtual address is eligible
8159 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8162 pt_entry_t *pte, PG_V;
8165 PG_V = pmap_valid_bit(pmap);
8168 pde = pmap_pde(pmap, addr);
8169 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8170 pte = pmap_pde_to_pte(pde, addr);
8171 rv = (*pte & PG_V) == 0;
8178 * pmap_is_referenced:
8180 * Return whether or not the specified physical page was referenced
8181 * in any physical maps.
8184 pmap_is_referenced(vm_page_t m)
8187 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8188 ("pmap_is_referenced: page %p is not managed", m));
8189 return (pmap_page_test_mappings(m, TRUE, FALSE));
8193 * Clear the write and modified bits in each of the given page's mappings.
8196 pmap_remove_write(vm_page_t m)
8198 struct md_page *pvh;
8200 struct rwlock *lock;
8201 pv_entry_t next_pv, pv;
8203 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8205 int pvh_gen, md_gen;
8207 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8208 ("pmap_remove_write: page %p is not managed", m));
8210 vm_page_assert_busied(m);
8211 if (!pmap_page_is_write_mapped(m))
8214 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8215 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8216 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8219 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8221 if (!PMAP_TRYLOCK(pmap)) {
8222 pvh_gen = pvh->pv_gen;
8226 if (pvh_gen != pvh->pv_gen) {
8232 PG_RW = pmap_rw_bit(pmap);
8234 pde = pmap_pde(pmap, va);
8235 if ((*pde & PG_RW) != 0)
8236 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8237 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8238 ("inconsistent pv lock %p %p for page %p",
8239 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8242 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8244 if (!PMAP_TRYLOCK(pmap)) {
8245 pvh_gen = pvh->pv_gen;
8246 md_gen = m->md.pv_gen;
8250 if (pvh_gen != pvh->pv_gen ||
8251 md_gen != m->md.pv_gen) {
8257 PG_M = pmap_modified_bit(pmap);
8258 PG_RW = pmap_rw_bit(pmap);
8259 pde = pmap_pde(pmap, pv->pv_va);
8260 KASSERT((*pde & PG_PS) == 0,
8261 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8263 pte = pmap_pde_to_pte(pde, pv->pv_va);
8266 if (oldpte & PG_RW) {
8267 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8270 if ((oldpte & PG_M) != 0)
8272 pmap_invalidate_page(pmap, pv->pv_va);
8277 vm_page_aflag_clear(m, PGA_WRITEABLE);
8278 pmap_delayed_invl_wait(m);
8281 static __inline boolean_t
8282 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8285 if (!pmap_emulate_ad_bits(pmap))
8288 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8291 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8292 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8293 * if the EPT_PG_WRITE bit is set.
8295 if ((pte & EPT_PG_WRITE) != 0)
8299 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8301 if ((pte & EPT_PG_EXECUTE) == 0 ||
8302 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8309 * pmap_ts_referenced:
8311 * Return a count of reference bits for a page, clearing those bits.
8312 * It is not necessary for every reference bit to be cleared, but it
8313 * is necessary that 0 only be returned when there are truly no
8314 * reference bits set.
8316 * As an optimization, update the page's dirty field if a modified bit is
8317 * found while counting reference bits. This opportunistic update can be
8318 * performed at low cost and can eliminate the need for some future calls
8319 * to pmap_is_modified(). However, since this function stops after
8320 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8321 * dirty pages. Those dirty pages will only be detected by a future call
8322 * to pmap_is_modified().
8324 * A DI block is not needed within this function, because
8325 * invalidations are performed before the PV list lock is
8329 pmap_ts_referenced(vm_page_t m)
8331 struct md_page *pvh;
8334 struct rwlock *lock;
8335 pd_entry_t oldpde, *pde;
8336 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8339 int cleared, md_gen, not_cleared, pvh_gen;
8340 struct spglist free;
8343 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8344 ("pmap_ts_referenced: page %p is not managed", m));
8347 pa = VM_PAGE_TO_PHYS(m);
8348 lock = PHYS_TO_PV_LIST_LOCK(pa);
8349 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8353 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8354 goto small_mappings;
8360 if (!PMAP_TRYLOCK(pmap)) {
8361 pvh_gen = pvh->pv_gen;
8365 if (pvh_gen != pvh->pv_gen) {
8370 PG_A = pmap_accessed_bit(pmap);
8371 PG_M = pmap_modified_bit(pmap);
8372 PG_RW = pmap_rw_bit(pmap);
8374 pde = pmap_pde(pmap, pv->pv_va);
8376 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8378 * Although "oldpde" is mapping a 2MB page, because
8379 * this function is called at a 4KB page granularity,
8380 * we only update the 4KB page under test.
8384 if ((oldpde & PG_A) != 0) {
8386 * Since this reference bit is shared by 512 4KB
8387 * pages, it should not be cleared every time it is
8388 * tested. Apply a simple "hash" function on the
8389 * physical page number, the virtual superpage number,
8390 * and the pmap address to select one 4KB page out of
8391 * the 512 on which testing the reference bit will
8392 * result in clearing that reference bit. This
8393 * function is designed to avoid the selection of the
8394 * same 4KB page for every 2MB page mapping.
8396 * On demotion, a mapping that hasn't been referenced
8397 * is simply destroyed. To avoid the possibility of a
8398 * subsequent page fault on a demoted wired mapping,
8399 * always leave its reference bit set. Moreover,
8400 * since the superpage is wired, the current state of
8401 * its reference bit won't affect page replacement.
8403 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8404 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8405 (oldpde & PG_W) == 0) {
8406 if (safe_to_clear_referenced(pmap, oldpde)) {
8407 atomic_clear_long(pde, PG_A);
8408 pmap_invalidate_page(pmap, pv->pv_va);
8410 } else if (pmap_demote_pde_locked(pmap, pde,
8411 pv->pv_va, &lock)) {
8413 * Remove the mapping to a single page
8414 * so that a subsequent access may
8415 * repromote. Since the underlying
8416 * page table page is fully populated,
8417 * this removal never frees a page
8421 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8423 pte = pmap_pde_to_pte(pde, va);
8424 pmap_remove_pte(pmap, pte, va, *pde,
8426 pmap_invalidate_page(pmap, va);
8432 * The superpage mapping was removed
8433 * entirely and therefore 'pv' is no
8441 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8442 ("inconsistent pv lock %p %p for page %p",
8443 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8448 /* Rotate the PV list if it has more than one entry. */
8449 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8450 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8451 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8454 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8456 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8458 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8465 if (!PMAP_TRYLOCK(pmap)) {
8466 pvh_gen = pvh->pv_gen;
8467 md_gen = m->md.pv_gen;
8471 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8476 PG_A = pmap_accessed_bit(pmap);
8477 PG_M = pmap_modified_bit(pmap);
8478 PG_RW = pmap_rw_bit(pmap);
8479 pde = pmap_pde(pmap, pv->pv_va);
8480 KASSERT((*pde & PG_PS) == 0,
8481 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8483 pte = pmap_pde_to_pte(pde, pv->pv_va);
8484 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8486 if ((*pte & PG_A) != 0) {
8487 if (safe_to_clear_referenced(pmap, *pte)) {
8488 atomic_clear_long(pte, PG_A);
8489 pmap_invalidate_page(pmap, pv->pv_va);
8491 } else if ((*pte & PG_W) == 0) {
8493 * Wired pages cannot be paged out so
8494 * doing accessed bit emulation for
8495 * them is wasted effort. We do the
8496 * hard work for unwired pages only.
8498 pmap_remove_pte(pmap, pte, pv->pv_va,
8499 *pde, &free, &lock);
8500 pmap_invalidate_page(pmap, pv->pv_va);
8505 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8506 ("inconsistent pv lock %p %p for page %p",
8507 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8512 /* Rotate the PV list if it has more than one entry. */
8513 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8514 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8515 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8518 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8519 not_cleared < PMAP_TS_REFERENCED_MAX);
8522 vm_page_free_pages_toq(&free, true);
8523 return (cleared + not_cleared);
8527 * Apply the given advice to the specified range of addresses within the
8528 * given pmap. Depending on the advice, clear the referenced and/or
8529 * modified flags in each mapping and set the mapped page's dirty field.
8532 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8534 struct rwlock *lock;
8535 pml4_entry_t *pml4e;
8537 pd_entry_t oldpde, *pde;
8538 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8539 vm_offset_t va, va_next;
8543 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8547 * A/D bit emulation requires an alternate code path when clearing
8548 * the modified and accessed bits below. Since this function is
8549 * advisory in nature we skip it entirely for pmaps that require
8550 * A/D bit emulation.
8552 if (pmap_emulate_ad_bits(pmap))
8555 PG_A = pmap_accessed_bit(pmap);
8556 PG_G = pmap_global_bit(pmap);
8557 PG_M = pmap_modified_bit(pmap);
8558 PG_V = pmap_valid_bit(pmap);
8559 PG_RW = pmap_rw_bit(pmap);
8561 pmap_delayed_invl_start();
8563 for (; sva < eva; sva = va_next) {
8564 pml4e = pmap_pml4e(pmap, sva);
8565 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8566 va_next = (sva + NBPML4) & ~PML4MASK;
8572 va_next = (sva + NBPDP) & ~PDPMASK;
8575 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8576 if ((*pdpe & PG_V) == 0)
8578 if ((*pdpe & PG_PS) != 0) {
8579 KASSERT(va_next <= eva,
8580 ("partial update of non-transparent 1G mapping "
8581 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8582 *pdpe, sva, eva, va_next));
8586 va_next = (sva + NBPDR) & ~PDRMASK;
8589 pde = pmap_pdpe_to_pde(pdpe, sva);
8591 if ((oldpde & PG_V) == 0)
8593 else if ((oldpde & PG_PS) != 0) {
8594 if ((oldpde & PG_MANAGED) == 0)
8597 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8602 * The large page mapping was destroyed.
8608 * Unless the page mappings are wired, remove the
8609 * mapping to a single page so that a subsequent
8610 * access may repromote. Choosing the last page
8611 * within the address range [sva, min(va_next, eva))
8612 * generally results in more repromotions. Since the
8613 * underlying page table page is fully populated, this
8614 * removal never frees a page table page.
8616 if ((oldpde & PG_W) == 0) {
8622 ("pmap_advise: no address gap"));
8623 pte = pmap_pde_to_pte(pde, va);
8624 KASSERT((*pte & PG_V) != 0,
8625 ("pmap_advise: invalid PTE"));
8626 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8636 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8638 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8640 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8641 if (advice == MADV_DONTNEED) {
8643 * Future calls to pmap_is_modified()
8644 * can be avoided by making the page
8647 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8650 atomic_clear_long(pte, PG_M | PG_A);
8651 } else if ((*pte & PG_A) != 0)
8652 atomic_clear_long(pte, PG_A);
8656 if ((*pte & PG_G) != 0) {
8663 if (va != va_next) {
8664 pmap_invalidate_range(pmap, va, sva);
8669 pmap_invalidate_range(pmap, va, sva);
8672 pmap_invalidate_all(pmap);
8674 pmap_delayed_invl_finish();
8678 * Clear the modify bits on the specified physical page.
8681 pmap_clear_modify(vm_page_t m)
8683 struct md_page *pvh;
8685 pv_entry_t next_pv, pv;
8686 pd_entry_t oldpde, *pde;
8687 pt_entry_t *pte, PG_M, PG_RW;
8688 struct rwlock *lock;
8690 int md_gen, pvh_gen;
8692 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8693 ("pmap_clear_modify: page %p is not managed", m));
8694 vm_page_assert_busied(m);
8696 if (!pmap_page_is_write_mapped(m))
8698 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8699 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8700 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8703 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8705 if (!PMAP_TRYLOCK(pmap)) {
8706 pvh_gen = pvh->pv_gen;
8710 if (pvh_gen != pvh->pv_gen) {
8715 PG_M = pmap_modified_bit(pmap);
8716 PG_RW = pmap_rw_bit(pmap);
8718 pde = pmap_pde(pmap, va);
8720 /* If oldpde has PG_RW set, then it also has PG_M set. */
8721 if ((oldpde & PG_RW) != 0 &&
8722 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8723 (oldpde & PG_W) == 0) {
8725 * Write protect the mapping to a single page so that
8726 * a subsequent write access may repromote.
8728 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8729 pte = pmap_pde_to_pte(pde, va);
8730 atomic_clear_long(pte, PG_M | PG_RW);
8732 pmap_invalidate_page(pmap, va);
8736 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8738 if (!PMAP_TRYLOCK(pmap)) {
8739 md_gen = m->md.pv_gen;
8740 pvh_gen = pvh->pv_gen;
8744 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8749 PG_M = pmap_modified_bit(pmap);
8750 PG_RW = pmap_rw_bit(pmap);
8751 pde = pmap_pde(pmap, pv->pv_va);
8752 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8753 " a 2mpage in page %p's pv list", m));
8754 pte = pmap_pde_to_pte(pde, pv->pv_va);
8755 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8756 atomic_clear_long(pte, PG_M);
8757 pmap_invalidate_page(pmap, pv->pv_va);
8765 * Miscellaneous support routines follow
8768 /* Adjust the properties for a leaf page table entry. */
8769 static __inline void
8770 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8774 opte = *(u_long *)pte;
8776 npte = opte & ~mask;
8778 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8783 * Map a set of physical memory pages into the kernel virtual
8784 * address space. Return a pointer to where it is mapped. This
8785 * routine is intended to be used for mapping device memory,
8789 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8791 struct pmap_preinit_mapping *ppim;
8792 vm_offset_t va, offset;
8796 offset = pa & PAGE_MASK;
8797 size = round_page(offset + size);
8798 pa = trunc_page(pa);
8800 if (!pmap_initialized) {
8802 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8803 ppim = pmap_preinit_mapping + i;
8804 if (ppim->va == 0) {
8808 ppim->va = virtual_avail;
8809 virtual_avail += size;
8815 panic("%s: too many preinit mappings", __func__);
8818 * If we have a preinit mapping, re-use it.
8820 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8821 ppim = pmap_preinit_mapping + i;
8822 if (ppim->pa == pa && ppim->sz == size &&
8823 (ppim->mode == mode ||
8824 (flags & MAPDEV_SETATTR) == 0))
8825 return ((void *)(ppim->va + offset));
8828 * If the specified range of physical addresses fits within
8829 * the direct map window, use the direct map.
8831 if (pa < dmaplimit && pa + size <= dmaplimit) {
8832 va = PHYS_TO_DMAP(pa);
8833 if ((flags & MAPDEV_SETATTR) != 0) {
8834 PMAP_LOCK(kernel_pmap);
8835 i = pmap_change_props_locked(va, size,
8836 PROT_NONE, mode, flags);
8837 PMAP_UNLOCK(kernel_pmap);
8841 return ((void *)(va + offset));
8843 va = kva_alloc(size);
8845 panic("%s: Couldn't allocate KVA", __func__);
8847 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8848 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8849 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8850 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8851 pmap_invalidate_cache_range(va, va + tmpsize);
8852 return ((void *)(va + offset));
8856 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8859 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8864 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8867 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8871 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8874 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8879 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8882 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8883 MAPDEV_FLUSHCACHE));
8887 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8889 struct pmap_preinit_mapping *ppim;
8893 /* If we gave a direct map region in pmap_mapdev, do nothing */
8894 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8896 offset = va & PAGE_MASK;
8897 size = round_page(offset + size);
8898 va = trunc_page(va);
8899 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8900 ppim = pmap_preinit_mapping + i;
8901 if (ppim->va == va && ppim->sz == size) {
8902 if (pmap_initialized)
8908 if (va + size == virtual_avail)
8913 if (pmap_initialized) {
8914 pmap_qremove(va, atop(size));
8920 * Tries to demote a 1GB page mapping.
8923 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8925 pdp_entry_t newpdpe, oldpdpe;
8926 pd_entry_t *firstpde, newpde, *pde;
8927 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8931 PG_A = pmap_accessed_bit(pmap);
8932 PG_M = pmap_modified_bit(pmap);
8933 PG_V = pmap_valid_bit(pmap);
8934 PG_RW = pmap_rw_bit(pmap);
8936 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8938 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8939 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8940 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8941 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8942 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8943 " in pmap %p", va, pmap);
8946 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8947 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8948 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8949 KASSERT((oldpdpe & PG_A) != 0,
8950 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8951 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8952 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8956 * Initialize the page directory page.
8958 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8964 * Demote the mapping.
8969 * Invalidate a stale recursive mapping of the page directory page.
8971 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8973 pmap_pdpe_demotions++;
8974 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8975 " in pmap %p", va, pmap);
8980 * Sets the memory attribute for the specified page.
8983 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8986 m->md.pat_mode = ma;
8989 * If "m" is a normal page, update its direct mapping. This update
8990 * can be relied upon to perform any cache operations that are
8991 * required for data coherence.
8993 if ((m->flags & PG_FICTITIOUS) == 0 &&
8994 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8996 panic("memory attribute change on the direct map failed");
9000 * Changes the specified virtual address range's memory type to that given by
9001 * the parameter "mode". The specified virtual address range must be
9002 * completely contained within either the direct map or the kernel map. If
9003 * the virtual address range is contained within the kernel map, then the
9004 * memory type for each of the corresponding ranges of the direct map is also
9005 * changed. (The corresponding ranges of the direct map are those ranges that
9006 * map the same physical pages as the specified virtual address range.) These
9007 * changes to the direct map are necessary because Intel describes the
9008 * behavior of their processors as "undefined" if two or more mappings to the
9009 * same physical page have different memory types.
9011 * Returns zero if the change completed successfully, and either EINVAL or
9012 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9013 * of the virtual address range was not mapped, and ENOMEM is returned if
9014 * there was insufficient memory available to complete the change. In the
9015 * latter case, the memory type may have been changed on some part of the
9016 * virtual address range or the direct map.
9019 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9023 PMAP_LOCK(kernel_pmap);
9024 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9026 PMAP_UNLOCK(kernel_pmap);
9031 * Changes the specified virtual address range's protections to those
9032 * specified by "prot". Like pmap_change_attr(), protections for aliases
9033 * in the direct map are updated as well. Protections on aliasing mappings may
9034 * be a subset of the requested protections; for example, mappings in the direct
9035 * map are never executable.
9038 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9042 /* Only supported within the kernel map. */
9043 if (va < VM_MIN_KERNEL_ADDRESS)
9046 PMAP_LOCK(kernel_pmap);
9047 error = pmap_change_props_locked(va, size, prot, -1,
9048 MAPDEV_ASSERTVALID);
9049 PMAP_UNLOCK(kernel_pmap);
9054 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9055 int mode, int flags)
9057 vm_offset_t base, offset, tmpva;
9058 vm_paddr_t pa_start, pa_end, pa_end1;
9060 pd_entry_t *pde, pde_bits, pde_mask;
9061 pt_entry_t *pte, pte_bits, pte_mask;
9065 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9066 base = trunc_page(va);
9067 offset = va & PAGE_MASK;
9068 size = round_page(offset + size);
9071 * Only supported on kernel virtual addresses, including the direct
9072 * map but excluding the recursive map.
9074 if (base < DMAP_MIN_ADDRESS)
9078 * Construct our flag sets and masks. "bits" is the subset of
9079 * "mask" that will be set in each modified PTE.
9081 * Mappings in the direct map are never allowed to be executable.
9083 pde_bits = pte_bits = 0;
9084 pde_mask = pte_mask = 0;
9086 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9087 pde_mask |= X86_PG_PDE_CACHE;
9088 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9089 pte_mask |= X86_PG_PTE_CACHE;
9091 if (prot != VM_PROT_NONE) {
9092 if ((prot & VM_PROT_WRITE) != 0) {
9093 pde_bits |= X86_PG_RW;
9094 pte_bits |= X86_PG_RW;
9096 if ((prot & VM_PROT_EXECUTE) == 0 ||
9097 va < VM_MIN_KERNEL_ADDRESS) {
9101 pde_mask |= X86_PG_RW | pg_nx;
9102 pte_mask |= X86_PG_RW | pg_nx;
9106 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9107 * into 4KB pages if required.
9109 for (tmpva = base; tmpva < base + size; ) {
9110 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9111 if (pdpe == NULL || *pdpe == 0) {
9112 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9113 ("%s: addr %#lx is not mapped", __func__, tmpva));
9116 if (*pdpe & PG_PS) {
9118 * If the current 1GB page already has the required
9119 * properties, then we need not demote this page. Just
9120 * increment tmpva to the next 1GB page frame.
9122 if ((*pdpe & pde_mask) == pde_bits) {
9123 tmpva = trunc_1gpage(tmpva) + NBPDP;
9128 * If the current offset aligns with a 1GB page frame
9129 * and there is at least 1GB left within the range, then
9130 * we need not break down this page into 2MB pages.
9132 if ((tmpva & PDPMASK) == 0 &&
9133 tmpva + PDPMASK < base + size) {
9137 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9140 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9142 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9143 ("%s: addr %#lx is not mapped", __func__, tmpva));
9148 * If the current 2MB page already has the required
9149 * properties, then we need not demote this page. Just
9150 * increment tmpva to the next 2MB page frame.
9152 if ((*pde & pde_mask) == pde_bits) {
9153 tmpva = trunc_2mpage(tmpva) + NBPDR;
9158 * If the current offset aligns with a 2MB page frame
9159 * and there is at least 2MB left within the range, then
9160 * we need not break down this page into 4KB pages.
9162 if ((tmpva & PDRMASK) == 0 &&
9163 tmpva + PDRMASK < base + size) {
9167 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9170 pte = pmap_pde_to_pte(pde, tmpva);
9172 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9173 ("%s: addr %#lx is not mapped", __func__, tmpva));
9181 * Ok, all the pages exist, so run through them updating their
9182 * properties if required.
9185 pa_start = pa_end = 0;
9186 for (tmpva = base; tmpva < base + size; ) {
9187 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9188 if (*pdpe & PG_PS) {
9189 if ((*pdpe & pde_mask) != pde_bits) {
9190 pmap_pte_props(pdpe, pde_bits, pde_mask);
9193 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9194 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9195 if (pa_start == pa_end) {
9196 /* Start physical address run. */
9197 pa_start = *pdpe & PG_PS_FRAME;
9198 pa_end = pa_start + NBPDP;
9199 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9202 /* Run ended, update direct map. */
9203 error = pmap_change_props_locked(
9204 PHYS_TO_DMAP(pa_start),
9205 pa_end - pa_start, prot, mode,
9209 /* Start physical address run. */
9210 pa_start = *pdpe & PG_PS_FRAME;
9211 pa_end = pa_start + NBPDP;
9214 tmpva = trunc_1gpage(tmpva) + NBPDP;
9217 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9219 if ((*pde & pde_mask) != pde_bits) {
9220 pmap_pte_props(pde, pde_bits, pde_mask);
9223 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9224 (*pde & PG_PS_FRAME) < dmaplimit) {
9225 if (pa_start == pa_end) {
9226 /* Start physical address run. */
9227 pa_start = *pde & PG_PS_FRAME;
9228 pa_end = pa_start + NBPDR;
9229 } else if (pa_end == (*pde & PG_PS_FRAME))
9232 /* Run ended, update direct map. */
9233 error = pmap_change_props_locked(
9234 PHYS_TO_DMAP(pa_start),
9235 pa_end - pa_start, prot, mode,
9239 /* Start physical address run. */
9240 pa_start = *pde & PG_PS_FRAME;
9241 pa_end = pa_start + NBPDR;
9244 tmpva = trunc_2mpage(tmpva) + NBPDR;
9246 pte = pmap_pde_to_pte(pde, tmpva);
9247 if ((*pte & pte_mask) != pte_bits) {
9248 pmap_pte_props(pte, pte_bits, pte_mask);
9251 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9252 (*pte & PG_FRAME) < dmaplimit) {
9253 if (pa_start == pa_end) {
9254 /* Start physical address run. */
9255 pa_start = *pte & PG_FRAME;
9256 pa_end = pa_start + PAGE_SIZE;
9257 } else if (pa_end == (*pte & PG_FRAME))
9258 pa_end += PAGE_SIZE;
9260 /* Run ended, update direct map. */
9261 error = pmap_change_props_locked(
9262 PHYS_TO_DMAP(pa_start),
9263 pa_end - pa_start, prot, mode,
9267 /* Start physical address run. */
9268 pa_start = *pte & PG_FRAME;
9269 pa_end = pa_start + PAGE_SIZE;
9275 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9276 pa_end1 = MIN(pa_end, dmaplimit);
9277 if (pa_start != pa_end1)
9278 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9279 pa_end1 - pa_start, prot, mode, flags);
9283 * Flush CPU caches if required to make sure any data isn't cached that
9284 * shouldn't be, etc.
9287 pmap_invalidate_range(kernel_pmap, base, tmpva);
9288 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9289 pmap_invalidate_cache_range(base, tmpva);
9295 * Demotes any mapping within the direct map region that covers more than the
9296 * specified range of physical addresses. This range's size must be a power
9297 * of two and its starting address must be a multiple of its size. Since the
9298 * demotion does not change any attributes of the mapping, a TLB invalidation
9299 * is not mandatory. The caller may, however, request a TLB invalidation.
9302 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9311 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9312 KASSERT((base & (len - 1)) == 0,
9313 ("pmap_demote_DMAP: base is not a multiple of len"));
9314 if (len < NBPDP && base < dmaplimit) {
9315 va = PHYS_TO_DMAP(base);
9317 PMAP_LOCK(kernel_pmap);
9318 pdpe = pmap_pdpe(kernel_pmap, va);
9319 if ((*pdpe & X86_PG_V) == 0)
9320 panic("pmap_demote_DMAP: invalid PDPE");
9321 if ((*pdpe & PG_PS) != 0) {
9322 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9323 panic("pmap_demote_DMAP: PDPE failed");
9327 pde = pmap_pdpe_to_pde(pdpe, va);
9328 if ((*pde & X86_PG_V) == 0)
9329 panic("pmap_demote_DMAP: invalid PDE");
9330 if ((*pde & PG_PS) != 0) {
9331 if (!pmap_demote_pde(kernel_pmap, pde, va))
9332 panic("pmap_demote_DMAP: PDE failed");
9336 if (changed && invalidate)
9337 pmap_invalidate_page(kernel_pmap, va);
9338 PMAP_UNLOCK(kernel_pmap);
9343 * Perform the pmap work for mincore(2). If the page is not both referenced and
9344 * modified by this pmap, returns its physical address so that the caller can
9345 * find other mappings.
9348 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9352 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9356 PG_A = pmap_accessed_bit(pmap);
9357 PG_M = pmap_modified_bit(pmap);
9358 PG_V = pmap_valid_bit(pmap);
9359 PG_RW = pmap_rw_bit(pmap);
9365 pdpe = pmap_pdpe(pmap, addr);
9366 if ((*pdpe & PG_V) != 0) {
9367 if ((*pdpe & PG_PS) != 0) {
9369 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9371 val = MINCORE_PSIND(2);
9373 pdep = pmap_pde(pmap, addr);
9374 if (pdep != NULL && (*pdep & PG_V) != 0) {
9375 if ((*pdep & PG_PS) != 0) {
9377 /* Compute the physical address of the 4KB page. */
9378 pa = ((pte & PG_PS_FRAME) | (addr &
9379 PDRMASK)) & PG_FRAME;
9380 val = MINCORE_PSIND(1);
9382 pte = *pmap_pde_to_pte(pdep, addr);
9383 pa = pte & PG_FRAME;
9389 if ((pte & PG_V) != 0) {
9390 val |= MINCORE_INCORE;
9391 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9392 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9393 if ((pte & PG_A) != 0)
9394 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9396 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9397 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9398 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9406 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9408 uint32_t gen, new_gen, pcid_next;
9410 CRITICAL_ASSERT(curthread);
9411 gen = PCPU_GET(pcid_gen);
9412 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9413 return (pti ? 0 : CR3_PCID_SAVE);
9414 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9415 return (CR3_PCID_SAVE);
9416 pcid_next = PCPU_GET(pcid_next);
9417 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9418 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9419 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9420 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9421 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9425 PCPU_SET(pcid_gen, new_gen);
9426 pcid_next = PMAP_PCID_KERN + 1;
9430 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9431 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9432 PCPU_SET(pcid_next, pcid_next + 1);
9437 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9441 cached = pmap_pcid_alloc(pmap, cpuid);
9442 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9443 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9444 pmap->pm_pcids[cpuid].pm_pcid));
9445 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9446 pmap == kernel_pmap,
9447 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9448 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9453 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9456 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9457 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9461 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9464 uint64_t cached, cr3, kcr3, ucr3;
9466 KASSERT((read_rflags() & PSL_I) == 0,
9467 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9469 /* See the comment in pmap_invalidate_page_pcid(). */
9470 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9471 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9472 old_pmap = PCPU_GET(curpmap);
9473 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9474 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9477 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9479 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9480 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9481 PCPU_SET(curpmap, pmap);
9482 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9483 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9486 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9487 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9489 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9490 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9492 PCPU_INC(pm_save_cnt);
9494 pmap_activate_sw_pti_post(td, pmap);
9498 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9501 uint64_t cached, cr3;
9503 KASSERT((read_rflags() & PSL_I) == 0,
9504 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9506 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9508 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9509 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9511 PCPU_SET(curpmap, pmap);
9513 PCPU_INC(pm_save_cnt);
9517 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9518 u_int cpuid __unused)
9521 load_cr3(pmap->pm_cr3);
9522 PCPU_SET(curpmap, pmap);
9526 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9527 u_int cpuid __unused)
9530 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9531 PCPU_SET(kcr3, pmap->pm_cr3);
9532 PCPU_SET(ucr3, pmap->pm_ucr3);
9533 pmap_activate_sw_pti_post(td, pmap);
9536 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9540 if (pmap_pcid_enabled && pti)
9541 return (pmap_activate_sw_pcid_pti);
9542 else if (pmap_pcid_enabled && !pti)
9543 return (pmap_activate_sw_pcid_nopti);
9544 else if (!pmap_pcid_enabled && pti)
9545 return (pmap_activate_sw_nopcid_pti);
9546 else /* if (!pmap_pcid_enabled && !pti) */
9547 return (pmap_activate_sw_nopcid_nopti);
9551 pmap_activate_sw(struct thread *td)
9553 pmap_t oldpmap, pmap;
9556 oldpmap = PCPU_GET(curpmap);
9557 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9558 if (oldpmap == pmap) {
9559 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9563 cpuid = PCPU_GET(cpuid);
9565 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9567 CPU_SET(cpuid, &pmap->pm_active);
9569 pmap_activate_sw_mode(td, pmap, cpuid);
9571 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9573 CPU_CLR(cpuid, &oldpmap->pm_active);
9578 pmap_activate(struct thread *td)
9581 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9582 * invalidate_all IPI, which checks for curpmap ==
9583 * smp_tlb_pmap. The below sequence of operations has a
9584 * window where %CR3 is loaded with the new pmap's PML4
9585 * address, but the curpmap value has not yet been updated.
9586 * This causes the invltlb IPI handler, which is called
9587 * between the updates, to execute as a NOP, which leaves
9588 * stale TLB entries.
9590 * Note that the most common use of pmap_activate_sw(), from
9591 * a context switch, is immune to this race, because
9592 * interrupts are disabled (while the thread lock is owned),
9593 * so the IPI is delayed until after curpmap is updated. Protect
9594 * other callers in a similar way, by disabling interrupts
9595 * around the %cr3 register reload and curpmap assignment.
9598 pmap_activate_sw(td);
9603 pmap_activate_boot(pmap_t pmap)
9609 * kernel_pmap must be never deactivated, and we ensure that
9610 * by never activating it at all.
9612 MPASS(pmap != kernel_pmap);
9614 cpuid = PCPU_GET(cpuid);
9616 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9618 CPU_SET(cpuid, &pmap->pm_active);
9620 PCPU_SET(curpmap, pmap);
9622 kcr3 = pmap->pm_cr3;
9623 if (pmap_pcid_enabled)
9624 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9628 PCPU_SET(kcr3, kcr3);
9629 PCPU_SET(ucr3, PMAP_NO_CR3);
9633 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9638 * Increase the starting virtual address of the given mapping if a
9639 * different alignment might result in more superpage mappings.
9642 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9643 vm_offset_t *addr, vm_size_t size)
9645 vm_offset_t superpage_offset;
9649 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9650 offset += ptoa(object->pg_color);
9651 superpage_offset = offset & PDRMASK;
9652 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9653 (*addr & PDRMASK) == superpage_offset)
9655 if ((*addr & PDRMASK) < superpage_offset)
9656 *addr = (*addr & ~PDRMASK) + superpage_offset;
9658 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9662 static unsigned long num_dirty_emulations;
9663 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9664 &num_dirty_emulations, 0, NULL);
9666 static unsigned long num_accessed_emulations;
9667 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9668 &num_accessed_emulations, 0, NULL);
9670 static unsigned long num_superpage_accessed_emulations;
9671 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9672 &num_superpage_accessed_emulations, 0, NULL);
9674 static unsigned long ad_emulation_superpage_promotions;
9675 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9676 &ad_emulation_superpage_promotions, 0, NULL);
9677 #endif /* INVARIANTS */
9680 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9683 struct rwlock *lock;
9684 #if VM_NRESERVLEVEL > 0
9688 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9690 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9691 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9693 if (!pmap_emulate_ad_bits(pmap))
9696 PG_A = pmap_accessed_bit(pmap);
9697 PG_M = pmap_modified_bit(pmap);
9698 PG_V = pmap_valid_bit(pmap);
9699 PG_RW = pmap_rw_bit(pmap);
9705 pde = pmap_pde(pmap, va);
9706 if (pde == NULL || (*pde & PG_V) == 0)
9709 if ((*pde & PG_PS) != 0) {
9710 if (ftype == VM_PROT_READ) {
9712 atomic_add_long(&num_superpage_accessed_emulations, 1);
9720 pte = pmap_pde_to_pte(pde, va);
9721 if ((*pte & PG_V) == 0)
9724 if (ftype == VM_PROT_WRITE) {
9725 if ((*pte & PG_RW) == 0)
9728 * Set the modified and accessed bits simultaneously.
9730 * Intel EPT PTEs that do software emulation of A/D bits map
9731 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9732 * An EPT misconfiguration is triggered if the PTE is writable
9733 * but not readable (WR=10). This is avoided by setting PG_A
9734 * and PG_M simultaneously.
9736 *pte |= PG_M | PG_A;
9741 #if VM_NRESERVLEVEL > 0
9742 /* try to promote the mapping */
9743 if (va < VM_MAXUSER_ADDRESS)
9744 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9748 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9750 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9751 pmap_ps_enabled(pmap) &&
9752 (m->flags & PG_FICTITIOUS) == 0 &&
9753 vm_reserv_level_iffullpop(m) == 0) {
9754 pmap_promote_pde(pmap, pde, va, &lock);
9756 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9762 if (ftype == VM_PROT_WRITE)
9763 atomic_add_long(&num_dirty_emulations, 1);
9765 atomic_add_long(&num_accessed_emulations, 1);
9767 rv = 0; /* success */
9776 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9781 pt_entry_t *pte, PG_V;
9785 PG_V = pmap_valid_bit(pmap);
9788 pml4 = pmap_pml4e(pmap, va);
9792 if ((*pml4 & PG_V) == 0)
9795 pdp = pmap_pml4e_to_pdpe(pml4, va);
9797 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9800 pde = pmap_pdpe_to_pde(pdp, va);
9802 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9805 pte = pmap_pde_to_pte(pde, va);
9814 * Get the kernel virtual address of a set of physical pages. If there are
9815 * physical addresses not covered by the DMAP perform a transient mapping
9816 * that will be removed when calling pmap_unmap_io_transient.
9818 * \param page The pages the caller wishes to obtain the virtual
9819 * address on the kernel memory map.
9820 * \param vaddr On return contains the kernel virtual memory address
9821 * of the pages passed in the page parameter.
9822 * \param count Number of pages passed in.
9823 * \param can_fault TRUE if the thread using the mapped pages can take
9824 * page faults, FALSE otherwise.
9826 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9827 * finished or FALSE otherwise.
9831 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9832 boolean_t can_fault)
9835 boolean_t needs_mapping;
9837 int cache_bits, error __unused, i;
9840 * Allocate any KVA space that we need, this is done in a separate
9841 * loop to prevent calling vmem_alloc while pinned.
9843 needs_mapping = FALSE;
9844 for (i = 0; i < count; i++) {
9845 paddr = VM_PAGE_TO_PHYS(page[i]);
9846 if (__predict_false(paddr >= dmaplimit)) {
9847 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9848 M_BESTFIT | M_WAITOK, &vaddr[i]);
9849 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9850 needs_mapping = TRUE;
9852 vaddr[i] = PHYS_TO_DMAP(paddr);
9856 /* Exit early if everything is covered by the DMAP */
9861 * NB: The sequence of updating a page table followed by accesses
9862 * to the corresponding pages used in the !DMAP case is subject to
9863 * the situation described in the "AMD64 Architecture Programmer's
9864 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9865 * Coherency Considerations". Therefore, issuing the INVLPG right
9866 * after modifying the PTE bits is crucial.
9870 for (i = 0; i < count; i++) {
9871 paddr = VM_PAGE_TO_PHYS(page[i]);
9872 if (paddr >= dmaplimit) {
9875 * Slow path, since we can get page faults
9876 * while mappings are active don't pin the
9877 * thread to the CPU and instead add a global
9878 * mapping visible to all CPUs.
9880 pmap_qenter(vaddr[i], &page[i], 1);
9882 pte = vtopte(vaddr[i]);
9883 cache_bits = pmap_cache_bits(kernel_pmap,
9884 page[i]->md.pat_mode, 0);
9885 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9892 return (needs_mapping);
9896 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9897 boolean_t can_fault)
9904 for (i = 0; i < count; i++) {
9905 paddr = VM_PAGE_TO_PHYS(page[i]);
9906 if (paddr >= dmaplimit) {
9908 pmap_qremove(vaddr[i], 1);
9909 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9915 pmap_quick_enter_page(vm_page_t m)
9919 paddr = VM_PAGE_TO_PHYS(m);
9920 if (paddr < dmaplimit)
9921 return (PHYS_TO_DMAP(paddr));
9922 mtx_lock_spin(&qframe_mtx);
9923 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9924 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9925 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9930 pmap_quick_remove_page(vm_offset_t addr)
9935 pte_store(vtopte(qframe), 0);
9937 mtx_unlock_spin(&qframe_mtx);
9941 * Pdp pages from the large map are managed differently from either
9942 * kernel or user page table pages. They are permanently allocated at
9943 * initialization time, and their reference count is permanently set to
9944 * zero. The pml4 entries pointing to those pages are copied into
9945 * each allocated pmap.
9947 * In contrast, pd and pt pages are managed like user page table
9948 * pages. They are dynamically allocated, and their reference count
9949 * represents the number of valid entries within the page.
9952 pmap_large_map_getptp_unlocked(void)
9956 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9958 if (m != NULL && (m->flags & PG_ZERO) == 0)
9964 pmap_large_map_getptp(void)
9968 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9969 m = pmap_large_map_getptp_unlocked();
9971 PMAP_UNLOCK(kernel_pmap);
9973 PMAP_LOCK(kernel_pmap);
9974 /* Callers retry. */
9979 static pdp_entry_t *
9980 pmap_large_map_pdpe(vm_offset_t va)
9982 vm_pindex_t pml4_idx;
9985 pml4_idx = pmap_pml4e_index(va);
9986 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9987 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9989 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9990 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
9991 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9992 "LMSPML4I %#jx lm_ents %d",
9993 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9994 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
9995 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9999 pmap_large_map_pde(vm_offset_t va)
10006 pdpe = pmap_large_map_pdpe(va);
10008 m = pmap_large_map_getptp();
10011 mphys = VM_PAGE_TO_PHYS(m);
10012 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10014 MPASS((*pdpe & X86_PG_PS) == 0);
10015 mphys = *pdpe & PG_FRAME;
10017 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10020 static pt_entry_t *
10021 pmap_large_map_pte(vm_offset_t va)
10028 pde = pmap_large_map_pde(va);
10030 m = pmap_large_map_getptp();
10033 mphys = VM_PAGE_TO_PHYS(m);
10034 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10035 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10037 MPASS((*pde & X86_PG_PS) == 0);
10038 mphys = *pde & PG_FRAME;
10040 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10044 pmap_large_map_kextract(vm_offset_t va)
10046 pdp_entry_t *pdpe, pdp;
10047 pd_entry_t *pde, pd;
10048 pt_entry_t *pte, pt;
10050 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10051 ("not largemap range %#lx", (u_long)va));
10052 pdpe = pmap_large_map_pdpe(va);
10054 KASSERT((pdp & X86_PG_V) != 0,
10055 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10056 (u_long)pdpe, pdp));
10057 if ((pdp & X86_PG_PS) != 0) {
10058 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10059 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10060 (u_long)pdpe, pdp));
10061 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10063 pde = pmap_pdpe_to_pde(pdpe, va);
10065 KASSERT((pd & X86_PG_V) != 0,
10066 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10067 if ((pd & X86_PG_PS) != 0)
10068 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10069 pte = pmap_pde_to_pte(pde, va);
10071 KASSERT((pt & X86_PG_V) != 0,
10072 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10073 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10077 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10078 vmem_addr_t *vmem_res)
10082 * Large mappings are all but static. Consequently, there
10083 * is no point in waiting for an earlier allocation to be
10086 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10087 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10091 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10092 vm_memattr_t mattr)
10097 vm_offset_t va, inc;
10098 vmem_addr_t vmem_res;
10102 if (len == 0 || spa + len < spa)
10105 /* See if DMAP can serve. */
10106 if (spa + len <= dmaplimit) {
10107 va = PHYS_TO_DMAP(spa);
10108 *addr = (void *)va;
10109 return (pmap_change_attr(va, len, mattr));
10113 * No, allocate KVA. Fit the address with best possible
10114 * alignment for superpages. Fall back to worse align if
10118 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10119 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10120 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10122 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10124 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10127 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10132 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10133 * in the pagetable to minimize flushing. No need to
10134 * invalidate TLB, since we only update invalid entries.
10136 PMAP_LOCK(kernel_pmap);
10137 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10139 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10140 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10141 pdpe = pmap_large_map_pdpe(va);
10143 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10144 X86_PG_V | X86_PG_A | pg_nx |
10145 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10147 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10148 (va & PDRMASK) == 0) {
10149 pde = pmap_large_map_pde(va);
10151 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10152 X86_PG_V | X86_PG_A | pg_nx |
10153 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10154 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10158 pte = pmap_large_map_pte(va);
10160 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10161 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10163 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10168 PMAP_UNLOCK(kernel_pmap);
10171 *addr = (void *)vmem_res;
10176 pmap_large_unmap(void *svaa, vm_size_t len)
10178 vm_offset_t sva, va;
10180 pdp_entry_t *pdpe, pdp;
10181 pd_entry_t *pde, pd;
10184 struct spglist spgf;
10186 sva = (vm_offset_t)svaa;
10187 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10188 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10192 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10193 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10194 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10195 PMAP_LOCK(kernel_pmap);
10196 for (va = sva; va < sva + len; va += inc) {
10197 pdpe = pmap_large_map_pdpe(va);
10199 KASSERT((pdp & X86_PG_V) != 0,
10200 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10201 (u_long)pdpe, pdp));
10202 if ((pdp & X86_PG_PS) != 0) {
10203 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10204 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10205 (u_long)pdpe, pdp));
10206 KASSERT((va & PDPMASK) == 0,
10207 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10208 (u_long)pdpe, pdp));
10209 KASSERT(va + NBPDP <= sva + len,
10210 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10211 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10212 (u_long)pdpe, pdp, len));
10217 pde = pmap_pdpe_to_pde(pdpe, va);
10219 KASSERT((pd & X86_PG_V) != 0,
10220 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10222 if ((pd & X86_PG_PS) != 0) {
10223 KASSERT((va & PDRMASK) == 0,
10224 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10226 KASSERT(va + NBPDR <= sva + len,
10227 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10228 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10232 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10234 if (m->ref_count == 0) {
10236 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10240 pte = pmap_pde_to_pte(pde, va);
10241 KASSERT((*pte & X86_PG_V) != 0,
10242 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10243 (u_long)pte, *pte));
10246 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10248 if (m->ref_count == 0) {
10250 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10251 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10253 if (m->ref_count == 0) {
10255 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10259 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10260 PMAP_UNLOCK(kernel_pmap);
10261 vm_page_free_pages_toq(&spgf, false);
10262 vmem_free(large_vmem, sva, len);
10266 pmap_large_map_wb_fence_mfence(void)
10273 pmap_large_map_wb_fence_atomic(void)
10276 atomic_thread_fence_seq_cst();
10280 pmap_large_map_wb_fence_nop(void)
10284 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10287 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10288 return (pmap_large_map_wb_fence_mfence);
10289 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10290 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10291 return (pmap_large_map_wb_fence_atomic);
10293 /* clflush is strongly enough ordered */
10294 return (pmap_large_map_wb_fence_nop);
10298 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10301 for (; len > 0; len -= cpu_clflush_line_size,
10302 va += cpu_clflush_line_size)
10307 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10310 for (; len > 0; len -= cpu_clflush_line_size,
10311 va += cpu_clflush_line_size)
10316 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10319 for (; len > 0; len -= cpu_clflush_line_size,
10320 va += cpu_clflush_line_size)
10325 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10329 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10332 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10333 return (pmap_large_map_flush_range_clwb);
10334 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10335 return (pmap_large_map_flush_range_clflushopt);
10336 else if ((cpu_feature & CPUID_CLFSH) != 0)
10337 return (pmap_large_map_flush_range_clflush);
10339 return (pmap_large_map_flush_range_nop);
10343 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10345 volatile u_long *pe;
10351 for (va = sva; va < eva; va += inc) {
10353 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10354 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10356 if ((p & X86_PG_PS) != 0)
10360 pe = (volatile u_long *)pmap_large_map_pde(va);
10362 if ((p & X86_PG_PS) != 0)
10366 pe = (volatile u_long *)pmap_large_map_pte(va);
10370 seen_other = false;
10372 if ((p & X86_PG_AVAIL1) != 0) {
10374 * Spin-wait for the end of a parallel
10381 * If we saw other write-back
10382 * occuring, we cannot rely on PG_M to
10383 * indicate state of the cache. The
10384 * PG_M bit is cleared before the
10385 * flush to avoid ignoring new writes,
10386 * and writes which are relevant for
10387 * us might happen after.
10393 if ((p & X86_PG_M) != 0 || seen_other) {
10394 if (!atomic_fcmpset_long(pe, &p,
10395 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10397 * If we saw PG_M without
10398 * PG_AVAIL1, and then on the
10399 * next attempt we do not
10400 * observe either PG_M or
10401 * PG_AVAIL1, the other
10402 * write-back started after us
10403 * and finished before us. We
10404 * can rely on it doing our
10408 pmap_large_map_flush_range(va, inc);
10409 atomic_clear_long(pe, X86_PG_AVAIL1);
10418 * Write-back cache lines for the given address range.
10420 * Must be called only on the range or sub-range returned from
10421 * pmap_large_map(). Must not be called on the coalesced ranges.
10423 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10424 * instructions support.
10427 pmap_large_map_wb(void *svap, vm_size_t len)
10429 vm_offset_t eva, sva;
10431 sva = (vm_offset_t)svap;
10433 pmap_large_map_wb_fence();
10434 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10435 pmap_large_map_flush_range(sva, len);
10437 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10438 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10439 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10440 pmap_large_map_wb_large(sva, eva);
10442 pmap_large_map_wb_fence();
10446 pmap_pti_alloc_page(void)
10450 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10451 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10452 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10457 pmap_pti_free_page(vm_page_t m)
10460 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10461 if (!vm_page_unwire_noq(m))
10463 vm_page_free_zero(m);
10468 pmap_pti_init(void)
10477 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10478 VM_OBJECT_WLOCK(pti_obj);
10479 pml4_pg = pmap_pti_alloc_page();
10480 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10481 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10482 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10483 pdpe = pmap_pti_pdpe(va);
10484 pmap_pti_wire_pte(pdpe);
10486 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10487 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10488 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10489 sizeof(struct gate_descriptor) * NIDT, false);
10491 /* Doublefault stack IST 1 */
10492 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10493 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10494 /* NMI stack IST 2 */
10495 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10496 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10497 /* MC# stack IST 3 */
10498 va = __pcpu[i].pc_common_tss.tss_ist3 +
10499 sizeof(struct nmi_pcpu);
10500 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10501 /* DB# stack IST 4 */
10502 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10503 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10505 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10506 (vm_offset_t)etext, true);
10507 pti_finalized = true;
10508 VM_OBJECT_WUNLOCK(pti_obj);
10510 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10512 static pdp_entry_t *
10513 pmap_pti_pdpe(vm_offset_t va)
10515 pml4_entry_t *pml4e;
10518 vm_pindex_t pml4_idx;
10521 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10523 pml4_idx = pmap_pml4e_index(va);
10524 pml4e = &pti_pml4[pml4_idx];
10528 panic("pml4 alloc after finalization\n");
10529 m = pmap_pti_alloc_page();
10531 pmap_pti_free_page(m);
10532 mphys = *pml4e & ~PAGE_MASK;
10534 mphys = VM_PAGE_TO_PHYS(m);
10535 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10538 mphys = *pml4e & ~PAGE_MASK;
10540 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10545 pmap_pti_wire_pte(void *pte)
10549 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10550 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10555 pmap_pti_unwire_pde(void *pde, bool only_ref)
10559 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10560 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10561 MPASS(m->ref_count > 0);
10562 MPASS(only_ref || m->ref_count > 1);
10563 pmap_pti_free_page(m);
10567 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10572 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10573 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10574 MPASS(m->ref_count > 0);
10575 if (pmap_pti_free_page(m)) {
10576 pde = pmap_pti_pde(va);
10577 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10579 pmap_pti_unwire_pde(pde, false);
10583 static pd_entry_t *
10584 pmap_pti_pde(vm_offset_t va)
10589 vm_pindex_t pd_idx;
10592 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10594 pdpe = pmap_pti_pdpe(va);
10596 m = pmap_pti_alloc_page();
10598 pmap_pti_free_page(m);
10599 MPASS((*pdpe & X86_PG_PS) == 0);
10600 mphys = *pdpe & ~PAGE_MASK;
10602 mphys = VM_PAGE_TO_PHYS(m);
10603 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10606 MPASS((*pdpe & X86_PG_PS) == 0);
10607 mphys = *pdpe & ~PAGE_MASK;
10610 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10611 pd_idx = pmap_pde_index(va);
10616 static pt_entry_t *
10617 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10624 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10626 pde = pmap_pti_pde(va);
10627 if (unwire_pde != NULL) {
10628 *unwire_pde = true;
10629 pmap_pti_wire_pte(pde);
10632 m = pmap_pti_alloc_page();
10634 pmap_pti_free_page(m);
10635 MPASS((*pde & X86_PG_PS) == 0);
10636 mphys = *pde & ~(PAGE_MASK | pg_nx);
10638 mphys = VM_PAGE_TO_PHYS(m);
10639 *pde = mphys | X86_PG_RW | X86_PG_V;
10640 if (unwire_pde != NULL)
10641 *unwire_pde = false;
10644 MPASS((*pde & X86_PG_PS) == 0);
10645 mphys = *pde & ~(PAGE_MASK | pg_nx);
10648 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10649 pte += pmap_pte_index(va);
10655 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10659 pt_entry_t *pte, ptev;
10662 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10664 sva = trunc_page(sva);
10665 MPASS(sva > VM_MAXUSER_ADDRESS);
10666 eva = round_page(eva);
10668 for (; sva < eva; sva += PAGE_SIZE) {
10669 pte = pmap_pti_pte(sva, &unwire_pde);
10670 pa = pmap_kextract(sva);
10671 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10672 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10673 VM_MEMATTR_DEFAULT, FALSE);
10675 pte_store(pte, ptev);
10676 pmap_pti_wire_pte(pte);
10678 KASSERT(!pti_finalized,
10679 ("pti overlap after fin %#lx %#lx %#lx",
10681 KASSERT(*pte == ptev,
10682 ("pti non-identical pte after fin %#lx %#lx %#lx",
10686 pde = pmap_pti_pde(sva);
10687 pmap_pti_unwire_pde(pde, true);
10693 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10698 VM_OBJECT_WLOCK(pti_obj);
10699 pmap_pti_add_kva_locked(sva, eva, exec);
10700 VM_OBJECT_WUNLOCK(pti_obj);
10704 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10711 sva = rounddown2(sva, PAGE_SIZE);
10712 MPASS(sva > VM_MAXUSER_ADDRESS);
10713 eva = roundup2(eva, PAGE_SIZE);
10715 VM_OBJECT_WLOCK(pti_obj);
10716 for (va = sva; va < eva; va += PAGE_SIZE) {
10717 pte = pmap_pti_pte(va, NULL);
10718 KASSERT((*pte & X86_PG_V) != 0,
10719 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10720 (u_long)pte, *pte));
10722 pmap_pti_unwire_pte(pte, va);
10724 pmap_invalidate_range(kernel_pmap, sva, eva);
10725 VM_OBJECT_WUNLOCK(pti_obj);
10729 pkru_dup_range(void *ctx __unused, void *data)
10731 struct pmap_pkru_range *node, *new_node;
10733 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10734 if (new_node == NULL)
10737 memcpy(new_node, node, sizeof(*node));
10742 pkru_free_range(void *ctx __unused, void *node)
10745 uma_zfree(pmap_pkru_ranges_zone, node);
10749 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10752 struct pmap_pkru_range *ppr;
10755 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10756 MPASS(pmap->pm_type == PT_X86);
10757 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10758 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10759 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10761 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10764 ppr->pkru_keyidx = keyidx;
10765 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10766 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10768 uma_zfree(pmap_pkru_ranges_zone, ppr);
10773 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10776 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10777 MPASS(pmap->pm_type == PT_X86);
10778 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10779 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10783 pmap_pkru_deassign_all(pmap_t pmap)
10786 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10787 if (pmap->pm_type == PT_X86 &&
10788 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10789 rangeset_remove_all(&pmap->pm_pkru);
10793 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10795 struct pmap_pkru_range *ppr, *prev_ppr;
10798 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10799 if (pmap->pm_type != PT_X86 ||
10800 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10801 sva >= VM_MAXUSER_ADDRESS)
10803 MPASS(eva <= VM_MAXUSER_ADDRESS);
10804 for (va = sva; va < eva; prev_ppr = ppr) {
10805 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10808 else if ((ppr == NULL) ^ (prev_ppr == NULL))
10814 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10816 va = ppr->pkru_rs_el.re_end;
10822 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10824 struct pmap_pkru_range *ppr;
10826 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10827 if (pmap->pm_type != PT_X86 ||
10828 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10829 va >= VM_MAXUSER_ADDRESS)
10831 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10833 return (X86_PG_PKU(ppr->pkru_keyidx));
10838 pred_pkru_on_remove(void *ctx __unused, void *r)
10840 struct pmap_pkru_range *ppr;
10843 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10847 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10850 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10851 if (pmap->pm_type == PT_X86 &&
10852 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10853 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10854 pred_pkru_on_remove);
10859 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10862 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10863 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10864 MPASS(dst_pmap->pm_type == PT_X86);
10865 MPASS(src_pmap->pm_type == PT_X86);
10866 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10867 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10869 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10873 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10876 pml4_entry_t *pml4e;
10878 pd_entry_t newpde, ptpaddr, *pde;
10879 pt_entry_t newpte, *ptep, pte;
10880 vm_offset_t va, va_next;
10883 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10884 MPASS(pmap->pm_type == PT_X86);
10885 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10887 for (changed = false, va = sva; va < eva; va = va_next) {
10888 pml4e = pmap_pml4e(pmap, va);
10889 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
10890 va_next = (va + NBPML4) & ~PML4MASK;
10896 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10897 if ((*pdpe & X86_PG_V) == 0) {
10898 va_next = (va + NBPDP) & ~PDPMASK;
10904 va_next = (va + NBPDR) & ~PDRMASK;
10908 pde = pmap_pdpe_to_pde(pdpe, va);
10913 MPASS((ptpaddr & X86_PG_V) != 0);
10914 if ((ptpaddr & PG_PS) != 0) {
10915 if (va + NBPDR == va_next && eva >= va_next) {
10916 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10917 X86_PG_PKU(keyidx);
10918 if (newpde != ptpaddr) {
10923 } else if (!pmap_demote_pde(pmap, pde, va)) {
10931 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10932 ptep++, va += PAGE_SIZE) {
10934 if ((pte & X86_PG_V) == 0)
10936 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10937 if (newpte != pte) {
10944 pmap_invalidate_range(pmap, sva, eva);
10948 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10949 u_int keyidx, int flags)
10952 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10953 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10955 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10957 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10963 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10968 sva = trunc_page(sva);
10969 eva = round_page(eva);
10970 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10975 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10977 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10979 if (error != ENOMEM)
10987 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10991 sva = trunc_page(sva);
10992 eva = round_page(eva);
10993 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10998 error = pmap_pkru_deassign(pmap, sva, eva);
11000 pmap_pkru_update_range(pmap, sva, eva, 0);
11002 if (error != ENOMEM)
11010 * Track a range of the kernel's virtual address space that is contiguous
11011 * in various mapping attributes.
11013 struct pmap_kernel_map_range {
11022 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11028 if (eva <= range->sva)
11031 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11032 for (i = 0; i < PAT_INDEX_SIZE; i++)
11033 if (pat_index[i] == pat_idx)
11037 case PAT_WRITE_BACK:
11040 case PAT_WRITE_THROUGH:
11043 case PAT_UNCACHEABLE:
11049 case PAT_WRITE_PROTECTED:
11052 case PAT_WRITE_COMBINING:
11056 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11057 __func__, pat_idx, range->sva, eva);
11062 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11064 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11065 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11066 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11067 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11068 mode, range->pdpes, range->pdes, range->ptes);
11070 /* Reset to sentinel value. */
11071 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11072 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11073 NPDEPG - 1, NPTEPG - 1);
11077 * Determine whether the attributes specified by a page table entry match those
11078 * being tracked by the current range. This is not quite as simple as a direct
11079 * flag comparison since some PAT modes have multiple representations.
11082 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11084 pt_entry_t diff, mask;
11086 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11087 diff = (range->attrs ^ attrs) & mask;
11090 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11091 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11092 pmap_pat_index(kernel_pmap, attrs, true))
11098 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11102 memset(range, 0, sizeof(*range));
11104 range->attrs = attrs;
11108 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11109 * those of the current run, dump the address range and its attributes, and
11113 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11114 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11119 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11121 attrs |= pdpe & pg_nx;
11122 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11123 if ((pdpe & PG_PS) != 0) {
11124 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11125 } else if (pde != 0) {
11126 attrs |= pde & pg_nx;
11127 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11129 if ((pde & PG_PS) != 0) {
11130 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11131 } else if (pte != 0) {
11132 attrs |= pte & pg_nx;
11133 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11134 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11136 /* Canonicalize by always using the PDE PAT bit. */
11137 if ((attrs & X86_PG_PTE_PAT) != 0)
11138 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11141 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11142 sysctl_kmaps_dump(sb, range, va);
11143 sysctl_kmaps_reinit(range, va, attrs);
11148 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11150 struct pmap_kernel_map_range range;
11151 struct sbuf sbuf, *sb;
11152 pml4_entry_t pml4e;
11153 pdp_entry_t *pdp, pdpe;
11154 pd_entry_t *pd, pde;
11155 pt_entry_t *pt, pte;
11158 int error, i, j, k, l;
11160 error = sysctl_wire_old_buffer(req, 0);
11164 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11166 /* Sentinel value. */
11167 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11168 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11169 NPDEPG - 1, NPTEPG - 1);
11172 * Iterate over the kernel page tables without holding the kernel pmap
11173 * lock. Outside of the large map, kernel page table pages are never
11174 * freed, so at worst we will observe inconsistencies in the output.
11175 * Within the large map, ensure that PDP and PD page addresses are
11176 * valid before descending.
11178 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11181 sbuf_printf(sb, "\nRecursive map:\n");
11184 sbuf_printf(sb, "\nDirect map:\n");
11187 sbuf_printf(sb, "\nKernel map:\n");
11190 sbuf_printf(sb, "\nLarge map:\n");
11194 /* Convert to canonical form. */
11195 if (sva == 1ul << 47)
11199 pml4e = kernel_pml4[i];
11200 if ((pml4e & X86_PG_V) == 0) {
11201 sva = rounddown2(sva, NBPML4);
11202 sysctl_kmaps_dump(sb, &range, sva);
11206 pa = pml4e & PG_FRAME;
11207 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11209 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11211 if ((pdpe & X86_PG_V) == 0) {
11212 sva = rounddown2(sva, NBPDP);
11213 sysctl_kmaps_dump(sb, &range, sva);
11217 pa = pdpe & PG_FRAME;
11218 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11219 vm_phys_paddr_to_vm_page(pa) == NULL)
11221 if ((pdpe & PG_PS) != 0) {
11222 sva = rounddown2(sva, NBPDP);
11223 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11229 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11231 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11233 if ((pde & X86_PG_V) == 0) {
11234 sva = rounddown2(sva, NBPDR);
11235 sysctl_kmaps_dump(sb, &range, sva);
11239 pa = pde & PG_FRAME;
11240 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11241 vm_phys_paddr_to_vm_page(pa) == NULL)
11243 if ((pde & PG_PS) != 0) {
11244 sva = rounddown2(sva, NBPDR);
11245 sysctl_kmaps_check(sb, &range, sva,
11246 pml4e, pdpe, pde, 0);
11251 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11253 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11254 sva += PAGE_SIZE) {
11256 if ((pte & X86_PG_V) == 0) {
11257 sysctl_kmaps_dump(sb, &range,
11261 sysctl_kmaps_check(sb, &range, sva,
11262 pml4e, pdpe, pde, pte);
11269 error = sbuf_finish(sb);
11273 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11274 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
11275 NULL, 0, sysctl_kmaps, "A",
11276 "Dump kernel address layout");
11279 DB_SHOW_COMMAND(pte, pmap_print_pte)
11282 pml5_entry_t *pml5;
11283 pml4_entry_t *pml4;
11286 pt_entry_t *pte, PG_V;
11290 db_printf("show pte addr\n");
11293 va = (vm_offset_t)addr;
11295 if (kdb_thread != NULL)
11296 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11298 pmap = PCPU_GET(curpmap);
11300 PG_V = pmap_valid_bit(pmap);
11301 db_printf("VA 0x%016lx", va);
11303 if (pmap_is_la57(pmap)) {
11304 pml5 = pmap_pml5e(pmap, va);
11305 db_printf(" pml5e 0x%016lx", *pml5);
11306 if ((*pml5 & PG_V) == 0) {
11310 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11312 pml4 = pmap_pml4e(pmap, va);
11314 db_printf(" pml4e 0x%016lx", *pml4);
11315 if ((*pml4 & PG_V) == 0) {
11319 pdp = pmap_pml4e_to_pdpe(pml4, va);
11320 db_printf(" pdpe 0x%016lx", *pdp);
11321 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11325 pde = pmap_pdpe_to_pde(pdp, va);
11326 db_printf(" pde 0x%016lx", *pde);
11327 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11331 pte = pmap_pde_to_pte(pde, va);
11332 db_printf(" pte 0x%016lx\n", *pte);
11335 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11340 a = (vm_paddr_t)addr;
11341 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11343 db_printf("show phys2dmap addr\n");
11348 ptpages_show_page(int level, int idx, vm_page_t pg)
11350 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11351 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11355 ptpages_show_complain(int level, int idx, uint64_t pte)
11357 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11361 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11363 vm_page_t pg3, pg2, pg1;
11364 pml4_entry_t *pml4;
11369 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11370 for (i4 = 0; i4 < num_entries; i4++) {
11371 if ((pml4[i4] & PG_V) == 0)
11373 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11375 ptpages_show_complain(3, i4, pml4[i4]);
11378 ptpages_show_page(3, i4, pg3);
11379 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11380 for (i3 = 0; i3 < NPDPEPG; i3++) {
11381 if ((pdp[i3] & PG_V) == 0)
11383 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11385 ptpages_show_complain(2, i3, pdp[i3]);
11388 ptpages_show_page(2, i3, pg2);
11389 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11390 for (i2 = 0; i2 < NPDEPG; i2++) {
11391 if ((pd[i2] & PG_V) == 0)
11393 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11395 ptpages_show_complain(1, i2, pd[i2]);
11398 ptpages_show_page(1, i2, pg1);
11404 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11408 pml5_entry_t *pml5;
11413 pmap = (pmap_t)addr;
11415 pmap = PCPU_GET(curpmap);
11417 PG_V = pmap_valid_bit(pmap);
11419 if (pmap_is_la57(pmap)) {
11420 pml5 = pmap->pm_pmltop;
11421 for (i5 = 0; i5 < NUPML5E; i5++) {
11422 if ((pml5[i5] & PG_V) == 0)
11424 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11426 ptpages_show_complain(4, i5, pml5[i5]);
11429 ptpages_show_page(4, i5, pg);
11430 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11433 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11434 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);