sys/ia64/ia64/exception.S

   1 /*-
   2  * Copyright (c) 2003,2004 Marcel Moolenaar
   3  * Copyright (c) 2000 Doug Rabson
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <machine/asm.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_xtrace.h"
  32
  33 #include <machine/pte.h>
  34 #include <assym.s>
  35
  36 /*
  37  * Nested TLB restart tokens. These are used by the
  38  * nested TLB handler for jumping back to the code
  39  * where the nested TLB was caused.
  40  */
  41 #define NTLBRT_SAVE     0x12c12c
  42 #define NTLBRT_RESTORE  0x12c12d
  43
  44 /*
  45  * ar.k7 = kernel memory stack
  46  * ar.k6 = kernel register stack
  47  * ar.k5 = EPC gateway page
  48  * ar.k4 = PCPU data
  49  */
  50
  51 #ifdef EXCEPTION_TRACING
  52
  53         .data
  54         .global xtrace, xhead
  55 xtrace: .space  1024*5*8
  56 xhead:  data8   xtrace
  57
  58 #define XTRACE(offset)                          \
  59 {       .mmi ;                                  \
  60         mov     r24=ar.itc ;                    \
  61         mov     r25=cr.iip ;                    \
  62         mov     r27=offset ;                    \
  63 } ;                                             \
  64 {       .mlx ;                                  \
  65         mov     r28=cr.ifa ;                    \
  66         movl    r29=xhead ;;                    \
  67 } ;                                             \
  68 {       .mmi ;                                  \
  69         ld8     r29=[r29] ;;                    \
  70         st8     [r29]=r24,8 ;                   \
  71         nop     0 ;;                            \
  72 } ;                                             \
  73 {       .mmi ;                                  \
  74         st8     [r29]=r27,8 ;;                  \
  75         mov     r24=cr.isr ;                    \
  76         add     r27=8,r29 ;;                    \
  77 } ;                                             \
  78 {       .mmi ;                                  \
  79         st8     [r29]=r25,16 ;;                 \
  80         st8     [r27]=r28,16 ;                  \
  81         mov     r25=pr ;;                       \
  82 } ;                                             \
  83 {       .mlx ;                                  \
  84         st8     [r29]=r24 ;                     \
  85         movl    r28=xhead ;;                    \
  86 } ;                                             \
  87 {       .mii ;                                  \
  88         cmp.eq  p15,p0=r27,r28 ;                \
  89         addl    r29=1024*5*8,r0 ;;              \
  90 (p15)   sub     r27=r28,r29 ;;                  \
  91 } ;                                             \
  92 {       .mmi ;                                  \
  93         st8     [r28]=r27 ;                     \
  94         nop     0 ;                             \
  95         mov     pr=r25,0x1ffff ;;               \
  96 }
  97
  98 #else
  99
 100 #define XTRACE(offset)
 101
 102 #endif
 103
 104         .text
 105
 106 /*
 107  * exception_save: save interrupted state
 108  *
 109  * Arguments:
 110  *      r16     address of bundle that contains the branch. The
 111  *              return address will be the next bundle.
 112  *      r17     the value to save as ifa in the trapframe. This
 113  *              normally is cr.ifa, but some interruptions set
 114  *              set cr.iim and not cr.ifa.
 115  *
 116  * Returns:
 117  *      p15     interrupted from user stack
 118  *      p14     interrupted from kernel stack
 119  *      p13     interrupted from user backing store
 120  *      p12     interrupted from kernel backing store
 121  *      p11     interrupts were enabled
 122  *      p10     interrupts were disabled
 123  */
 124 ENTRY_NOPROFILE(exception_save, 0)
 125 {       .mii
 126         mov             r20=ar.unat
 127         extr.u          r31=sp,61,3
 128         mov             r18=pr
 129         ;;
 130 }
 131 {       .mmi
 132         cmp.le          p14,p15=5,r31
 133         ;;
 134 (p15)   mov             r23=ar.k7               // kernel memory stack
 135 (p14)   mov             r23=sp
 136         ;;
 137 }
 138 {       .mii
 139         mov             r21=ar.rsc
 140         add             r30=-SIZEOF_TRAPFRAME,r23
 141         ;;
 142         dep             r30=0,r30,0,10
 143         ;;
 144 }
 145 {       .mmi
 146         mov             ar.rsc=0
 147         sub             r19=r23,r30
 148         add             r31=8,r30
 149         ;;
 150 }
 151 {       .mmi
 152         mov             r22=cr.iip
 153         nop             0
 154         addl            r29=NTLBRT_SAVE,r0      // 22-bit restart token.
 155         ;;
 156 }
 157
 158         /*
 159          * We have a 1KB aligned trapframe, pointed to by sp. If we write
 160          * to the trapframe, we may trigger a data nested TLB fault. By
 161          * aligning the trapframe on a 1KB boundary, we guarantee that if
 162          * we get a data nested TLB fault, it will be on the very first
 163          * write. Since the data nested TLB fault does not preserve any
 164          * state, we have to be careful what we clobber. Consequently, we
 165          * have to be careful what we use here. Below a list of registers
 166          * that are currently alive:
 167          *      r16,r17=arguments
 168          *      r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS
 169          *      r29=restart point
 170          *      r30,r31=trapframe pointers
 171          *      p14,p15=memory stack switch
 172          */
 173
 174         /* PTC.G enter non-exclusive */
 175         mov     r24 = ar.ccv
 176         movl    r25 = pmap_ptc_g_sem
 177         ;;
 178 .ptc_g_0:
 179         ld8.acq r26 = [r25]
 180         ;;
 181         tbit.nz p12, p0 = r26, 63
 182 (p12)   br.cond.spnt.few .ptc_g_0
 183         ;;
 184         mov     ar.ccv = r26
 185         adds    r27 = 1, r26
 186         ;;
 187         cmpxchg8.rel    r27 = [r25], r27, ar.ccv
 188         ;;
 189         cmp.ne  p12, p0 = r26, r27
 190 (p12)   br.cond.spnt.few .ptc_g_0
 191         ;;
 192         mov     ar.ccv = r24
 193
 194 exception_save_restart:
 195 {       .mmi
 196         st8             [r30]=r19,16            // length
 197         st8             [r31]=r0,16             // flags
 198         add             r19=16,r19
 199         ;;
 200 }
 201 {       .mmi
 202         st8.spill       [r30]=sp,16             // sp
 203         st8             [r31]=r20,16            // unat
 204         sub             sp=r23,r19
 205         ;;
 206 }
 207 {       .mmi
 208         mov             r19=ar.rnat
 209         mov             r20=ar.bspstore
 210         mov             r23=rp
 211         ;;
 212 }
 213         // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp
 214 {       .mmi
 215         st8             [r30]=r23,16            // rp
 216         st8             [r31]=r18,16            // pr
 217         mov             r24=ar.pfs
 218         ;;
 219 }
 220 {       .mmb
 221         st8             [r30]=r24,16            // pfs
 222         st8             [r31]=r20,16            // bspstore
 223         cover
 224         ;;
 225 }
 226 {       .mmi
 227         mov             r18=ar.fpsr
 228         mov             r23=cr.ipsr
 229         extr.u          r24=r20,61,3
 230         ;;
 231 }
 232         // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr
 233 {       .mmi
 234         st8             [r30]=r19,16            // rnat
 235         st8             [r31]=r0,16             // __spare
 236         cmp.le          p12,p13=5,r24
 237         ;;
 238 }
 239 {       .mmi
 240         st8.spill       [r30]=r13,16            // tp
 241         st8             [r31]=r21,16            // rsc
 242         tbit.nz         p11,p10=r23,14          // p11=interrupts enabled
 243         ;;
 244 }
 245 {       .mmi
 246 (p13)   mov             r21=ar.k6               // kernel register stack
 247         ;;
 248         st8             [r30]=r18,16            // fpsr
 249 (p13)   dep             r20=r20,r21,0,9         // align dirty registers
 250         ;;
 251 }
 252         // r19=rnat, r20=bspstore, r22=iip, r23=ipsr
 253 {       .mmi
 254         st8             [r31]=r23,16            // psr
 255 (p13)   mov             ar.bspstore=r20
 256         nop             0
 257         ;;
 258 }
 259 {       .mmi
 260 (p13)   mov             ar.rnat=r19
 261         mov             r18=ar.bsp
 262         nop             0
 263         ;;
 264 }
 265 {       .mmi
 266         mov             r19=cr.ifs
 267         st8.spill       [r30]=gp,16             // gp
 268         sub             r18=r18,r20
 269         ;;
 270 }
 271         // r19=ifs, r22=iip
 272 {       .mmi
 273         st8             [r31]=r18,16            // ndirty
 274         st8             [r30]=r19,16            // cfm
 275         nop             0
 276         ;;
 277 }
 278 {       .mmi
 279         mov             r18=cr.isr
 280         st8             [r31]=r22,16            // iip
 281         add             r29=16,r30
 282         ;;
 283 }
 284 {       .mmi
 285         st8             [r30]=r17,24            // ifa
 286         st8             [r31]=r18,24            // isr
 287         nop             0
 288         ;;
 289 }
 290 {       .mmi
 291         .mem.offset     0,0
 292         st8.spill       [r30]=r2,16             // r2
 293         .mem.offset     8,0
 294         st8.spill       [r31]=r3,16             // r3
 295         add             r2=9*8,r29
 296         ;;
 297 }
 298 {       .mmi
 299         .mem.offset     0,0
 300         st8.spill       [r30]=r8,16             // r8
 301         .mem.offset     8,0
 302         st8.spill       [r31]=r9,16             // r9
 303         add             r3=8,r2
 304         ;;
 305 }
 306 {       .mmi
 307         .mem.offset     0,0
 308         st8.spill       [r30]=r10,16            // r10
 309         .mem.offset     8,0
 310         st8.spill       [r31]=r11,16            // r11
 311         add             r8=16,r16
 312         ;;
 313 }
 314 {       .mmi
 315         .mem.offset     0,0
 316         st8.spill       [r30]=r14               // r14
 317         .mem.offset     8,0
 318         st8.spill       [r31]=r15               // r15
 319         mov             r9=r29
 320 }
 321 {       .mmb
 322         mov             r10=ar.csd
 323         mov             r11=ar.ssd
 324         bsw.1
 325         ;;
 326 }
 327 {       .mmi
 328         .mem.offset     0,0
 329         st8.spill       [r2]=r16,16             // r16
 330         .mem.offset     8,0
 331         st8.spill       [r3]=r17,16             // r17
 332         mov             r14=b6
 333         ;;
 334 }
 335 {       .mmi
 336         .mem.offset     0,0
 337         st8.spill       [r2]=r18,16             // r18
 338         .mem.offset     8,0
 339         st8.spill       [r3]=r19,16             // r19
 340         mov             r15=b7
 341         ;;
 342 }
 343 {       .mmi
 344         .mem.offset     0,0
 345         st8.spill       [r2]=r20,16             // r20
 346         .mem.offset     8,0
 347         st8.spill       [r3]=r21,16             // r21
 348         mov             b7=r8
 349         ;;
 350 }
 351 {       .mmi
 352         .mem.offset     0,0
 353         st8.spill       [r2]=r22,16             // r22
 354         .mem.offset     8,0
 355         st8.spill       [r3]=r23,16             // r23
 356         ;;
 357 }
 358
 359         .mem.offset     0,0
 360         st8.spill       [r2]=r24,16             // r24
 361         .mem.offset     8,0
 362         st8.spill       [r3]=r25,16             // r25
 363         ;;
 364         .mem.offset     0,0
 365         st8.spill       [r2]=r26,16             // r26
 366         .mem.offset     8,0
 367         st8.spill       [r3]=r27,16             // r27
 368         ;;
 369         .mem.offset     0,0
 370         st8.spill       [r2]=r28,16             // r28
 371         .mem.offset     8,0
 372         st8.spill       [r3]=r29,16             // r29
 373         ;;
 374         .mem.offset     0,0
 375         st8.spill       [r2]=r30,16             // r30
 376         .mem.offset     8,0
 377         st8.spill       [r3]=r31,16             // r31
 378         ;;
 379
 380 {       .mmi
 381         st8             [r2]=r14,16             // b6
 382         mov             r17=ar.unat
 383         nop             0
 384         ;;
 385 }
 386 {       .mmi
 387         st8             [r3]=r15,16             // b7
 388         mov             r16=ar.ccv
 389         nop             0
 390         ;;
 391 }
 392 {       .mmi
 393         st8             [r2]=r16,16             // ccv
 394         st8             [r3]=r10,16             // csd
 395         nop             0
 396         ;;
 397 }
 398 {       .mmi
 399         st8             [r2]=r11,24             // ssd
 400         st8             [r9]=r17
 401         nop             0
 402         ;;
 403 }
 404
 405         stf.spill       [r3]=f6,32              // f6
 406         stf.spill       [r2]=f7,32              // f7
 407         ;;
 408         stf.spill       [r3]=f8,32              // f8
 409         stf.spill       [r2]=f9,32              // f9
 410         ;;
 411         stf.spill       [r3]=f10,32             // f10
 412         stf.spill       [r2]=f11,32             // f11
 413         ;;
 414         stf.spill       [r3]=f12,32             // f12
 415         stf.spill       [r2]=f13,32             // f13
 416         ;;
 417         stf.spill       [r3]=f14                // f14
 418         stf.spill       [r2]=f15                // f15
 419         ;;
 420 {       .mmi
 421         mov             ar.rsc=3
 422         mov             r13=ar.k4
 423         nop             0
 424         ;;
 425 }
 426 {       .mlx
 427         ssm             psr.ic|psr.dfh
 428         movl            gp=__gp
 429         ;;
 430 }
 431
 432         /* PTC.G leave non-exclusive */
 433         srlz.d
 434         movl    r25 = pmap_ptc_g_sem
 435         ;;
 436 .ptc_g_1:
 437         ld8.acq r26 = [r25]
 438         ;;
 439         mov     ar.ccv = r26
 440         adds    r27 = -1, r26
 441         ;;
 442         cmpxchg8.rel    r27 = [r25], r27, ar.ccv
 443         ;;
 444         cmp.ne  p12, p0 = r26, r27
 445 (p12)   br.cond.spnt.few .ptc_g_1
 446         ;;
 447
 448 {       .mib
 449         srlz.d
 450         nop             0
 451         br.sptk         b7
 452         ;;
 453 }
 454 END(exception_save)
 455
 456 /*
 457  * exception_restore:   restore interrupted state
 458  *
 459  * Arguments:
 460  *      sp+16   trapframe pointer
 461  */
 462 ENTRY_NOPROFILE(exception_restore, 0)
 463 {       .mmi
 464         rsm             psr.i
 465         add             r3=SIZEOF_TRAPFRAME-16,sp
 466         add             r2=SIZEOF_TRAPFRAME,sp
 467         ;;
 468 }
 469 {       .mmi
 470         srlz.d
 471         add             r8=SIZEOF_SPECIAL+32,sp
 472         nop             0
 473         ;;
 474 }
 475         // The next load can trap. Let it be...
 476         ldf.fill        f15=[r2],-32            // f15
 477         ldf.fill        f14=[r3],-32            // f14
 478         add             sp=16,sp
 479         ;;
 480         ldf.fill        f13=[r2],-32            // f13
 481         ldf.fill        f12=[r3],-32            // f12
 482         ;;
 483         ldf.fill        f11=[r2],-32            // f11
 484         ldf.fill        f10=[r3],-32            // f10
 485         ;;
 486         ldf.fill        f9=[r2],-32             // f9
 487         ldf.fill        f8=[r3],-32             // f8
 488         ;;
 489         ldf.fill        f7=[r2],-24             // f7
 490         ldf.fill        f6=[r3],-16             // f6
 491         ;;
 492
 493 {       .mmi
 494         ld8             r8=[r8]                 // unat (after)
 495         ;;
 496         mov             ar.unat=r8
 497         nop             0
 498         ;;
 499 }
 500
 501         ld8             r10=[r2],-16            // ssd
 502         ld8             r11=[r3],-16            // csd
 503         ;;
 504         mov             ar.ssd=r10
 505         mov             ar.csd=r11
 506
 507         ld8             r14=[r2],-16            // ccv
 508         ld8             r15=[r3],-16            // b7
 509         ;;
 510
 511 {       .mmi
 512         mov             ar.ccv=r14
 513         ld8             r8=[r2],-16             // b6
 514         mov             b7=r15
 515         ;;
 516 }
 517 {       .mmi
 518         ld8.fill        r31=[r3],-16            // r31
 519         ld8.fill        r30=[r2],-16            // r30
 520         mov             b6=r8
 521         ;;
 522 }
 523
 524         ld8.fill        r29=[r3],-16            // r29
 525         ld8.fill        r28=[r2],-16            // r28
 526         ;;
 527         ld8.fill        r27=[r3],-16            // r27
 528         ld8.fill        r26=[r2],-16            // r26
 529         ;;
 530         ld8.fill        r25=[r3],-16            // r25
 531         ld8.fill        r24=[r2],-16            // r24
 532         ;;
 533         ld8.fill        r23=[r3],-16            // r23
 534         ld8.fill        r22=[r2],-16            // r22
 535         ;;
 536         ld8.fill        r21=[r3],-16            // r21
 537         ld8.fill        r20=[r2],-16            // r20
 538         ;;
 539         ld8.fill        r19=[r3],-16            // r19
 540         ld8.fill        r18=[r2],-16            // r18
 541         ;;
 542
 543 {       .mmb
 544         ld8.fill        r17=[r3],-16            // r17
 545         ld8.fill        r16=[r2],-16            // r16
 546         bsw.0
 547         ;;
 548 }
 549 {       .mmi
 550         ld8.fill        r15=[r3],-16            // r15
 551         ld8.fill        r14=[r2],-16            // r14
 552         add             r31=16,sp
 553         ;;
 554 }
 555 {       .mmi
 556         ld8             r16=[sp]                // tf_length
 557         ld8.fill        r11=[r3],-16            // r11
 558         add             r30=24,sp
 559         ;;
 560 }
 561 {       .mmi
 562         ld8.fill        r10=[r2],-16            // r10
 563         ld8.fill        r9=[r3],-16             // r9
 564         add             r16=r16,sp              // ar.k7
 565         ;;
 566 }
 567 {       .mmi
 568         ld8.fill        r8=[r2],-16             // r8
 569         ld8.fill        r3=[r3]                 // r3
 570         ;;
 571 }
 572         // We want nested TLB faults from here on...
 573         rsm             psr.ic|psr.i
 574         ld8.fill        r2=[r2]                 // r2
 575         nop             0
 576         ;;
 577         srlz.d
 578         ld8.fill        sp=[r31],16             // sp
 579         nop             0
 580         ;;
 581
 582         ld8             r17=[r30],16            // unat
 583         ld8             r29=[r31],16            // rp
 584         ;;
 585         ld8             r18=[r30],16            // pr
 586         ld8             r28=[r31],16            // pfs
 587         mov             rp=r29
 588         ;;
 589         ld8             r20=[r30],24            // bspstore
 590         ld8             r21=[r31],24            // rnat
 591         mov             ar.pfs=r28
 592         ;;
 593         ld8.fill        r26=[r30],16            // tp
 594         ld8             r22=[r31],16            // rsc
 595         ;;
 596 {       .mmi
 597         ld8             r23=[r30],16            // fpsr
 598         ld8             r24=[r31],16            // psr
 599         extr.u          r28=r20,61,3
 600         ;;
 601 }
 602 {       .mmi
 603         ld8.fill        r1=[r30],16             // gp
 604         ld8             r27=[r31],16            // ndirty
 605         cmp.le          p14,p15=5,r28
 606         ;;
 607 }
 608 {       .mmi
 609         ld8             r25=[r30]               // cfm
 610         ld8             r19=[r31]               // ip
 611         nop             0
 612         ;;
 613 }
 614 {       .mii
 615         // Switch register stack
 616         alloc           r30=ar.pfs,0,0,0,0      // discard current frame
 617         shl             r31=r27,16              // value for ar.rsc
 618 (p15)   mov             r13=r26
 619         ;;
 620 }
 621         // The loadrs can fault if the backing store is not currently
 622         // mapped. We assured forward progress by getting everything we
 623         // need from the trapframe so that we don't care if the CPU
 624         // purges that translation when it needs to insert a new one for
 625         // the backing store.
 626 {       .mmi
 627         mov             ar.rsc=r31              // setup for loadrs
 628         mov             ar.k7=r16
 629         addl            r29=NTLBRT_RESTORE,r0   // 22-bit restart token
 630         ;;
 631 }
 632 exception_restore_restart:
 633 {       .mmi
 634         mov             r30=ar.bspstore
 635         ;;
 636         loadrs                                  // load user regs
 637         nop             0
 638         ;;
 639 }
 640 {       .mmi
 641         mov             r31=ar.bspstore
 642         ;;
 643         mov             ar.bspstore=r20
 644         dep             r31=0,r31,0,13          // 8KB aligned
 645         ;;
 646 }
 647 {       .mmi
 648         mov             ar.k6=r31
 649         mov             ar.rnat=r21
 650         nop             0
 651         ;;
 652 }
 653 {       .mmi
 654         mov             ar.unat=r17
 655         mov             cr.iip=r19
 656         nop             0
 657 }
 658 {       .mmi
 659         mov             cr.ipsr=r24
 660         mov             cr.ifs=r25
 661         mov             pr=r18,0x1ffff
 662         ;;
 663 }
 664 {       .mmb
 665         mov             ar.rsc=r22
 666         mov             ar.fpsr=r23
 667         rfi
 668         ;;
 669 }
 670 END(exception_restore)
 671
 672 /*
 673  * Call exception_save_regs to preserve the interrupted state in a
 674  * trapframe. Note that we don't use a call instruction because we
 675  * must be careful not to lose track of the RSE state. We then call
 676  * trap() with the value of _n_ as an argument to handle the
 677  * exception. We arrange for trap() to return to exception_restore
 678  * which will restore the interrupted state before executing an rfi to
 679  * resume it.
 680  */
 681 #define CALL(_func_, _n_, _ifa_)                \
 682 {       .mib ;                                  \
 683         mov             r17=_ifa_ ;             \
 684         mov             r16=ip ;                \
 685         br.sptk         exception_save ;;       \
 686 } ;                                             \
 687 {       .mmi ;                                  \
 688         alloc           r15=ar.pfs,0,0,2,0 ;;   \
 689 (p11)   ssm             psr.i ;                 \
 690         mov             out0=_n_ ;;             \
 691 } ;                                             \
 692 {       .mib ;                                  \
 693 (p11)   srlz.d ;                                \
 694         add             out1=16,sp ;            \
 695         br.call.sptk    rp=_func_ ;;            \
 696 } ;                                             \
 697 {       .mib ;                                  \
 698         nop             0 ;                     \
 699         nop             0 ;                     \
 700         br.sptk         exception_restore ;;    \
 701 }
 702
 703 #define IVT_ENTRY(name, offset)                 \
 704         .org    ia64_vector_table + offset;     \
 705         .global ivt_##name;                     \
 706         .proc   ivt_##name;                     \
 707         .prologue;                              \
 708         .unwabi @svr4, 'I';                     \
 709         .save   rp, r0;                         \
 710         .body;                                  \
 711 ivt_##name:                                     \
 712         XTRACE(offset)
 713
 714 #define IVT_END(name)                           \
 715         .endp   ivt_##name
 716
 717 #ifdef COMPAT_FREEBSD32
 718 #define IA32_TRAP       ia32_trap
 719 #else
 720 #define IA32_TRAP       trap
 721 #endif
 722
 723 /*
 724  * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64
 725  * bundles per vector and 48 slots with 16 bundles per vector.
 726  */
 727
 728         .section .text.ivt,"ax"
 729
 730         .align  32768
 731         .global ia64_vector_table
 732         .size   ia64_vector_table, 32768
 733 ia64_vector_table:
 734
 735 IVT_ENTRY(VHPT_Translation, 0x0000)
 736         CALL(trap, 0, cr.ifa)
 737 IVT_END(VHPT_Translation)
 738
 739 IVT_ENTRY(Instruction_TLB, 0x0400)
 740         mov     r16=cr.ifa
 741         mov     r17=pr
 742         ;;
 743         thash   r18=r16
 744         ttag    r19=r16
 745         ;;
 746         add     r21=16,r18              // tag
 747         add     r20=24,r18              // collision chain
 748         ;;
 749         ld8     r21=[r21]               // check VHPT tag
 750         ld8     r20=[r20]               // bucket head
 751         ;;
 752         cmp.ne  p15,p0=r21,r19
 753 (p15)   br.dpnt.few 1f
 754         ;;
 755         ld8     r21=[r18]               // read pte
 756         ;;
 757         itc.i   r21                     // insert pte
 758         mov     pr=r17,0x1ffff
 759         ;;
 760         rfi                             // done
 761         ;;
 762 1:      rsm     psr.dt                  // turn off data translations
 763         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
 764         ;;
 765         srlz.d                          // serialize
 766         ld8     r20=[r20]               // first entry
 767         ;;
 768 2:      cmp.eq  p15,p0=r0,r20           // done?
 769 (p15)   br.cond.spnt.few 9f             // bail if done
 770         ;;
 771         add     r21=16,r20              // tag location
 772         ;;
 773         ld8     r21=[r21]               // read tag
 774         ;;
 775         cmp.ne  p15,p0=r21,r19          // compare tags
 776 (p15)   br.cond.sptk.few 3f             // if not, read next in chain
 777         ;;
 778         ld8     r21=[r20]               // read pte
 779         mov     r22=PTE_ACCESSED
 780         ;;
 781         or      r21=r21,r22
 782         ;;
 783         st8     [r20]=r21,8
 784         ;;
 785         ld8     r22=[r20]               // read rest of pte
 786         ;;
 787         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
 788         ;;
 789         add     r20=16,r18              // address of tag
 790         ;;
 791         ld8.acq r23=[r20]               // read old tag
 792         ;;
 793         dep     r23=-1,r23,63,1         // set ti bit
 794         ;;
 795         st8.rel [r20]=r23               // store old tag + ti
 796         ;;
 797         mf                              // make sure everyone sees
 798         ;;
 799         st8     [r18]=r21,8             // store pte
 800         ;;
 801         st8     [r18]=r22,8
 802         ;;
 803         st8.rel [r18]=r19               // store new tag
 804         ;;
 805         itc.i   r21                     // and place in TLB
 806         ssm     psr.dt
 807         ;;
 808         srlz.d
 809         mov     pr=r17,0x1ffff          // restore predicates
 810         rfi
 811         ;;
 812 3:      add     r20=24,r20              // next in chain
 813         ;;
 814         ld8     r20=[r20]               // read chain
 815         br.cond.sptk.few 2b             // loop
 816         ;;
 817 9:      ssm     psr.dt
 818         mov     pr=r17,0x1ffff          // restore predicates
 819         ;;
 820         srlz.d
 821         ;;
 822         CALL(trap, 20, cr.ifa)          // Page Not Present trap
 823 IVT_END(Instruction_TLB)
 824
 825 IVT_ENTRY(Data_TLB, 0x0800)
 826         mov     r16=cr.ifa
 827         mov     r17=pr
 828         ;;
 829         thash   r18=r16
 830         ttag    r19=r16
 831         ;;
 832         add     r21=16,r18              // tag
 833         add     r20=24,r18              // collision chain
 834         ;;
 835         ld8     r21=[r21]               // check VHPT tag
 836         ld8     r20=[r20]               // bucket head
 837         ;;
 838         cmp.ne  p15,p0=r21,r19
 839 (p15)   br.dpnt.few 1f
 840         ;;
 841         ld8     r21=[r18]               // read pte
 842         ;;
 843         itc.d   r21                     // insert pte
 844         mov     pr=r17,0x1ffff
 845         ;;
 846         rfi                             // done
 847         ;;
 848 1:      rsm     psr.dt                  // turn off data translations
 849         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
 850         ;;
 851         srlz.d                          // serialize
 852         ld8     r20=[r20]               // first entry
 853         ;;
 854 2:      cmp.eq  p15,p0=r0,r20           // done?
 855 (p15)   br.cond.spnt.few 9f             // bail if done
 856         ;;
 857         add     r21=16,r20              // tag location
 858         ;;
 859         ld8     r21=[r21]               // read tag
 860         ;;
 861         cmp.ne  p15,p0=r21,r19          // compare tags
 862 (p15)   br.cond.sptk.few 3f             // if not, read next in chain
 863         ;;
 864         ld8     r21=[r20]               // read pte
 865         mov     r22=PTE_ACCESSED
 866         ;;
 867         or      r21=r21,r22
 868         ;;
 869         st8     [r20]=r21,8
 870         ;;
 871         ld8     r22=[r20]               // read rest of pte
 872         ;;
 873         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
 874         ;;
 875         add     r20=16,r18              // address of tag
 876         ;;
 877         ld8.acq r23=[r20]               // read old tag
 878         ;;
 879         dep     r23=-1,r23,63,1         // set ti bit
 880         ;;
 881         st8.rel [r20]=r23               // store old tag + ti
 882         ;;
 883         mf                              // make sure everyone sees
 884         ;;
 885         st8     [r18]=r21,8             // store pte
 886         ;;
 887         st8     [r18]=r22,8
 888         ;;
 889         st8.rel [r18]=r19               // store new tag
 890         ;;
 891         itc.d   r21                     // and place in TLB
 892         ssm     psr.dt
 893         ;;
 894         srlz.d
 895         mov     pr=r17,0x1ffff          // restore predicates
 896         rfi
 897         ;;
 898 3:      add     r20=24,r20              // next in chain
 899         ;;
 900         ld8     r20=[r20]               // read chain
 901         br.cond.sptk.few 2b             // loop
 902         ;;
 903 9:      ssm     psr.dt
 904         mov     pr=r17,0x1ffff          // restore predicates
 905         ;;
 906         srlz.d
 907         ;;
 908         CALL(trap, 20, cr.ifa)          // Page Not Present trap
 909 IVT_END(Data_TLB)
 910
 911 IVT_ENTRY(Alternate_Instruction_TLB, 0x0c00)
 912         mov     r16=cr.ifa              // where did it happen
 913         mov     r18=pr                  // save predicates
 914         ;;
 915         extr.u  r17=r16,61,3            // get region number
 916         ;;
 917         cmp.ge  p13,p0=5,r17            // RR0-RR5?
 918         cmp.eq  p15,p14=7,r17           // RR7->p15, RR6->p14
 919 (p13)   br.spnt 9f
 920         ;;
 921 (p15)   movl    r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 922                         PTE_AR_RX+PTE_ED
 923 (p14)   movl    r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 924                         PTE_AR_RX
 925         ;;
 926         dep     r16=0,r16,50,14         // clear bits above PPN
 927         ;;
 928         dep     r16=r17,r16,0,12        // put pte bits in 0..11
 929         ;;
 930         itc.i   r16
 931         mov     pr=r18,0x1ffff          // restore predicates
 932         ;;
 933         rfi
 934         ;;
 935 9:      mov     pr=r18,0x1ffff          // restore predicates
 936         CALL(trap, 3, cr.ifa)
 937 IVT_END(Alternate_Instruction_TLB)
 938
 939 IVT_ENTRY(Alternate_Data_TLB, 0x1000)
 940         mov     r16=cr.ifa              // where did it happen
 941         mov     r18=pr                  // save predicates
 942         ;;
 943         extr.u  r17=r16,61,3            // get region number
 944         ;;
 945         cmp.ge  p13,p0=5,r17            // RR0-RR5?
 946         cmp.eq  p15,p14=7,r17           // RR7->p15, RR6->p14
 947 (p13)   br.spnt 9f
 948         ;;
 949 (p15)   movl    r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 950                         PTE_AR_RW+PTE_ED
 951 (p14)   movl    r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 952                         PTE_AR_RW
 953         ;;
 954         dep     r16=0,r16,50,14         // clear bits above PPN
 955         ;;
 956         dep     r16=r17,r16,0,12        // put pte bits in 0..11
 957         ;;
 958         itc.d   r16
 959         mov     pr=r18,0x1ffff          // restore predicates
 960         ;;
 961         rfi
 962         ;;
 963 9:      mov     pr=r18,0x1ffff          // restore predicates
 964         CALL(trap, 4, cr.ifa)
 965 IVT_END(Alternate_Data_TLB)
 966
 967 IVT_ENTRY(Data_Nested_TLB, 0x1400)
 968         // See exception_save_restart and exception_restore_restart for the
 969         // contexts that may cause a data nested TLB. We can only use the
 970         // banked general registers and predicates, but don't use:
 971         //      p14 & p15       -       Set in exception save
 972         //      r16 & r17       -       Arguments to exception save
 973         //      r30             -       Faulting address (modulo page size)
 974         // We assume r30 has the virtual addresses that relate to the data
 975         // nested TLB fault. The address does not have to be exact, as long
 976         // as it's in the same page. We use physical addressing to avoid
 977         // double nested faults. Since all virtual addresses we encounter
 978         // here are direct mapped region 7 addresses, we have no problem
 979         // constructing physical addresses.
 980 {       .mlx
 981         rsm             psr.dt
 982         movl            r27=ia64_kptdir
 983         ;;
 984 }
 985 {       .mii
 986         srlz.d
 987         dep             r27=0,r27,61,3
 988         ;;
 989         extr.u          r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3    // dir L0 index
 990 }
 991 {       .mii
 992         ld8             r27=[r27]                               // dir L0 page
 993         extr.u          r26=r30,2*PAGE_SHIFT-5, PAGE_SHIFT-3    // dir L1 index
 994         ;;
 995         dep             r27=0,r27,61,3
 996         ;;
 997 }
 998 {       .mmi
 999         shladd          r27=r28,3,r27
1000         ;;
1001         ld8             r27=[r27]                               // dir L1 page
1002         extr.u          r28=r30,PAGE_SHIFT,PAGE_SHIFT-5         // pte index
1003         ;;
1004 }
1005 {       .mmi
1006         shladd          r27=r26,3,r27
1007         ;;
1008         mov             r26=rr[r30]
1009         dep             r27=0,r27,61,3
1010         ;;
1011 }
1012 {       .mii
1013         ld8             r27=[r27]                               // pte page
1014         shl             r28=r28,5
1015         dep             r26=0,r26,0,2
1016         ;;
1017 }
1018 {       .mmi
1019         add             r27=r28,r27
1020         ;;
1021         mov             cr.ifa=r30
1022         dep             r27=0,r27,61,3
1023         ;;
1024 }
1025 {       .mmi
1026         ld8             r28=[r27]               // pte
1027         ;;
1028         mov             cr.itir=r26
1029         or              r28=PTE_DIRTY+PTE_ACCESSED,r28
1030         ;;
1031 }
1032 {       .mmi
1033         st8             [r27]=r28
1034         ;;
1035         addl            r26=NTLBRT_SAVE,r0
1036         addl            r27=NTLBRT_RESTORE,r0
1037 }
1038 {       .mmi
1039         itc.d           r28
1040         ;;
1041         ssm             psr.dt
1042         cmp.eq          p12,p0=r29,r26
1043         ;;
1044 }
1045 {       .mib
1046         srlz.d
1047         cmp.eq          p13,p0=r29,r27
1048 (p12)   br.sptk         exception_save_restart
1049         ;;
1050 }
1051 {       .mib
1052         nop             0
1053         nop             0
1054 (p13)   br.sptk         exception_restore_restart
1055         ;;
1056 }
1057 {       .mlx
1058         mov             r26=ar.bsp
1059         movl            r27=kstack
1060         ;;
1061 }
1062 {       .mmi
1063         mov             r28=sp
1064         nop             0
1065         addl            r27=KSTACK_PAGES*PAGE_SIZE-16,r0
1066         ;;
1067 }
1068 {       .mmi
1069         mov             sp=r27
1070         ;;
1071         mov             r27=ar.bspstore
1072         nop             0
1073         ;;
1074 }
1075         CALL(trap, 5, r30)
1076 IVT_END(Data_Nested_TLB)
1077
1078 IVT_ENTRY(Instruction_Key_Miss, 0x1800)
1079         CALL(trap, 6, cr.ifa)
1080 IVT_END(Instruction_Key_Miss)
1081
1082 IVT_ENTRY(Data_Key_Miss, 0x1c00)
1083         CALL(trap, 7, cr.ifa)
1084 IVT_END(Data_Key_Miss)
1085
1086 IVT_ENTRY(Dirty_Bit, 0x2000)
1087         mov     r16=cr.ifa
1088         mov     r17=pr
1089         ;;
1090         thash   r18=r16
1091         ;;
1092         ttag    r19=r16
1093         add     r20=24,r18              // collision chain
1094         ;;
1095         ld8     r20=[r20]               // bucket head
1096         ;;
1097         rsm     psr.dt                  // turn off data translations
1098         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1099         ;;
1100         srlz.d                          // serialize
1101         ld8     r20=[r20]               // first entry
1102         ;;
1103 1:      cmp.eq  p15,p0=r0,r20           // done?
1104 (p15)   br.cond.spnt.few 9f             // bail if done
1105         ;;
1106         add     r21=16,r20              // tag location
1107         ;;
1108         ld8     r21=[r21]               // read tag
1109         ;;
1110         cmp.ne  p15,p0=r21,r19          // compare tags
1111 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1112         ;;
1113         ld8     r21=[r20]               // read pte
1114         mov     r22=PTE_DIRTY+PTE_ACCESSED
1115         ;;
1116         or      r21=r22,r21             // set dirty & access bit
1117         ;;
1118         st8     [r20]=r21,8             // store back
1119         ;;
1120         ld8     r22=[r20]               // read rest of pte
1121         ;;
1122         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1123         ;;
1124         add     r20=16,r18              // address of tag
1125         ;;
1126         ld8.acq r23=[r20]               // read old tag
1127         ;;
1128         dep     r23=-1,r23,63,1         // set ti bit
1129         ;;
1130         st8.rel [r20]=r23               // store old tag + ti
1131         ;;
1132         mf                              // make sure everyone sees
1133         ;;
1134         st8     [r18]=r21,8             // store pte
1135         ;;
1136         st8     [r18]=r22,8
1137         ;;
1138         st8.rel [r18]=r19               // store new tag
1139         ;;
1140         itc.d   r21                     // and place in TLB
1141         ssm     psr.dt
1142         ;;
1143         srlz.d
1144         mov     pr=r17,0x1ffff          // restore predicates
1145         rfi
1146         ;;
1147 2:      add     r20=24,r20              // next in chain
1148         ;;
1149         ld8     r20=[r20]               // read chain
1150         br.cond.sptk.few 1b             // loop
1151         ;;
1152 9:      ssm     psr.dt
1153         mov     pr=r17,0x1ffff          // restore predicates
1154         ;;
1155         srlz.d
1156         ;;
1157         CALL(trap, 8, cr.ifa)                   // die horribly
1158 IVT_END(Dirty_Bit)
1159
1160 IVT_ENTRY(Instruction_Access_Bit, 0x2400)
1161         mov     r16=cr.ifa
1162         mov     r17=pr
1163         ;;
1164         thash   r18=r16
1165         ;;
1166         ttag    r19=r16
1167         add     r20=24,r18              // collision chain
1168         ;;
1169         ld8     r20=[r20]               // bucket head
1170         ;;
1171         rsm     psr.dt                  // turn off data translations
1172         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1173         ;;
1174         srlz.d                          // serialize
1175         ld8     r20=[r20]               // first entry
1176         ;;
1177 1:      cmp.eq  p15,p0=r0,r20           // done?
1178 (p15)   br.cond.spnt.few 9f             // bail if done
1179         ;;
1180         add     r21=16,r20              // tag location
1181         ;;
1182         ld8     r21=[r21]               // read tag
1183         ;;
1184         cmp.ne  p15,p0=r21,r19          // compare tags
1185 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1186         ;;
1187         ld8     r21=[r20]               // read pte
1188         mov     r22=PTE_ACCESSED
1189         ;;
1190         or      r21=r22,r21             // set accessed bit
1191         ;;
1192         st8     [r20]=r21,8             // store back
1193         ;;
1194         ld8     r22=[r20]               // read rest of pte
1195         ;;
1196         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1197         ;;
1198         add     r20=16,r18              // address of tag
1199         ;;
1200         ld8.acq r23=[r20]               // read old tag
1201         ;;
1202         dep     r23=-1,r23,63,1         // set ti bit
1203         ;;
1204         st8.rel [r20]=r23               // store old tag + ti
1205         ;;
1206         mf                              // make sure everyone sees
1207         ;;
1208         st8     [r18]=r21,8             // store pte
1209         ;;
1210         st8     [r18]=r22,8
1211         ;;
1212         st8.rel [r18]=r19               // store new tag
1213         ;;
1214         itc.i   r21                     // and place in TLB
1215         ssm     psr.dt
1216         ;;
1217         srlz.d
1218         mov     pr=r17,0x1ffff          // restore predicates
1219         rfi                             // walker will retry the access
1220         ;;
1221 2:      add     r20=24,r20              // next in chain
1222         ;;
1223         ld8     r20=[r20]               // read chain
1224         br.cond.sptk.few 1b             // loop
1225         ;;
1226 9:      ssm     psr.dt
1227         mov     pr=r17,0x1ffff          // restore predicates
1228         ;;
1229         srlz.d
1230         ;;
1231         CALL(trap, 9, cr.ifa)
1232 IVT_END(Instruction_Access_Bit)
1233
1234 IVT_ENTRY(Data_Access_Bit, 0x2800)
1235         mov     r16=cr.ifa
1236         mov     r17=pr
1237         ;;
1238         thash   r18=r16
1239         ;;
1240         ttag    r19=r16
1241         add     r20=24,r18              // collision chain
1242         ;;
1243         ld8     r20=[r20]               // bucket head
1244         ;;
1245         rsm     psr.dt                  // turn off data translations
1246         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1247         ;;
1248         srlz.d                          // serialize
1249         ld8     r20=[r20]               // first entry
1250         ;;
1251 1:      cmp.eq  p15,p0=r0,r20           // done?
1252 (p15)   br.cond.spnt.few 9f             // bail if done
1253         ;;
1254         add     r21=16,r20              // tag location
1255         ;;
1256         ld8     r21=[r21]               // read tag
1257         ;;
1258         cmp.ne  p15,p0=r21,r19          // compare tags
1259 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1260         ;;
1261         ld8     r21=[r20]               // read pte
1262         mov     r22=PTE_ACCESSED
1263         ;;
1264         or      r21=r22,r21             // set accessed bit
1265         ;;
1266         st8     [r20]=r21,8             // store back
1267         ;;
1268         ld8     r22=[r20]               // read rest of pte
1269         ;;
1270         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1271         ;;
1272         add     r20=16,r18              // address of tag
1273         ;;
1274         ld8.acq r23=[r20]               // read old tag
1275         ;;
1276         dep     r23=-1,r23,63,1         // set ti bit
1277         ;;
1278         st8.rel [r20]=r23               // store old tag + ti
1279         ;;
1280         mf                              // make sure everyone sees
1281         ;;
1282         st8     [r18]=r21,8             // store pte
1283         ;;
1284         st8     [r18]=r22,8
1285         ;;
1286         st8.rel [r18]=r19               // store new tag
1287         ;;
1288         itc.d   r21                     // and place in TLB
1289         ssm     psr.dt
1290         ;;
1291         srlz.d
1292         mov     pr=r17,0x1ffff          // restore predicates
1293         rfi                             // walker will retry the access
1294         ;;
1295 2:      add     r20=24,r20              // next in chain
1296         ;;
1297         ld8     r20=[r20]               // read chain
1298         br.cond.sptk.few 1b             // loop
1299         ;;
1300 9:      ssm     psr.dt
1301         mov     pr=r17,0x1ffff          // restore predicates
1302         ;;
1303         srlz.d
1304         ;;
1305         CALL(trap, 10, cr.ifa)
1306 IVT_END(Data_Access_Bit)
1307
1308 IVT_ENTRY(Break_Instruction, 0x2c00)
1309 {       .mib
1310         mov             r17=cr.iim
1311         mov             r16=ip
1312         br.sptk         exception_save
1313         ;;
1314 }
1315 {       .mmi
1316         alloc           r15=ar.pfs,0,0,2,0
1317         ;;
1318 (p11)   ssm             psr.i
1319         mov             out0=11
1320         ;;
1321 }
1322 {       .mmi
1323         flushrs
1324         ;;
1325 (p11)   srlz.d
1326         add             out1=16,sp
1327 }
1328 {       .mib
1329         nop             0
1330         nop             0
1331         br.call.sptk    rp=trap
1332         ;;
1333 }
1334 {       .mib
1335         nop             0
1336         nop             0
1337         br.sptk         exception_restore
1338         ;;
1339 }
1340 IVT_END(Break_Instruction)
1341
1342 IVT_ENTRY(External_Interrupt, 0x3000)
1343 {       .mib
1344         mov             r17=ar.itc      // Put the ITC in the trapframe.
1345         mov             r16=ip
1346         br.sptk         exception_save
1347         ;;
1348 }
1349 {       .mmi
1350         alloc           r15=ar.pfs,0,0,1,0
1351         nop             0
1352         nop             0
1353         ;;
1354 }
1355 {       .mib
1356         add             out0=16,sp
1357         nop             0
1358         br.call.sptk    rp=ia64_handle_intr
1359         ;;
1360 }
1361 {       .mib
1362         nop             0
1363         nop             0
1364         br.sptk         exception_restore
1365         ;;
1366 }
1367 IVT_END(External_Interrupt)
1368
1369 IVT_ENTRY(Reserved_3400, 0x3400)
1370         CALL(trap, 13, cr.ifa)
1371 IVT_END(Reserved_3400)
1372
1373 IVT_ENTRY(Reserved_3800, 0x3800)
1374         CALL(trap, 14, cr.ifa)
1375 IVT_END(Reserved_3800)
1376
1377 IVT_ENTRY(Reserved_3c00, 0x3c00)
1378         CALL(trap, 15, cr.ifa)
1379 IVT_END(Reserved_3c00)
1380
1381 IVT_ENTRY(Reserved_4000, 0x4000)
1382         CALL(trap, 16, cr.ifa)
1383 IVT_END(Reserved_4000)
1384
1385 IVT_ENTRY(Reserved_4400, 0x4400)
1386         CALL(trap, 17, cr.ifa)
1387 IVT_END(Reserved_4400)
1388
1389 IVT_ENTRY(Reserved_4800, 0x4800)
1390         CALL(trap, 18, cr.ifa)
1391 IVT_END(Reserved_4800)
1392
1393 IVT_ENTRY(Reserved_4c00, 0x4c00)
1394         CALL(trap, 19, cr.ifa)
1395 IVT_END(Reserved_4c00)
1396
1397 IVT_ENTRY(Page_Not_Present, 0x5000)
1398         CALL(trap, 20, cr.ifa)
1399 IVT_END(Page_Not_Present)
1400
1401 IVT_ENTRY(Key_Permission, 0x5100)
1402         CALL(trap, 21, cr.ifa)
1403 IVT_END(Key_Permission)
1404
1405 IVT_ENTRY(Instruction_Access_Rights, 0x5200)
1406         CALL(trap, 22, cr.ifa)
1407 IVT_END(Instruction_Access_Rights)
1408
1409 IVT_ENTRY(Data_Access_Rights, 0x5300)
1410         CALL(trap, 23, cr.ifa)
1411 IVT_END(Data_Access_Rights)
1412
1413 IVT_ENTRY(General_Exception, 0x5400)
1414         CALL(trap, 24, cr.ifa)
1415 IVT_END(General_Exception)
1416
1417 IVT_ENTRY(Disabled_FP_Register, 0x5500)
1418         CALL(trap, 25, cr.ifa)
1419 IVT_END(Disabled_FP_Register)
1420
1421 IVT_ENTRY(NaT_Consumption, 0x5600)
1422         CALL(trap, 26, cr.ifa)
1423 IVT_END(NaT_Consumption)
1424
1425 IVT_ENTRY(Speculation, 0x5700)
1426         CALL(trap, 27, cr.iim)
1427 IVT_END(Speculation)
1428
1429 IVT_ENTRY(Reserved_5800, 0x5800)
1430         CALL(trap, 28, cr.ifa)
1431 IVT_END(Reserved_5800)
1432
1433 IVT_ENTRY(Debug, 0x5900)
1434         CALL(trap, 29, cr.ifa)
1435 IVT_END(Debug)
1436
1437 IVT_ENTRY(Unaligned_Reference, 0x5a00)
1438         CALL(trap, 30, cr.ifa)
1439 IVT_END(Unaligned_Reference)
1440
1441 IVT_ENTRY(Unsupported_Data_Reference, 0x5b00)
1442         CALL(trap, 31, cr.ifa)
1443 IVT_END(Unsupported_Data_Reference)
1444
1445 IVT_ENTRY(Floating_Point_Fault, 0x5c00)
1446         CALL(trap, 32, cr.ifa)
1447 IVT_END(Floating_Point_Fault)
1448
1449 IVT_ENTRY(Floating_Point_Trap, 0x5d00)
1450         CALL(trap, 33, cr.ifa)
1451 IVT_END(Floating_Point_Trap)
1452
1453 IVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00)
1454         CALL(trap, 34, cr.ifa)
1455 IVT_END(Lower_Privilege_Transfer_Trap)
1456
1457 IVT_ENTRY(Taken_Branch_Trap, 0x5f00)
1458         CALL(trap, 35, cr.ifa)
1459 IVT_END(Taken_Branch_Trap)
1460
1461 IVT_ENTRY(Single_Step_Trap, 0x6000)
1462         CALL(trap, 36, cr.ifa)
1463 IVT_END(Single_Step_Trap)
1464
1465 IVT_ENTRY(Reserved_6100, 0x6100)
1466         CALL(trap, 37, cr.ifa)
1467 IVT_END(Reserved_6100)
1468
1469 IVT_ENTRY(Reserved_6200, 0x6200)
1470         CALL(trap, 38, cr.ifa)
1471 IVT_END(Reserved_6200)
1472
1473 IVT_ENTRY(Reserved_6300, 0x6300)
1474         CALL(trap, 39, cr.ifa)
1475 IVT_END(Reserved_6300)
1476
1477 IVT_ENTRY(Reserved_6400, 0x6400)
1478         CALL(trap, 40, cr.ifa)
1479 IVT_END(Reserved_6400)
1480
1481 IVT_ENTRY(Reserved_6500, 0x6500)
1482         CALL(trap, 41, cr.ifa)
1483 IVT_END(Reserved_6500)
1484
1485 IVT_ENTRY(Reserved_6600, 0x6600)
1486         CALL(trap, 42, cr.ifa)
1487 IVT_END(Reserved_6600)
1488
1489 IVT_ENTRY(Reserved_6700, 0x6700)
1490         CALL(trap, 43, cr.ifa)
1491 IVT_END(Reserved_6700)
1492
1493 IVT_ENTRY(Reserved_6800, 0x6800)
1494         CALL(trap, 44, cr.ifa)
1495 IVT_END(Reserved_6800)
1496
1497 IVT_ENTRY(IA_32_Exception, 0x6900)
1498         CALL(IA32_TRAP, 45, cr.ifa)
1499 IVT_END(IA_32_Exception)
1500
1501 IVT_ENTRY(IA_32_Intercept, 0x6a00)
1502         CALL(IA32_TRAP, 46, cr.iim)
1503 IVT_END(IA_32_Intercept)
1504
1505 IVT_ENTRY(IA_32_Interrupt, 0x6b00)
1506         CALL(IA32_TRAP, 47, cr.ifa)
1507 IVT_END(IA_32_Interrupt)
1508
1509 IVT_ENTRY(Reserved_6c00, 0x6c00)
1510         CALL(trap, 48, cr.ifa)
1511 IVT_END(Reserved_6c00)
1512
1513 IVT_ENTRY(Reserved_6d00, 0x6d00)
1514         CALL(trap, 49, cr.ifa)
1515 IVT_END(Reserved_6d00)
1516
1517 IVT_ENTRY(Reserved_6e00, 0x6e00)
1518         CALL(trap, 50, cr.ifa)
1519 IVT_END(Reserved_6e00)
1520
1521 IVT_ENTRY(Reserved_6f00, 0x6f00)
1522         CALL(trap, 51, cr.ifa)
1523 IVT_END(Reserved_6f00)
1524
1525 IVT_ENTRY(Reserved_7000, 0x7000)
1526         CALL(trap, 52, cr.ifa)
1527 IVT_END(Reserved_7000)
1528
1529 IVT_ENTRY(Reserved_7100, 0x7100)
1530         CALL(trap, 53, cr.ifa)
1531 IVT_END(Reserved_7100)
1532
1533 IVT_ENTRY(Reserved_7200, 0x7200)
1534         CALL(trap, 54, cr.ifa)
1535 IVT_END(Reserved_7200)
1536
1537 IVT_ENTRY(Reserved_7300, 0x7300)
1538         CALL(trap, 55, cr.ifa)
1539 IVT_END(Reserved_7300)
1540
1541 IVT_ENTRY(Reserved_7400, 0x7400)
1542         CALL(trap, 56, cr.ifa)
1543 IVT_END(Reserved_7400)
1544
1545 IVT_ENTRY(Reserved_7500, 0x7500)
1546         CALL(trap, 57, cr.ifa)
1547 IVT_END(Reserved_7500)
1548
1549 IVT_ENTRY(Reserved_7600, 0x7600)
1550         CALL(trap, 58, cr.ifa)
1551 IVT_END(Reserved_7600)
1552
1553 IVT_ENTRY(Reserved_7700, 0x7700)
1554         CALL(trap, 59, cr.ifa)
1555 IVT_END(Reserved_7700)
1556
1557 IVT_ENTRY(Reserved_7800, 0x7800)
1558         CALL(trap, 60, cr.ifa)
1559 IVT_END(Reserved_7800)
1560
1561 IVT_ENTRY(Reserved_7900, 0x7900)
1562         CALL(trap, 61, cr.ifa)
1563 IVT_END(Reserved_7900)
1564
1565 IVT_ENTRY(Reserved_7a00, 0x7a00)
1566         CALL(trap, 62, cr.ifa)
1567 IVT_END(Reserved_7a00)
1568
1569 IVT_ENTRY(Reserved_7b00, 0x7b00)
1570         CALL(trap, 63, cr.ifa)
1571 IVT_END(Reserved_7b00)
1572
1573 IVT_ENTRY(Reserved_7c00, 0x7c00)
1574         CALL(trap, 64, cr.ifa)
1575 IVT_END(Reserved_7c00)
1576
1577 IVT_ENTRY(Reserved_7d00, 0x7d00)
1578         CALL(trap, 65, cr.ifa)
1579 IVT_END(Reserved_7d00)
1580
1581 IVT_ENTRY(Reserved_7e00, 0x7e00)
1582         CALL(trap, 66, cr.ifa)
1583 IVT_END(Reserved_7e00)
1584
1585 IVT_ENTRY(Reserved_7f00, 0x7f00)
1586         CALL(trap, 67, cr.ifa)
1587 IVT_END(Reserved_7f00)