sys/dev/age/if_age.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/endian.h>
  37 #include <sys/kernel.h>
  38 #include <sys/malloc.h>
  39 #include <sys/mbuf.h>
  40 #include <sys/rman.h>
  41 #include <sys/module.h>
  42 #include <sys/queue.h>
  43 #include <sys/socket.h>
  44 #include <sys/sockio.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <net/bpf.h>
  49 #include <net/if.h>
  50 #include <net/if_arp.h>
  51 #include <net/ethernet.h>
  52 #include <net/if_dl.h>
  53 #include <net/if_media.h>
  54 #include <net/if_types.h>
  55 #include <net/if_vlan_var.h>
  56
  57 #include <netinet/in.h>
  58 #include <netinet/in_systm.h>
  59 #include <netinet/ip.h>
  60 #include <netinet/tcp.h>
  61
  62 #include <dev/mii/mii.h>
  63 #include <dev/mii/miivar.h>
  64
  65 #include <dev/pci/pcireg.h>
  66 #include <dev/pci/pcivar.h>
  67
  68 #include <machine/bus.h>
  69 #include <machine/in_cksum.h>
  70
  71 #include <dev/age/if_agereg.h>
  72 #include <dev/age/if_agevar.h>
  73
  74 /* "device miibus" required.  See GENERIC if you get errors here. */
  75 #include "miibus_if.h"
  76
  77 #define AGE_CSUM_FEATURES       (CSUM_TCP | CSUM_UDP)
  78
  79 MODULE_DEPEND(age, pci, 1, 1, 1);
  80 MODULE_DEPEND(age, ether, 1, 1, 1);
  81 MODULE_DEPEND(age, miibus, 1, 1, 1);
  82
  83 /* Tunables. */
  84 static int msi_disable = 0;
  85 static int msix_disable = 0;
  86 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
  87 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
  88
  89 /*
  90  * Devices supported by this driver.
  91  */
  92 static struct age_dev {
  93         uint16_t        age_vendorid;
  94         uint16_t        age_deviceid;
  95         const char      *age_name;
  96 } age_devs[] = {
  97         { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
  98             "Attansic Technology Corp, L1 Gigabit Ethernet" },
  99 };
 100
 101 static int age_miibus_readreg(device_t, int, int);
 102 static int age_miibus_writereg(device_t, int, int, int);
 103 static void age_miibus_statchg(device_t);
 104 static void age_mediastatus(struct ifnet *, struct ifmediareq *);
 105 static int age_mediachange(struct ifnet *);
 106 static int age_probe(device_t);
 107 static void age_get_macaddr(struct age_softc *);
 108 static void age_phy_reset(struct age_softc *);
 109 static int age_attach(device_t);
 110 static int age_detach(device_t);
 111 static void age_sysctl_node(struct age_softc *);
 112 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 113 static int age_check_boundary(struct age_softc *);
 114 static int age_dma_alloc(struct age_softc *);
 115 static void age_dma_free(struct age_softc *);
 116 static int age_shutdown(device_t);
 117 static void age_setwol(struct age_softc *);
 118 static int age_suspend(device_t);
 119 static int age_resume(device_t);
 120 static int age_encap(struct age_softc *, struct mbuf **);
 121 static void age_tx_task(void *, int);
 122 static void age_start(struct ifnet *);
 123 static void age_watchdog(struct age_softc *);
 124 static int age_ioctl(struct ifnet *, u_long, caddr_t);
 125 static void age_mac_config(struct age_softc *);
 126 static void age_link_task(void *, int);
 127 static void age_stats_update(struct age_softc *);
 128 static int age_intr(void *);
 129 static void age_int_task(void *, int);
 130 static void age_txintr(struct age_softc *, int);
 131 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
 132 static int age_rxintr(struct age_softc *, int, int);
 133 static void age_tick(void *);
 134 static void age_reset(struct age_softc *);
 135 static void age_init(void *);
 136 static void age_init_locked(struct age_softc *);
 137 static void age_stop(struct age_softc *);
 138 static void age_stop_txmac(struct age_softc *);
 139 static void age_stop_rxmac(struct age_softc *);
 140 static void age_init_tx_ring(struct age_softc *);
 141 static int age_init_rx_ring(struct age_softc *);
 142 static void age_init_rr_ring(struct age_softc *);
 143 static void age_init_cmb_block(struct age_softc *);
 144 static void age_init_smb_block(struct age_softc *);
 145 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
 146 static void age_rxvlan(struct age_softc *);
 147 static void age_rxfilter(struct age_softc *);
 148 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
 149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
 150 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
 151 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
 152
 153
 154 static device_method_t age_methods[] = {
 155         /* Device interface. */
 156         DEVMETHOD(device_probe,         age_probe),
 157         DEVMETHOD(device_attach,        age_attach),
 158         DEVMETHOD(device_detach,        age_detach),
 159         DEVMETHOD(device_shutdown,      age_shutdown),
 160         DEVMETHOD(device_suspend,       age_suspend),
 161         DEVMETHOD(device_resume,        age_resume),
 162
 163         /* MII interface. */
 164         DEVMETHOD(miibus_readreg,       age_miibus_readreg),
 165         DEVMETHOD(miibus_writereg,      age_miibus_writereg),
 166         DEVMETHOD(miibus_statchg,       age_miibus_statchg),
 167
 168         { NULL, NULL }
 169 };
 170
 171 static driver_t age_driver = {
 172         "age",
 173         age_methods,
 174         sizeof(struct age_softc)
 175 };
 176
 177 static devclass_t age_devclass;
 178
 179 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0);
 180 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0);
 181
 182 static struct resource_spec age_res_spec_mem[] = {
 183         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 184         { -1,                   0,              0 }
 185 };
 186
 187 static struct resource_spec age_irq_spec_legacy[] = {
 188         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 189         { -1,                   0,              0 }
 190 };
 191
 192 static struct resource_spec age_irq_spec_msi[] = {
 193         { SYS_RES_IRQ,          1,              RF_ACTIVE },
 194         { -1,                   0,              0 }
 195 };
 196
 197 static struct resource_spec age_irq_spec_msix[] = {
 198         { SYS_RES_IRQ,          1,              RF_ACTIVE },
 199         { -1,                   0,              0 }
 200 };
 201
 202 /*
 203  *      Read a PHY register on the MII of the L1.
 204  */
 205 static int
 206 age_miibus_readreg(device_t dev, int phy, int reg)
 207 {
 208         struct age_softc *sc;
 209         uint32_t v;
 210         int i;
 211
 212         sc = device_get_softc(dev);
 213
 214         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
 215             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 216         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 217                 DELAY(1);
 218                 v = CSR_READ_4(sc, AGE_MDIO);
 219                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 220                         break;
 221         }
 222
 223         if (i == 0) {
 224                 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
 225                 return (0);
 226         }
 227
 228         return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
 229 }
 230
 231 /*
 232  *      Write a PHY register on the MII of the L1.
 233  */
 234 static int
 235 age_miibus_writereg(device_t dev, int phy, int reg, int val)
 236 {
 237         struct age_softc *sc;
 238         uint32_t v;
 239         int i;
 240
 241         sc = device_get_softc(dev);
 242
 243         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
 244             (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
 245             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 246         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 247                 DELAY(1);
 248                 v = CSR_READ_4(sc, AGE_MDIO);
 249                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 250                         break;
 251         }
 252
 253         if (i == 0)
 254                 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
 255
 256         return (0);
 257 }
 258
 259 /*
 260  *      Callback from MII layer when media changes.
 261  */
 262 static void
 263 age_miibus_statchg(device_t dev)
 264 {
 265         struct age_softc *sc;
 266
 267         sc = device_get_softc(dev);
 268         taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
 269 }
 270
 271 /*
 272  *      Get the current interface media status.
 273  */
 274 static void
 275 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 276 {
 277         struct age_softc *sc;
 278         struct mii_data *mii;
 279
 280         sc = ifp->if_softc;
 281         AGE_LOCK(sc);
 282         mii = device_get_softc(sc->age_miibus);
 283
 284         mii_pollstat(mii);
 285         AGE_UNLOCK(sc);
 286         ifmr->ifm_status = mii->mii_media_status;
 287         ifmr->ifm_active = mii->mii_media_active;
 288 }
 289
 290 /*
 291  *      Set hardware to newly-selected media.
 292  */
 293 static int
 294 age_mediachange(struct ifnet *ifp)
 295 {
 296         struct age_softc *sc;
 297         struct mii_data *mii;
 298         struct mii_softc *miisc;
 299         int error;
 300
 301         sc = ifp->if_softc;
 302         AGE_LOCK(sc);
 303         mii = device_get_softc(sc->age_miibus);
 304         if (mii->mii_instance != 0) {
 305                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 306                         mii_phy_reset(miisc);
 307         }
 308         error = mii_mediachg(mii);
 309         AGE_UNLOCK(sc);
 310
 311         return (error);
 312 }
 313
 314 static int
 315 age_probe(device_t dev)
 316 {
 317         struct age_dev *sp;
 318         int i;
 319         uint16_t vendor, devid;
 320
 321         vendor = pci_get_vendor(dev);
 322         devid = pci_get_device(dev);
 323         sp = age_devs;
 324         for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]);
 325             i++, sp++) {
 326                 if (vendor == sp->age_vendorid &&
 327                     devid == sp->age_deviceid) {
 328                         device_set_desc(dev, sp->age_name);
 329                         return (BUS_PROBE_DEFAULT);
 330                 }
 331         }
 332
 333         return (ENXIO);
 334 }
 335
 336 static void
 337 age_get_macaddr(struct age_softc *sc)
 338 {
 339         uint32_t ea[2], reg;
 340         int i, vpdc;
 341
 342         reg = CSR_READ_4(sc, AGE_SPI_CTRL);
 343         if ((reg & SPI_VPD_ENB) != 0) {
 344                 /* Get VPD stored in TWSI EEPROM. */
 345                 reg &= ~SPI_VPD_ENB;
 346                 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
 347         }
 348
 349         if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
 350                 /*
 351                  * PCI VPD capability found, let TWSI reload EEPROM.
 352                  * This will set ethernet address of controller.
 353                  */
 354                 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
 355                     TWSI_CTRL_SW_LD_START);
 356                 for (i = 100; i > 0; i--) {
 357                         DELAY(1000);
 358                         reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
 359                         if ((reg & TWSI_CTRL_SW_LD_START) == 0)
 360                                 break;
 361                 }
 362                 if (i == 0)
 363                         device_printf(sc->age_dev,
 364                             "reloading EEPROM timeout!\n");
 365         } else {
 366                 if (bootverbose)
 367                         device_printf(sc->age_dev,
 368                             "PCI VPD capability not found!\n");
 369         }
 370
 371         ea[0] = CSR_READ_4(sc, AGE_PAR0);
 372         ea[1] = CSR_READ_4(sc, AGE_PAR1);
 373         sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
 374         sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
 375         sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
 376         sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
 377         sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
 378         sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
 379 }
 380
 381 static void
 382 age_phy_reset(struct age_softc *sc)
 383 {
 384         uint16_t reg, pn;
 385         int i, linkup;
 386
 387         /* Reset PHY. */
 388         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
 389         DELAY(2000);
 390         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
 391         DELAY(2000);
 392
 393 #define ATPHY_DBG_ADDR          0x1D
 394 #define ATPHY_DBG_DATA          0x1E
 395 #define ATPHY_CDTC              0x16
 396 #define PHY_CDTC_ENB            0x0001
 397 #define PHY_CDTC_POFF           8
 398 #define ATPHY_CDTS              0x1C
 399 #define PHY_CDTS_STAT_OK        0x0000
 400 #define PHY_CDTS_STAT_SHORT     0x0100
 401 #define PHY_CDTS_STAT_OPEN      0x0200
 402 #define PHY_CDTS_STAT_INVAL     0x0300
 403 #define PHY_CDTS_STAT_MASK      0x0300
 404
 405         /* Check power saving mode. Magic from Linux. */
 406         age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
 407         for (linkup = 0, pn = 0; pn < 4; pn++) {
 408                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
 409                     (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
 410                 for (i = 200; i > 0; i--) {
 411                         DELAY(1000);
 412                         reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 413                             ATPHY_CDTC);
 414                         if ((reg & PHY_CDTC_ENB) == 0)
 415                                 break;
 416                 }
 417                 DELAY(1000);
 418                 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 419                     ATPHY_CDTS);
 420                 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
 421                         linkup++;
 422                         break;
 423                 }
 424         }
 425         age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
 426             BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
 427         if (linkup == 0) {
 428                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 429                     ATPHY_DBG_ADDR, 0);
 430                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 431                     ATPHY_DBG_DATA, 0x124E);
 432                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 433                     ATPHY_DBG_ADDR, 1);
 434                 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 435                     ATPHY_DBG_DATA);
 436                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 437                     ATPHY_DBG_DATA, reg | 0x03);
 438                 /* XXX */
 439                 DELAY(1500 * 1000);
 440                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 441                     ATPHY_DBG_ADDR, 0);
 442                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 443                     ATPHY_DBG_DATA, 0x024E);
 444     }
 445
 446 #undef  ATPHY_DBG_ADDR
 447 #undef  ATPHY_DBG_DATA
 448 #undef  ATPHY_CDTC
 449 #undef  PHY_CDTC_ENB
 450 #undef  PHY_CDTC_POFF
 451 #undef  ATPHY_CDTS
 452 #undef  PHY_CDTS_STAT_OK
 453 #undef  PHY_CDTS_STAT_SHORT
 454 #undef  PHY_CDTS_STAT_OPEN
 455 #undef  PHY_CDTS_STAT_INVAL
 456 #undef  PHY_CDTS_STAT_MASK
 457 }
 458
 459 static int
 460 age_attach(device_t dev)
 461 {
 462         struct age_softc *sc;
 463         struct ifnet *ifp;
 464         uint16_t burst;
 465         int error, i, msic, msixc, pmc;
 466
 467         error = 0;
 468         sc = device_get_softc(dev);
 469         sc->age_dev = dev;
 470
 471         mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 472             MTX_DEF);
 473         callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
 474         TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
 475         TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
 476
 477         /* Map the device. */
 478         pci_enable_busmaster(dev);
 479         sc->age_res_spec = age_res_spec_mem;
 480         sc->age_irq_spec = age_irq_spec_legacy;
 481         error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
 482         if (error != 0) {
 483                 device_printf(dev, "cannot allocate memory resources.\n");
 484                 goto fail;
 485         }
 486
 487         /* Set PHY address. */
 488         sc->age_phyaddr = AGE_PHY_ADDR;
 489
 490         /* Reset PHY. */
 491         age_phy_reset(sc);
 492
 493         /* Reset the ethernet controller. */
 494         age_reset(sc);
 495
 496         /* Get PCI and chip id/revision. */
 497         sc->age_rev = pci_get_revid(dev);
 498         sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
 499             MASTER_CHIP_REV_SHIFT;
 500         if (bootverbose) {
 501                 device_printf(dev, "PCI device revision : 0x%04x\n",
 502                     sc->age_rev);
 503                 device_printf(dev, "Chip id/revision : 0x%04x\n",
 504                     sc->age_chip_rev);
 505         }
 506
 507         /*
 508          * XXX
 509          * Unintialized hardware returns an invalid chip id/revision
 510          * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
 511          * unplugged cable results in putting hardware into automatic
 512          * power down mode which in turn returns invalld chip revision.
 513          */
 514         if (sc->age_chip_rev == 0xFFFF) {
 515                 device_printf(dev,"invalid chip revision : 0x%04x -- "
 516                     "not initialized?\n", sc->age_chip_rev);
 517                 error = ENXIO;
 518                 goto fail;
 519         }
 520
 521         device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
 522             CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
 523             CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
 524
 525         /* Allocate IRQ resources. */
 526         msixc = pci_msix_count(dev);
 527         msic = pci_msi_count(dev);
 528         if (bootverbose) {
 529                 device_printf(dev, "MSIX count : %d\n", msixc);
 530                 device_printf(dev, "MSI count : %d\n", msic);
 531         }
 532
 533         /* Prefer MSIX over MSI. */
 534         if (msix_disable == 0 || msi_disable == 0) {
 535                 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
 536                     pci_alloc_msix(dev, &msixc) == 0) {
 537                         if (msic == AGE_MSIX_MESSAGES) {
 538                                 device_printf(dev, "Using %d MSIX messages.\n",
 539                                     msixc);
 540                                 sc->age_flags |= AGE_FLAG_MSIX;
 541                                 sc->age_irq_spec = age_irq_spec_msix;
 542                         } else
 543                                 pci_release_msi(dev);
 544                 }
 545                 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
 546                     msic == AGE_MSI_MESSAGES &&
 547                     pci_alloc_msi(dev, &msic) == 0) {
 548                         if (msic == AGE_MSI_MESSAGES) {
 549                                 device_printf(dev, "Using %d MSI messages.\n",
 550                                     msic);
 551                                 sc->age_flags |= AGE_FLAG_MSI;
 552                                 sc->age_irq_spec = age_irq_spec_msi;
 553                         } else
 554                                 pci_release_msi(dev);
 555                 }
 556         }
 557
 558         error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
 559         if (error != 0) {
 560                 device_printf(dev, "cannot allocate IRQ resources.\n");
 561                 goto fail;
 562         }
 563
 564
 565         /* Get DMA parameters from PCIe device control register. */
 566         if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
 567                 sc->age_flags |= AGE_FLAG_PCIE;
 568                 burst = pci_read_config(dev, i + 0x08, 2);
 569                 /* Max read request size. */
 570                 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
 571                     DMA_CFG_RD_BURST_SHIFT;
 572                 /* Max payload size. */
 573                 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
 574                     DMA_CFG_WR_BURST_SHIFT;
 575                 if (bootverbose) {
 576                         device_printf(dev, "Read request size : %d bytes.\n",
 577                             128 << ((burst >> 12) & 0x07));
 578                         device_printf(dev, "TLP payload size : %d bytes.\n",
 579                             128 << ((burst >> 5) & 0x07));
 580                 }
 581         } else {
 582                 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
 583                 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
 584         }
 585
 586         /* Create device sysctl node. */
 587         age_sysctl_node(sc);
 588
 589         if ((error = age_dma_alloc(sc) != 0))
 590                 goto fail;
 591
 592         /* Load station address. */
 593         age_get_macaddr(sc);
 594
 595         ifp = sc->age_ifp = if_alloc(IFT_ETHER);
 596         if (ifp == NULL) {
 597                 device_printf(dev, "cannot allocate ifnet structure.\n");
 598                 error = ENXIO;
 599                 goto fail;
 600         }
 601
 602         ifp->if_softc = sc;
 603         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 604         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 605         ifp->if_ioctl = age_ioctl;
 606         ifp->if_start = age_start;
 607         ifp->if_init = age_init;
 608         ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1;
 609         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
 610         IFQ_SET_READY(&ifp->if_snd);
 611         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
 612         ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO;
 613         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
 614                 sc->age_flags |= AGE_FLAG_PMCAP;
 615                 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
 616         }
 617         ifp->if_capenable = ifp->if_capabilities;
 618
 619         /* Set up MII bus. */
 620         error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
 621             age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
 622             0);
 623         if (error != 0) {
 624                 device_printf(dev, "attaching PHYs failed\n");
 625                 goto fail;
 626         }
 627
 628         ether_ifattach(ifp, sc->age_eaddr);
 629
 630         /* VLAN capability setup. */
 631         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
 632             IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
 633         ifp->if_capenable = ifp->if_capabilities;
 634
 635         /* Tell the upper layer(s) we support long frames. */
 636         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 637
 638         /* Create local taskq. */
 639         TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp);
 640         sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
 641             taskqueue_thread_enqueue, &sc->age_tq);
 642         if (sc->age_tq == NULL) {
 643                 device_printf(dev, "could not create taskqueue.\n");
 644                 ether_ifdetach(ifp);
 645                 error = ENXIO;
 646                 goto fail;
 647         }
 648         taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
 649             device_get_nameunit(sc->age_dev));
 650
 651         if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
 652                 msic = AGE_MSIX_MESSAGES;
 653         else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
 654                 msic = AGE_MSI_MESSAGES;
 655         else
 656                 msic = 1;
 657         for (i = 0; i < msic; i++) {
 658                 error = bus_setup_intr(dev, sc->age_irq[i],
 659                     INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
 660                     &sc->age_intrhand[i]);
 661                 if (error != 0)
 662                         break;
 663         }
 664         if (error != 0) {
 665                 device_printf(dev, "could not set up interrupt handler.\n");
 666                 taskqueue_free(sc->age_tq);
 667                 sc->age_tq = NULL;
 668                 ether_ifdetach(ifp);
 669                 goto fail;
 670         }
 671
 672 fail:
 673         if (error != 0)
 674                 age_detach(dev);
 675
 676         return (error);
 677 }
 678
 679 static int
 680 age_detach(device_t dev)
 681 {
 682         struct age_softc *sc;
 683         struct ifnet *ifp;
 684         int i, msic;
 685
 686         sc = device_get_softc(dev);
 687
 688         ifp = sc->age_ifp;
 689         if (device_is_attached(dev)) {
 690                 AGE_LOCK(sc);
 691                 sc->age_flags |= AGE_FLAG_DETACH;
 692                 age_stop(sc);
 693                 AGE_UNLOCK(sc);
 694                 callout_drain(&sc->age_tick_ch);
 695                 taskqueue_drain(sc->age_tq, &sc->age_int_task);
 696                 taskqueue_drain(sc->age_tq, &sc->age_tx_task);
 697                 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
 698                 ether_ifdetach(ifp);
 699         }
 700
 701         if (sc->age_tq != NULL) {
 702                 taskqueue_drain(sc->age_tq, &sc->age_int_task);
 703                 taskqueue_free(sc->age_tq);
 704                 sc->age_tq = NULL;
 705         }
 706
 707         if (sc->age_miibus != NULL) {
 708                 device_delete_child(dev, sc->age_miibus);
 709                 sc->age_miibus = NULL;
 710         }
 711         bus_generic_detach(dev);
 712         age_dma_free(sc);
 713
 714         if (ifp != NULL) {
 715                 if_free(ifp);
 716                 sc->age_ifp = NULL;
 717         }
 718
 719         if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
 720                 msic = AGE_MSIX_MESSAGES;
 721         else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
 722                 msic = AGE_MSI_MESSAGES;
 723         else
 724                 msic = 1;
 725         for (i = 0; i < msic; i++) {
 726                 if (sc->age_intrhand[i] != NULL) {
 727                         bus_teardown_intr(dev, sc->age_irq[i],
 728                             sc->age_intrhand[i]);
 729                         sc->age_intrhand[i] = NULL;
 730                 }
 731         }
 732
 733         bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
 734         if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
 735                 pci_release_msi(dev);
 736         bus_release_resources(dev, sc->age_res_spec, sc->age_res);
 737         mtx_destroy(&sc->age_mtx);
 738
 739         return (0);
 740 }
 741
 742 static void
 743 age_sysctl_node(struct age_softc *sc)
 744 {
 745         int error;
 746
 747         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 748             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 749             "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats,
 750             "I", "Statistics");
 751
 752         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 753             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 754             "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0,
 755             sysctl_hw_age_int_mod, "I", "age interrupt moderation");
 756
 757         /* Pull in device tunables. */
 758         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 759         error = resource_int_value(device_get_name(sc->age_dev),
 760             device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
 761         if (error == 0) {
 762                 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
 763                     sc->age_int_mod > AGE_IM_TIMER_MAX) {
 764                         device_printf(sc->age_dev,
 765                             "int_mod value out of range; using default: %d\n",
 766                             AGE_IM_TIMER_DEFAULT);
 767                         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 768                 }
 769         }
 770
 771         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 772             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 773             "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit,
 774             0, sysctl_hw_age_proc_limit, "I",
 775             "max number of Rx events to process");
 776
 777         /* Pull in device tunables. */
 778         sc->age_process_limit = AGE_PROC_DEFAULT;
 779         error = resource_int_value(device_get_name(sc->age_dev),
 780             device_get_unit(sc->age_dev), "process_limit",
 781             &sc->age_process_limit);
 782         if (error == 0) {
 783                 if (sc->age_process_limit < AGE_PROC_MIN ||
 784                     sc->age_process_limit > AGE_PROC_MAX) {
 785                         device_printf(sc->age_dev,
 786                             "process_limit value out of range; "
 787                             "using default: %d\n", AGE_PROC_DEFAULT);
 788                         sc->age_process_limit = AGE_PROC_DEFAULT;
 789                 }
 790         }
 791 }
 792
 793 struct age_dmamap_arg {
 794         bus_addr_t      age_busaddr;
 795 };
 796
 797 static void
 798 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 799 {
 800         struct age_dmamap_arg *ctx;
 801
 802         if (error != 0)
 803                 return;
 804
 805         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 806
 807         ctx = (struct age_dmamap_arg *)arg;
 808         ctx->age_busaddr = segs[0].ds_addr;
 809 }
 810
 811 /*
 812  * Attansic L1 controller have single register to specify high
 813  * address part of DMA blocks. So all descriptor structures and
 814  * DMA memory blocks should have the same high address of given
 815  * 4GB address space(i.e. crossing 4GB boundary is not allowed).
 816  */
 817 static int
 818 age_check_boundary(struct age_softc *sc)
 819 {
 820         bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
 821         bus_addr_t cmb_block_end, smb_block_end;
 822
 823         /* Tx/Rx descriptor queue should reside within 4GB boundary. */
 824         tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
 825         rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
 826         rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
 827         cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
 828         smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
 829
 830         if ((AGE_ADDR_HI(tx_ring_end) !=
 831             AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
 832             (AGE_ADDR_HI(rx_ring_end) !=
 833             AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
 834             (AGE_ADDR_HI(rr_ring_end) !=
 835             AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
 836             (AGE_ADDR_HI(cmb_block_end) !=
 837             AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
 838             (AGE_ADDR_HI(smb_block_end) !=
 839             AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
 840                 return (EFBIG);
 841
 842         if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
 843             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
 844             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
 845             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
 846                 return (EFBIG);
 847
 848         return (0);
 849 }
 850
 851 static int
 852 age_dma_alloc(struct age_softc *sc)
 853 {
 854         struct age_txdesc *txd;
 855         struct age_rxdesc *rxd;
 856         bus_addr_t lowaddr;
 857         struct age_dmamap_arg ctx;
 858         int error, i;
 859
 860         lowaddr = BUS_SPACE_MAXADDR;
 861
 862 again:
 863         /* Create parent ring/DMA block tag. */
 864         error = bus_dma_tag_create(
 865             bus_get_dma_tag(sc->age_dev), /* parent */
 866             1, 0,                       /* alignment, boundary */
 867             lowaddr,                    /* lowaddr */
 868             BUS_SPACE_MAXADDR,          /* highaddr */
 869             NULL, NULL,                 /* filter, filterarg */
 870             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
 871             0,                          /* nsegments */
 872             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
 873             0,                          /* flags */
 874             NULL, NULL,                 /* lockfunc, lockarg */
 875             &sc->age_cdata.age_parent_tag);
 876         if (error != 0) {
 877                 device_printf(sc->age_dev,
 878                     "could not create parent DMA tag.\n");
 879                 goto fail;
 880         }
 881
 882         /* Create tag for Tx ring. */
 883         error = bus_dma_tag_create(
 884             sc->age_cdata.age_parent_tag, /* parent */
 885             AGE_TX_RING_ALIGN, 0,       /* alignment, boundary */
 886             BUS_SPACE_MAXADDR,          /* lowaddr */
 887             BUS_SPACE_MAXADDR,          /* highaddr */
 888             NULL, NULL,                 /* filter, filterarg */
 889             AGE_TX_RING_SZ,             /* maxsize */
 890             1,                          /* nsegments */
 891             AGE_TX_RING_SZ,             /* maxsegsize */
 892             0,                          /* flags */
 893             NULL, NULL,                 /* lockfunc, lockarg */
 894             &sc->age_cdata.age_tx_ring_tag);
 895         if (error != 0) {
 896                 device_printf(sc->age_dev,
 897                     "could not create Tx ring DMA tag.\n");
 898                 goto fail;
 899         }
 900
 901         /* Create tag for Rx ring. */
 902         error = bus_dma_tag_create(
 903             sc->age_cdata.age_parent_tag, /* parent */
 904             AGE_RX_RING_ALIGN, 0,       /* alignment, boundary */
 905             BUS_SPACE_MAXADDR,          /* lowaddr */
 906             BUS_SPACE_MAXADDR,          /* highaddr */
 907             NULL, NULL,                 /* filter, filterarg */
 908             AGE_RX_RING_SZ,             /* maxsize */
 909             1,                          /* nsegments */
 910             AGE_RX_RING_SZ,             /* maxsegsize */
 911             0,                          /* flags */
 912             NULL, NULL,                 /* lockfunc, lockarg */
 913             &sc->age_cdata.age_rx_ring_tag);
 914         if (error != 0) {
 915                 device_printf(sc->age_dev,
 916                     "could not create Rx ring DMA tag.\n");
 917                 goto fail;
 918         }
 919
 920         /* Create tag for Rx return ring. */
 921         error = bus_dma_tag_create(
 922             sc->age_cdata.age_parent_tag, /* parent */
 923             AGE_RR_RING_ALIGN, 0,       /* alignment, boundary */
 924             BUS_SPACE_MAXADDR,          /* lowaddr */
 925             BUS_SPACE_MAXADDR,          /* highaddr */
 926             NULL, NULL,                 /* filter, filterarg */
 927             AGE_RR_RING_SZ,             /* maxsize */
 928             1,                          /* nsegments */
 929             AGE_RR_RING_SZ,             /* maxsegsize */
 930             0,                          /* flags */
 931             NULL, NULL,                 /* lockfunc, lockarg */
 932             &sc->age_cdata.age_rr_ring_tag);
 933         if (error != 0) {
 934                 device_printf(sc->age_dev,
 935                     "could not create Rx return ring DMA tag.\n");
 936                 goto fail;
 937         }
 938
 939         /* Create tag for coalesing message block. */
 940         error = bus_dma_tag_create(
 941             sc->age_cdata.age_parent_tag, /* parent */
 942             AGE_CMB_ALIGN, 0,           /* alignment, boundary */
 943             BUS_SPACE_MAXADDR,          /* lowaddr */
 944             BUS_SPACE_MAXADDR,          /* highaddr */
 945             NULL, NULL,                 /* filter, filterarg */
 946             AGE_CMB_BLOCK_SZ,           /* maxsize */
 947             1,                          /* nsegments */
 948             AGE_CMB_BLOCK_SZ,           /* maxsegsize */
 949             0,                          /* flags */
 950             NULL, NULL,                 /* lockfunc, lockarg */
 951             &sc->age_cdata.age_cmb_block_tag);
 952         if (error != 0) {
 953                 device_printf(sc->age_dev,
 954                     "could not create CMB DMA tag.\n");
 955                 goto fail;
 956         }
 957
 958         /* Create tag for statistics message block. */
 959         error = bus_dma_tag_create(
 960             sc->age_cdata.age_parent_tag, /* parent */
 961             AGE_SMB_ALIGN, 0,           /* alignment, boundary */
 962             BUS_SPACE_MAXADDR,          /* lowaddr */
 963             BUS_SPACE_MAXADDR,          /* highaddr */
 964             NULL, NULL,                 /* filter, filterarg */
 965             AGE_SMB_BLOCK_SZ,           /* maxsize */
 966             1,                          /* nsegments */
 967             AGE_SMB_BLOCK_SZ,           /* maxsegsize */
 968             0,                          /* flags */
 969             NULL, NULL,                 /* lockfunc, lockarg */
 970             &sc->age_cdata.age_smb_block_tag);
 971         if (error != 0) {
 972                 device_printf(sc->age_dev,
 973                     "could not create SMB DMA tag.\n");
 974                 goto fail;
 975         }
 976
 977         /* Allocate DMA'able memory and load the DMA map. */
 978         error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
 979             (void **)&sc->age_rdata.age_tx_ring,
 980             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
 981             &sc->age_cdata.age_tx_ring_map);
 982         if (error != 0) {
 983                 device_printf(sc->age_dev,
 984                     "could not allocate DMA'able memory for Tx ring.\n");
 985                 goto fail;
 986         }
 987         ctx.age_busaddr = 0;
 988         error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
 989             sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
 990             AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
 991         if (error != 0 || ctx.age_busaddr == 0) {
 992                 device_printf(sc->age_dev,
 993                     "could not load DMA'able memory for Tx ring.\n");
 994                 goto fail;
 995         }
 996         sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
 997         /* Rx ring */
 998         error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
 999             (void **)&sc->age_rdata.age_rx_ring,
1000             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1001             &sc->age_cdata.age_rx_ring_map);
1002         if (error != 0) {
1003                 device_printf(sc->age_dev,
1004                     "could not allocate DMA'able memory for Rx ring.\n");
1005                 goto fail;
1006         }
1007         ctx.age_busaddr = 0;
1008         error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
1009             sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
1010             AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
1011         if (error != 0 || ctx.age_busaddr == 0) {
1012                 device_printf(sc->age_dev,
1013                     "could not load DMA'able memory for Rx ring.\n");
1014                 goto fail;
1015         }
1016         sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1017         /* Rx return ring */
1018         error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1019             (void **)&sc->age_rdata.age_rr_ring,
1020             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1021             &sc->age_cdata.age_rr_ring_map);
1022         if (error != 0) {
1023                 device_printf(sc->age_dev,
1024                     "could not allocate DMA'able memory for Rx return ring.\n");
1025                 goto fail;
1026         }
1027         ctx.age_busaddr = 0;
1028         error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1029             sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1030             AGE_RR_RING_SZ, age_dmamap_cb,
1031             &ctx, 0);
1032         if (error != 0 || ctx.age_busaddr == 0) {
1033                 device_printf(sc->age_dev,
1034                     "could not load DMA'able memory for Rx return ring.\n");
1035                 goto fail;
1036         }
1037         sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1038         /* CMB block */
1039         error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1040             (void **)&sc->age_rdata.age_cmb_block,
1041             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1042             &sc->age_cdata.age_cmb_block_map);
1043         if (error != 0) {
1044                 device_printf(sc->age_dev,
1045                     "could not allocate DMA'able memory for CMB block.\n");
1046                 goto fail;
1047         }
1048         ctx.age_busaddr = 0;
1049         error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1050             sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1051             AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1052         if (error != 0 || ctx.age_busaddr == 0) {
1053                 device_printf(sc->age_dev,
1054                     "could not load DMA'able memory for CMB block.\n");
1055                 goto fail;
1056         }
1057         sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1058         /* SMB block */
1059         error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1060             (void **)&sc->age_rdata.age_smb_block,
1061             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1062             &sc->age_cdata.age_smb_block_map);
1063         if (error != 0) {
1064                 device_printf(sc->age_dev,
1065                     "could not allocate DMA'able memory for SMB block.\n");
1066                 goto fail;
1067         }
1068         ctx.age_busaddr = 0;
1069         error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1070             sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1071             AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1072         if (error != 0 || ctx.age_busaddr == 0) {
1073                 device_printf(sc->age_dev,
1074                     "could not load DMA'able memory for SMB block.\n");
1075                 goto fail;
1076         }
1077         sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1078
1079         /*
1080          * All ring buffer and DMA blocks should have the same
1081          * high address part of 64bit DMA address space.
1082          */
1083         if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1084             (error = age_check_boundary(sc)) != 0) {
1085                 device_printf(sc->age_dev, "4GB boundary crossed, "
1086                     "switching to 32bit DMA addressing mode.\n");
1087                 age_dma_free(sc);
1088                 /* Limit DMA address space to 32bit and try again. */
1089                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1090                 goto again;
1091         }
1092
1093         /*
1094          * Create Tx/Rx buffer parent tag.
1095          * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1096          * so it needs separate parent DMA tag.
1097          */
1098         error = bus_dma_tag_create(
1099             bus_get_dma_tag(sc->age_dev), /* parent */
1100             1, 0,                       /* alignment, boundary */
1101             BUS_SPACE_MAXADDR,          /* lowaddr */
1102             BUS_SPACE_MAXADDR,          /* highaddr */
1103             NULL, NULL,                 /* filter, filterarg */
1104             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1105             0,                          /* nsegments */
1106             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1107             0,                          /* flags */
1108             NULL, NULL,                 /* lockfunc, lockarg */
1109             &sc->age_cdata.age_buffer_tag);
1110         if (error != 0) {
1111                 device_printf(sc->age_dev,
1112                     "could not create parent buffer DMA tag.\n");
1113                 goto fail;
1114         }
1115
1116         /* Create tag for Tx buffers. */
1117         error = bus_dma_tag_create(
1118             sc->age_cdata.age_buffer_tag, /* parent */
1119             1, 0,                       /* alignment, boundary */
1120             BUS_SPACE_MAXADDR,          /* lowaddr */
1121             BUS_SPACE_MAXADDR,          /* highaddr */
1122             NULL, NULL,                 /* filter, filterarg */
1123             AGE_TSO_MAXSIZE,            /* maxsize */
1124             AGE_MAXTXSEGS,              /* nsegments */
1125             AGE_TSO_MAXSEGSIZE,         /* maxsegsize */
1126             0,                          /* flags */
1127             NULL, NULL,                 /* lockfunc, lockarg */
1128             &sc->age_cdata.age_tx_tag);
1129         if (error != 0) {
1130                 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1131                 goto fail;
1132         }
1133
1134         /* Create tag for Rx buffers. */
1135         error = bus_dma_tag_create(
1136             sc->age_cdata.age_buffer_tag, /* parent */
1137             1, 0,                       /* alignment, boundary */
1138             BUS_SPACE_MAXADDR,          /* lowaddr */
1139             BUS_SPACE_MAXADDR,          /* highaddr */
1140             NULL, NULL,                 /* filter, filterarg */
1141             MCLBYTES,                   /* maxsize */
1142             1,                          /* nsegments */
1143             MCLBYTES,                   /* maxsegsize */
1144             0,                          /* flags */
1145             NULL, NULL,                 /* lockfunc, lockarg */
1146             &sc->age_cdata.age_rx_tag);
1147         if (error != 0) {
1148                 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1149                 goto fail;
1150         }
1151
1152         /* Create DMA maps for Tx buffers. */
1153         for (i = 0; i < AGE_TX_RING_CNT; i++) {
1154                 txd = &sc->age_cdata.age_txdesc[i];
1155                 txd->tx_m = NULL;
1156                 txd->tx_dmamap = NULL;
1157                 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1158                     &txd->tx_dmamap);
1159                 if (error != 0) {
1160                         device_printf(sc->age_dev,
1161                             "could not create Tx dmamap.\n");
1162                         goto fail;
1163                 }
1164         }
1165         /* Create DMA maps for Rx buffers. */
1166         if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1167             &sc->age_cdata.age_rx_sparemap)) != 0) {
1168                 device_printf(sc->age_dev,
1169                     "could not create spare Rx dmamap.\n");
1170                 goto fail;
1171         }
1172         for (i = 0; i < AGE_RX_RING_CNT; i++) {
1173                 rxd = &sc->age_cdata.age_rxdesc[i];
1174                 rxd->rx_m = NULL;
1175                 rxd->rx_dmamap = NULL;
1176                 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1177                     &rxd->rx_dmamap);
1178                 if (error != 0) {
1179                         device_printf(sc->age_dev,
1180                             "could not create Rx dmamap.\n");
1181                         goto fail;
1182                 }
1183         }
1184
1185 fail:
1186         return (error);
1187 }
1188
1189 static void
1190 age_dma_free(struct age_softc *sc)
1191 {
1192         struct age_txdesc *txd;
1193         struct age_rxdesc *rxd;
1194         int i;
1195
1196         /* Tx buffers */
1197         if (sc->age_cdata.age_tx_tag != NULL) {
1198                 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1199                         txd = &sc->age_cdata.age_txdesc[i];
1200                         if (txd->tx_dmamap != NULL) {
1201                                 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1202                                     txd->tx_dmamap);
1203                                 txd->tx_dmamap = NULL;
1204                         }
1205                 }
1206                 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1207                 sc->age_cdata.age_tx_tag = NULL;
1208         }
1209         /* Rx buffers */
1210         if (sc->age_cdata.age_rx_tag != NULL) {
1211                 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1212                         rxd = &sc->age_cdata.age_rxdesc[i];
1213                         if (rxd->rx_dmamap != NULL) {
1214                                 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1215                                     rxd->rx_dmamap);
1216                                 rxd->rx_dmamap = NULL;
1217                         }
1218                 }
1219                 if (sc->age_cdata.age_rx_sparemap != NULL) {
1220                         bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1221                             sc->age_cdata.age_rx_sparemap);
1222                         sc->age_cdata.age_rx_sparemap = NULL;
1223                 }
1224                 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1225                 sc->age_cdata.age_rx_tag = NULL;
1226         }
1227         /* Tx ring. */
1228         if (sc->age_cdata.age_tx_ring_tag != NULL) {
1229                 if (sc->age_cdata.age_tx_ring_map != NULL)
1230                         bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1231                             sc->age_cdata.age_tx_ring_map);
1232                 if (sc->age_cdata.age_tx_ring_map != NULL &&
1233                     sc->age_rdata.age_tx_ring != NULL)
1234                         bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1235                             sc->age_rdata.age_tx_ring,
1236                             sc->age_cdata.age_tx_ring_map);
1237                 sc->age_rdata.age_tx_ring = NULL;
1238                 sc->age_cdata.age_tx_ring_map = NULL;
1239                 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1240                 sc->age_cdata.age_tx_ring_tag = NULL;
1241         }
1242         /* Rx ring. */
1243         if (sc->age_cdata.age_rx_ring_tag != NULL) {
1244                 if (sc->age_cdata.age_rx_ring_map != NULL)
1245                         bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1246                             sc->age_cdata.age_rx_ring_map);
1247                 if (sc->age_cdata.age_rx_ring_map != NULL &&
1248                     sc->age_rdata.age_rx_ring != NULL)
1249                         bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1250                             sc->age_rdata.age_rx_ring,
1251                             sc->age_cdata.age_rx_ring_map);
1252                 sc->age_rdata.age_rx_ring = NULL;
1253                 sc->age_cdata.age_rx_ring_map = NULL;
1254                 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1255                 sc->age_cdata.age_rx_ring_tag = NULL;
1256         }
1257         /* Rx return ring. */
1258         if (sc->age_cdata.age_rr_ring_tag != NULL) {
1259                 if (sc->age_cdata.age_rr_ring_map != NULL)
1260                         bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1261                             sc->age_cdata.age_rr_ring_map);
1262                 if (sc->age_cdata.age_rr_ring_map != NULL &&
1263                     sc->age_rdata.age_rr_ring != NULL)
1264                         bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1265                             sc->age_rdata.age_rr_ring,
1266                             sc->age_cdata.age_rr_ring_map);
1267                 sc->age_rdata.age_rr_ring = NULL;
1268                 sc->age_cdata.age_rr_ring_map = NULL;
1269                 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1270                 sc->age_cdata.age_rr_ring_tag = NULL;
1271         }
1272         /* CMB block */
1273         if (sc->age_cdata.age_cmb_block_tag != NULL) {
1274                 if (sc->age_cdata.age_cmb_block_map != NULL)
1275                         bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1276                             sc->age_cdata.age_cmb_block_map);
1277                 if (sc->age_cdata.age_cmb_block_map != NULL &&
1278                     sc->age_rdata.age_cmb_block != NULL)
1279                         bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1280                             sc->age_rdata.age_cmb_block,
1281                             sc->age_cdata.age_cmb_block_map);
1282                 sc->age_rdata.age_cmb_block = NULL;
1283                 sc->age_cdata.age_cmb_block_map = NULL;
1284                 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1285                 sc->age_cdata.age_cmb_block_tag = NULL;
1286         }
1287         /* SMB block */
1288         if (sc->age_cdata.age_smb_block_tag != NULL) {
1289                 if (sc->age_cdata.age_smb_block_map != NULL)
1290                         bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1291                             sc->age_cdata.age_smb_block_map);
1292                 if (sc->age_cdata.age_smb_block_map != NULL &&
1293                     sc->age_rdata.age_smb_block != NULL)
1294                         bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1295                             sc->age_rdata.age_smb_block,
1296                             sc->age_cdata.age_smb_block_map);
1297                 sc->age_rdata.age_smb_block = NULL;
1298                 sc->age_cdata.age_smb_block_map = NULL;
1299                 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1300                 sc->age_cdata.age_smb_block_tag = NULL;
1301         }
1302
1303         if (sc->age_cdata.age_buffer_tag != NULL) {
1304                 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1305                 sc->age_cdata.age_buffer_tag = NULL;
1306         }
1307         if (sc->age_cdata.age_parent_tag != NULL) {
1308                 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1309                 sc->age_cdata.age_parent_tag = NULL;
1310         }
1311 }
1312
1313 /*
1314  *      Make sure the interface is stopped at reboot time.
1315  */
1316 static int
1317 age_shutdown(device_t dev)
1318 {
1319
1320         return (age_suspend(dev));
1321 }
1322
1323 static void
1324 age_setwol(struct age_softc *sc)
1325 {
1326         struct ifnet *ifp;
1327         struct mii_data *mii;
1328         uint32_t reg, pmcs;
1329         uint16_t pmstat;
1330         int aneg, i, pmc;
1331
1332         AGE_LOCK_ASSERT(sc);
1333
1334         if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1335                 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1336                 /*
1337                  * No PME capability, PHY power down.
1338                  * XXX
1339                  * Due to an unknown reason powering down PHY resulted
1340                  * in unexpected results such as inaccessbility of
1341                  * hardware of freshly rebooted system. Disable
1342                  * powering down PHY until I got more information for
1343                  * Attansic/Atheros PHY hardwares.
1344                  */
1345 #ifdef notyet
1346                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1347                     MII_BMCR, BMCR_PDOWN);
1348 #endif
1349                 return;
1350         }
1351
1352         ifp = sc->age_ifp;
1353         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1354                 /*
1355                  * Note, this driver resets the link speed to 10/100Mbps with
1356                  * auto-negotiation but we don't know whether that operation
1357                  * would succeed or not as it have no control after powering
1358                  * off. If the renegotiation fail WOL may not work. Running
1359                  * at 1Gbps will draw more power than 375mA at 3.3V which is
1360                  * specified in PCI specification and that would result in
1361                  * complete shutdowning power to ethernet controller.
1362                  *
1363                  * TODO
1364                  *  Save current negotiated media speed/duplex/flow-control
1365                  *  to softc and restore the same link again after resuming.
1366                  *  PHY handling such as power down/resetting to 100Mbps
1367                  *  may be better handled in suspend method in phy driver.
1368                  */
1369                 mii = device_get_softc(sc->age_miibus);
1370                 mii_pollstat(mii);
1371                 aneg = 0;
1372                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1373                         switch IFM_SUBTYPE(mii->mii_media_active) {
1374                         case IFM_10_T:
1375                         case IFM_100_TX:
1376                                 goto got_link;
1377                         case IFM_1000_T:
1378                                 aneg++;
1379                         default:
1380                                 break;
1381                         }
1382                 }
1383                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1384                     MII_100T2CR, 0);
1385                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1386                     MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1387                     ANAR_10 | ANAR_CSMA);
1388                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1389                     MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1390                 DELAY(1000);
1391                 if (aneg != 0) {
1392                         /* Poll link state until age(4) get a 10/100 link. */
1393                         for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1394                                 mii_pollstat(mii);
1395                                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1396                                         switch (IFM_SUBTYPE(
1397                                             mii->mii_media_active)) {
1398                                         case IFM_10_T:
1399                                         case IFM_100_TX:
1400                                                 age_mac_config(sc);
1401                                                 goto got_link;
1402                                         default:
1403                                                 break;
1404                                         }
1405                                 }
1406                                 AGE_UNLOCK(sc);
1407                                 pause("agelnk", hz);
1408                                 AGE_LOCK(sc);
1409                         }
1410                         if (i == MII_ANEGTICKS_GIGE)
1411                                 device_printf(sc->age_dev,
1412                                     "establishing link failed, "
1413                                     "WOL may not work!");
1414                 }
1415                 /*
1416                  * No link, force MAC to have 100Mbps, full-duplex link.
1417                  * This is the last resort and may/may not work.
1418                  */
1419                 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1420                 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1421                 age_mac_config(sc);
1422         }
1423
1424 got_link:
1425         pmcs = 0;
1426         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1427                 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1428         CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1429         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1430         reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1431         reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1432         if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1433                 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1434         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1435                 reg |= MAC_CFG_RX_ENB;
1436                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1437         }
1438
1439         /* Request PME. */
1440         pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1441         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1442         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1443                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1444         pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1445 #ifdef notyet
1446         /* See above for powering down PHY issues. */
1447         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1448                 /* No WOL, PHY power down. */
1449                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1450                     MII_BMCR, BMCR_PDOWN);
1451         }
1452 #endif
1453 }
1454
1455 static int
1456 age_suspend(device_t dev)
1457 {
1458         struct age_softc *sc;
1459
1460         sc = device_get_softc(dev);
1461
1462         AGE_LOCK(sc);
1463         age_stop(sc);
1464         age_setwol(sc);
1465         AGE_UNLOCK(sc);
1466
1467         return (0);
1468 }
1469
1470 static int
1471 age_resume(device_t dev)
1472 {
1473         struct age_softc *sc;
1474         struct ifnet *ifp;
1475
1476         sc = device_get_softc(dev);
1477
1478         AGE_LOCK(sc);
1479         age_phy_reset(sc);
1480         ifp = sc->age_ifp;
1481         if ((ifp->if_flags & IFF_UP) != 0)
1482                 age_init_locked(sc);
1483
1484         AGE_UNLOCK(sc);
1485
1486         return (0);
1487 }
1488
1489 static int
1490 age_encap(struct age_softc *sc, struct mbuf **m_head)
1491 {
1492         struct age_txdesc *txd, *txd_last;
1493         struct tx_desc *desc;
1494         struct mbuf *m;
1495         struct ip *ip;
1496         struct tcphdr *tcp;
1497         bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1498         bus_dmamap_t map;
1499         uint32_t cflags, ip_off, poff, vtag;
1500         int error, i, nsegs, prod, si;
1501
1502         AGE_LOCK_ASSERT(sc);
1503
1504         M_ASSERTPKTHDR((*m_head));
1505
1506         m = *m_head;
1507         ip = NULL;
1508         tcp = NULL;
1509         cflags = vtag = 0;
1510         ip_off = poff = 0;
1511         if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1512                 /*
1513                  * L1 requires offset of TCP/UDP payload in its Tx
1514                  * descriptor to perform hardware Tx checksum offload.
1515                  * Additionally, TSO requires IP/TCP header size and
1516                  * modification of IP/TCP header in order to make TSO
1517                  * engine work. This kind of operation takes many CPU
1518                  * cycles on FreeBSD so fast host CPU is needed to get
1519                  * smooth TSO performance.
1520                  */
1521                 struct ether_header *eh;
1522
1523                 if (M_WRITABLE(m) == 0) {
1524                         /* Get a writable copy. */
1525                         m = m_dup(*m_head, M_DONTWAIT);
1526                         /* Release original mbufs. */
1527                         m_freem(*m_head);
1528                         if (m == NULL) {
1529                                 *m_head = NULL;
1530                                 return (ENOBUFS);
1531                         }
1532                         *m_head = m;
1533                 }
1534                 ip_off = sizeof(struct ether_header);
1535                 m = m_pullup(m, ip_off);
1536                 if (m == NULL) {
1537                         *m_head = NULL;
1538                         return (ENOBUFS);
1539                 }
1540                 eh = mtod(m, struct ether_header *);
1541                 /*
1542                  * Check if hardware VLAN insertion is off.
1543                  * Additional check for LLC/SNAP frame?
1544                  */
1545                 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1546                         ip_off = sizeof(struct ether_vlan_header);
1547                         m = m_pullup(m, ip_off);
1548                         if (m == NULL) {
1549                                 *m_head = NULL;
1550                                 return (ENOBUFS);
1551                         }
1552                 }
1553                 m = m_pullup(m, ip_off + sizeof(struct ip));
1554                 if (m == NULL) {
1555                         *m_head = NULL;
1556                         return (ENOBUFS);
1557                 }
1558                 ip = (struct ip *)(mtod(m, char *) + ip_off);
1559                 poff = ip_off + (ip->ip_hl << 2);
1560                 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1561                         m = m_pullup(m, poff + sizeof(struct tcphdr));
1562                         if (m == NULL) {
1563                                 *m_head = NULL;
1564                                 return (ENOBUFS);
1565                         }
1566                         ip = (struct ip *)(mtod(m, char *) + ip_off);
1567                         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1568                         /*
1569                          * L1 requires IP/TCP header size and offset as
1570                          * well as TCP pseudo checksum which complicates
1571                          * TSO configuration. I guess this comes from the
1572                          * adherence to Microsoft NDIS Large Send
1573                          * specification which requires insertion of
1574                          * pseudo checksum by upper stack. The pseudo
1575                          * checksum that NDIS refers to doesn't include
1576                          * TCP payload length so age(4) should recompute
1577                          * the pseudo checksum here. Hopefully this wouldn't
1578                          * be much burden on modern CPUs.
1579                          * Reset IP checksum and recompute TCP pseudo
1580                          * checksum as NDIS specification said.
1581                          */
1582                         ip->ip_sum = 0;
1583                         if (poff + (tcp->th_off << 2) == m->m_pkthdr.len)
1584                                 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1585                                     ip->ip_dst.s_addr,
1586                                     htons((tcp->th_off << 2) + IPPROTO_TCP));
1587                         else
1588                                 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1589                                     ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1590                 }
1591                 *m_head = m;
1592         }
1593
1594         si = prod = sc->age_cdata.age_tx_prod;
1595         txd = &sc->age_cdata.age_txdesc[prod];
1596         txd_last = txd;
1597         map = txd->tx_dmamap;
1598
1599         error =  bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1600             *m_head, txsegs, &nsegs, 0);
1601         if (error == EFBIG) {
1602                 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS);
1603                 if (m == NULL) {
1604                         m_freem(*m_head);
1605                         *m_head = NULL;
1606                         return (ENOMEM);
1607                 }
1608                 *m_head = m;
1609                 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1610                     *m_head, txsegs, &nsegs, 0);
1611                 if (error != 0) {
1612                         m_freem(*m_head);
1613                         *m_head = NULL;
1614                         return (error);
1615                 }
1616         } else if (error != 0)
1617                 return (error);
1618         if (nsegs == 0) {
1619                 m_freem(*m_head);
1620                 *m_head = NULL;
1621                 return (EIO);
1622         }
1623
1624         /* Check descriptor overrun. */
1625         if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1626                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1627                 return (ENOBUFS);
1628         }
1629
1630         m = *m_head;
1631         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1632                 /* Configure TSO. */
1633                 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1634                         /* Not TSO but IP/TCP checksum offload. */
1635                         cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1636                         /* Clear TSO in order not to set AGE_TD_TSO_HDR. */
1637                         m->m_pkthdr.csum_flags &= ~CSUM_TSO;
1638                 } else {
1639                         /* Request TSO and set MSS. */
1640                         cflags |= AGE_TD_TSO_IPV4;
1641                         cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1642                         cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1643                             AGE_TD_TSO_MSS_SHIFT);
1644                 }
1645                 /* Set IP/TCP header size. */
1646                 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1647                 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1648         } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1649                 /* Configure Tx IP/TCP/UDP checksum offload. */
1650                 cflags |= AGE_TD_CSUM;
1651                 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1652                         cflags |= AGE_TD_TCPCSUM;
1653                 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1654                         cflags |= AGE_TD_UDPCSUM;
1655                 /* Set checksum start offset. */
1656                 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1657                 /* Set checksum insertion position of TCP/UDP. */
1658                 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1659                     AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1660         }
1661
1662         /* Configure VLAN hardware tag insertion. */
1663         if ((m->m_flags & M_VLANTAG) != 0) {
1664                 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1665                 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1666                 cflags |= AGE_TD_INSERT_VLAN_TAG;
1667         }
1668
1669         desc = NULL;
1670         for (i = 0; i < nsegs; i++) {
1671                 desc = &sc->age_rdata.age_tx_ring[prod];
1672                 desc->addr = htole64(txsegs[i].ds_addr);
1673                 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1674                 desc->flags = htole32(cflags);
1675                 sc->age_cdata.age_tx_cnt++;
1676                 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1677         }
1678         /* Update producer index. */
1679         sc->age_cdata.age_tx_prod = prod;
1680
1681         /* Set EOP on the last descriptor. */
1682         prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1683         desc = &sc->age_rdata.age_tx_ring[prod];
1684         desc->flags |= htole32(AGE_TD_EOP);
1685
1686         /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1687         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1688                 desc = &sc->age_rdata.age_tx_ring[si];
1689                 desc->flags |= htole32(AGE_TD_TSO_HDR);
1690         }
1691
1692         /* Swap dmamap of the first and the last. */
1693         txd = &sc->age_cdata.age_txdesc[prod];
1694         map = txd_last->tx_dmamap;
1695         txd_last->tx_dmamap = txd->tx_dmamap;
1696         txd->tx_dmamap = map;
1697         txd->tx_m = m;
1698
1699         /* Sync descriptors. */
1700         bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1701         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1702             sc->age_cdata.age_tx_ring_map,
1703             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1704
1705         return (0);
1706 }
1707
1708 static void
1709 age_tx_task(void *arg, int pending)
1710 {
1711         struct ifnet *ifp;
1712
1713         ifp = (struct ifnet *)arg;
1714         age_start(ifp);
1715 }
1716
1717 static void
1718 age_start(struct ifnet *ifp)
1719 {
1720         struct age_softc *sc;
1721         struct mbuf *m_head;
1722         int enq;
1723
1724         sc = ifp->if_softc;
1725
1726         AGE_LOCK(sc);
1727
1728         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1729             IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) {
1730                 AGE_UNLOCK(sc);
1731                 return;
1732         }
1733
1734         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1735                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1736                 if (m_head == NULL)
1737                         break;
1738                 /*
1739                  * Pack the data into the transmit ring. If we
1740                  * don't have room, set the OACTIVE flag and wait
1741                  * for the NIC to drain the ring.
1742                  */
1743                 if (age_encap(sc, &m_head)) {
1744                         if (m_head == NULL)
1745                                 break;
1746                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1747                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1748                         break;
1749                 }
1750
1751                 enq++;
1752                 /*
1753                  * If there's a BPF listener, bounce a copy of this frame
1754                  * to him.
1755                  */
1756                 ETHER_BPF_MTAP(ifp, m_head);
1757         }
1758
1759         if (enq > 0) {
1760                 /* Update mbox. */
1761                 AGE_COMMIT_MBOX(sc);
1762                 /* Set a timeout in case the chip goes out to lunch. */
1763                 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1764         }
1765
1766         AGE_UNLOCK(sc);
1767 }
1768
1769 static void
1770 age_watchdog(struct age_softc *sc)
1771 {
1772         struct ifnet *ifp;
1773
1774         AGE_LOCK_ASSERT(sc);
1775
1776         if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1777                 return;
1778
1779         ifp = sc->age_ifp;
1780         if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1781                 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1782                 ifp->if_oerrors++;
1783                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1784                 age_init_locked(sc);
1785                 return;
1786         }
1787         if (sc->age_cdata.age_tx_cnt == 0) {
1788                 if_printf(sc->age_ifp,
1789                     "watchdog timeout (missed Tx interrupts) -- recovering\n");
1790                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1791                         taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
1792                 return;
1793         }
1794         if_printf(sc->age_ifp, "watchdog timeout\n");
1795         ifp->if_oerrors++;
1796         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1797         age_init_locked(sc);
1798         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1799                 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
1800 }
1801
1802 static int
1803 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1804 {
1805         struct age_softc *sc;
1806         struct ifreq *ifr;
1807         struct mii_data *mii;
1808         uint32_t reg;
1809         int error, mask;
1810
1811         sc = ifp->if_softc;
1812         ifr = (struct ifreq *)data;
1813         error = 0;
1814         switch (cmd) {
1815         case SIOCSIFMTU:
1816                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1817                         error = EINVAL;
1818                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1819                         AGE_LOCK(sc);
1820                         ifp->if_mtu = ifr->ifr_mtu;
1821                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1822                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1823                                 age_init_locked(sc);
1824                         }
1825                         AGE_UNLOCK(sc);
1826                 }
1827                 break;
1828         case SIOCSIFFLAGS:
1829                 AGE_LOCK(sc);
1830                 if ((ifp->if_flags & IFF_UP) != 0) {
1831                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1832                                 if (((ifp->if_flags ^ sc->age_if_flags)
1833                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1834                                         age_rxfilter(sc);
1835                         } else {
1836                                 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1837                                         age_init_locked(sc);
1838                         }
1839                 } else {
1840                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1841                                 age_stop(sc);
1842                 }
1843                 sc->age_if_flags = ifp->if_flags;
1844                 AGE_UNLOCK(sc);
1845                 break;
1846         case SIOCADDMULTI:
1847         case SIOCDELMULTI:
1848                 AGE_LOCK(sc);
1849                 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1850                         age_rxfilter(sc);
1851                 AGE_UNLOCK(sc);
1852                 break;
1853         case SIOCSIFMEDIA:
1854         case SIOCGIFMEDIA:
1855                 mii = device_get_softc(sc->age_miibus);
1856                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1857                 break;
1858         case SIOCSIFCAP:
1859                 AGE_LOCK(sc);
1860                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1861                 if ((mask & IFCAP_TXCSUM) != 0 &&
1862                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1863                         ifp->if_capenable ^= IFCAP_TXCSUM;
1864                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1865                                 ifp->if_hwassist |= AGE_CSUM_FEATURES;
1866                         else
1867                                 ifp->if_hwassist &= ~AGE_CSUM_FEATURES;
1868                 }
1869                 if ((mask & IFCAP_RXCSUM) != 0 &&
1870                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1871                         ifp->if_capenable ^= IFCAP_RXCSUM;
1872                         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1873                         reg &= ~MAC_CFG_RXCSUM_ENB;
1874                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1875                                 reg |= MAC_CFG_RXCSUM_ENB;
1876                         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1877                 }
1878                 if ((mask & IFCAP_TSO4) != 0 &&
1879                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1880                         ifp->if_capenable ^= IFCAP_TSO4;
1881                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1882                                 ifp->if_hwassist |= CSUM_TSO;
1883                         else
1884                                 ifp->if_hwassist &= ~CSUM_TSO;
1885                 }
1886
1887                 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1888                     (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
1889                         ifp->if_capenable ^= IFCAP_WOL_MCAST;
1890                 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1891                     (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1892                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1893                 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1894                     (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1895                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1896                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1897                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1898                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1899                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1900                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1901                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1902                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1903                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
1904                         age_rxvlan(sc);
1905                 }
1906                 AGE_UNLOCK(sc);
1907                 VLAN_CAPABILITIES(ifp);
1908                 break;
1909         default:
1910                 error = ether_ioctl(ifp, cmd, data);
1911                 break;
1912         }
1913
1914         return (error);
1915 }
1916
1917 static void
1918 age_mac_config(struct age_softc *sc)
1919 {
1920         struct mii_data *mii;
1921         uint32_t reg;
1922
1923         AGE_LOCK_ASSERT(sc);
1924
1925         mii = device_get_softc(sc->age_miibus);
1926         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1927         reg &= ~MAC_CFG_FULL_DUPLEX;
1928         reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1929         reg &= ~MAC_CFG_SPEED_MASK;
1930         /* Reprogram MAC with resolved speed/duplex. */
1931         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1932         case IFM_10_T:
1933         case IFM_100_TX:
1934                 reg |= MAC_CFG_SPEED_10_100;
1935                 break;
1936         case IFM_1000_T:
1937                 reg |= MAC_CFG_SPEED_1000;
1938                 break;
1939         }
1940         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1941                 reg |= MAC_CFG_FULL_DUPLEX;
1942 #ifdef notyet
1943                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1944                         reg |= MAC_CFG_TX_FC;
1945                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1946                         reg |= MAC_CFG_RX_FC;
1947 #endif
1948         }
1949
1950         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1951 }
1952
1953 static void
1954 age_link_task(void *arg, int pending)
1955 {
1956         struct age_softc *sc;
1957         struct mii_data *mii;
1958         struct ifnet *ifp;
1959         uint32_t reg;
1960
1961         sc = (struct age_softc *)arg;
1962
1963         AGE_LOCK(sc);
1964         mii = device_get_softc(sc->age_miibus);
1965         ifp = sc->age_ifp;
1966         if (mii == NULL || ifp == NULL ||
1967             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1968                 AGE_UNLOCK(sc);
1969                 return;
1970         }
1971
1972         sc->age_flags &= ~AGE_FLAG_LINK;
1973         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1974                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1975                 case IFM_10_T:
1976                 case IFM_100_TX:
1977                 case IFM_1000_T:
1978                         sc->age_flags |= AGE_FLAG_LINK;
1979                         break;
1980                 default:
1981                         break;
1982                 }
1983         }
1984
1985         /* Stop Rx/Tx MACs. */
1986         age_stop_rxmac(sc);
1987         age_stop_txmac(sc);
1988
1989         /* Program MACs with resolved speed/duplex/flow-control. */
1990         if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
1991                 age_mac_config(sc);
1992                 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1993                 /* Restart DMA engine and Tx/Rx MAC. */
1994                 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
1995                     DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
1996                 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
1997                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1998         }
1999
2000         AGE_UNLOCK(sc);
2001 }
2002
2003 static void
2004 age_stats_update(struct age_softc *sc)
2005 {
2006         struct age_stats *stat;
2007         struct smb *smb;
2008         struct ifnet *ifp;
2009
2010         AGE_LOCK_ASSERT(sc);
2011
2012         stat = &sc->age_stat;
2013
2014         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2015             sc->age_cdata.age_smb_block_map,
2016             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2017
2018         smb = sc->age_rdata.age_smb_block;
2019         if (smb->updated == 0)
2020                 return;
2021
2022         ifp = sc->age_ifp;
2023         /* Rx stats. */
2024         stat->rx_frames += smb->rx_frames;
2025         stat->rx_bcast_frames += smb->rx_bcast_frames;
2026         stat->rx_mcast_frames += smb->rx_mcast_frames;
2027         stat->rx_pause_frames += smb->rx_pause_frames;
2028         stat->rx_control_frames += smb->rx_control_frames;
2029         stat->rx_crcerrs += smb->rx_crcerrs;
2030         stat->rx_lenerrs += smb->rx_lenerrs;
2031         stat->rx_bytes += smb->rx_bytes;
2032         stat->rx_runts += smb->rx_runts;
2033         stat->rx_fragments += smb->rx_fragments;
2034         stat->rx_pkts_64 += smb->rx_pkts_64;
2035         stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2036         stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2037         stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2038         stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2039         stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2040         stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2041         stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2042         stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2043         stat->rx_desc_oflows += smb->rx_desc_oflows;
2044         stat->rx_alignerrs += smb->rx_alignerrs;
2045         stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2046         stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2047         stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2048
2049         /* Tx stats. */
2050         stat->tx_frames += smb->tx_frames;
2051         stat->tx_bcast_frames += smb->tx_bcast_frames;
2052         stat->tx_mcast_frames += smb->tx_mcast_frames;
2053         stat->tx_pause_frames += smb->tx_pause_frames;
2054         stat->tx_excess_defer += smb->tx_excess_defer;
2055         stat->tx_control_frames += smb->tx_control_frames;
2056         stat->tx_deferred += smb->tx_deferred;
2057         stat->tx_bytes += smb->tx_bytes;
2058         stat->tx_pkts_64 += smb->tx_pkts_64;
2059         stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2060         stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2061         stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2062         stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2063         stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2064         stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2065         stat->tx_single_colls += smb->tx_single_colls;
2066         stat->tx_multi_colls += smb->tx_multi_colls;
2067         stat->tx_late_colls += smb->tx_late_colls;
2068         stat->tx_excess_colls += smb->tx_excess_colls;
2069         stat->tx_underrun += smb->tx_underrun;
2070         stat->tx_desc_underrun += smb->tx_desc_underrun;
2071         stat->tx_lenerrs += smb->tx_lenerrs;
2072         stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2073         stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2074         stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2075
2076         /* Update counters in ifnet. */
2077         ifp->if_opackets += smb->tx_frames;
2078
2079         ifp->if_collisions += smb->tx_single_colls +
2080             smb->tx_multi_colls + smb->tx_late_colls +
2081             smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
2082
2083         ifp->if_oerrors += smb->tx_excess_colls +
2084             smb->tx_late_colls + smb->tx_underrun +
2085             smb->tx_pkts_truncated;
2086
2087         ifp->if_ipackets += smb->rx_frames;
2088
2089         ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2090             smb->rx_runts + smb->rx_pkts_truncated +
2091             smb->rx_fifo_oflows + smb->rx_desc_oflows +
2092             smb->rx_alignerrs;
2093
2094         /* Update done, clear. */
2095         smb->updated = 0;
2096
2097         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2098             sc->age_cdata.age_smb_block_map,
2099             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2100 }
2101
2102 static int
2103 age_intr(void *arg)
2104 {
2105         struct age_softc *sc;
2106         uint32_t status;
2107
2108         sc = (struct age_softc *)arg;
2109
2110         status = CSR_READ_4(sc, AGE_INTR_STATUS);
2111         if (status == 0 || (status & AGE_INTRS) == 0)
2112                 return (FILTER_STRAY);
2113         /* Disable interrupts. */
2114         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2115         taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2116
2117         return (FILTER_HANDLED);
2118 }
2119
2120 static void
2121 age_int_task(void *arg, int pending)
2122 {
2123         struct age_softc *sc;
2124         struct ifnet *ifp;
2125         struct cmb *cmb;
2126         uint32_t status;
2127
2128         sc = (struct age_softc *)arg;
2129
2130         AGE_LOCK(sc);
2131
2132         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2133             sc->age_cdata.age_cmb_block_map,
2134             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2135         cmb = sc->age_rdata.age_cmb_block;
2136         status = le32toh(cmb->intr_status);
2137         if (sc->age_morework != 0)
2138                 status |= INTR_CMB_RX;
2139         if ((status & AGE_INTRS) == 0)
2140                 goto done;
2141
2142         sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2143             TPD_CONS_SHIFT;
2144         sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2145             RRD_PROD_SHIFT;
2146         /* Let hardware know CMB was served. */
2147         cmb->intr_status = 0;
2148         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2149             sc->age_cdata.age_cmb_block_map,
2150             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2151
2152 #if 0
2153         printf("INTR: 0x%08x\n", status);
2154         status &= ~INTR_DIS_DMA;
2155         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2156 #endif
2157         ifp = sc->age_ifp;
2158         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2159                 if ((status & INTR_CMB_RX) != 0)
2160                         sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2161                             sc->age_process_limit);
2162                 if ((status & INTR_CMB_TX) != 0)
2163                         age_txintr(sc, sc->age_tpd_cons);
2164                 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2165                         if ((status & INTR_DMA_RD_TO_RST) != 0)
2166                                 device_printf(sc->age_dev,
2167                                     "DMA read error! -- resetting\n");
2168                         if ((status & INTR_DMA_WR_TO_RST) != 0)
2169                                 device_printf(sc->age_dev,
2170                                     "DMA write error! -- resetting\n");
2171                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2172                         age_init_locked(sc);
2173                 }
2174                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2175                         taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
2176                 if ((status & INTR_SMB) != 0)
2177                         age_stats_update(sc);
2178         }
2179
2180         /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2181         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2182             sc->age_cdata.age_cmb_block_map,
2183             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2184         status = le32toh(cmb->intr_status);
2185         if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2186                 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2187                 AGE_UNLOCK(sc);
2188                 return;
2189         }
2190
2191 done:
2192         /* Re-enable interrupts. */
2193         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2194         AGE_UNLOCK(sc);
2195 }
2196
2197 static void
2198 age_txintr(struct age_softc *sc, int tpd_cons)
2199 {
2200         struct ifnet *ifp;
2201         struct age_txdesc *txd;
2202         int cons, prog;
2203
2204         AGE_LOCK_ASSERT(sc);
2205
2206         ifp = sc->age_ifp;
2207
2208         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2209             sc->age_cdata.age_tx_ring_map,
2210             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2211
2212         /*
2213          * Go through our Tx list and free mbufs for those
2214          * frames which have been transmitted.
2215          */
2216         cons = sc->age_cdata.age_tx_cons;
2217         for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2218                 if (sc->age_cdata.age_tx_cnt <= 0)
2219                         break;
2220                 prog++;
2221                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2222                 sc->age_cdata.age_tx_cnt--;
2223                 txd = &sc->age_cdata.age_txdesc[cons];
2224                 /*
2225                  * Clear Tx descriptors, it's not required but would
2226                  * help debugging in case of Tx issues.
2227                  */
2228                 txd->tx_desc->addr = 0;
2229                 txd->tx_desc->len = 0;
2230                 txd->tx_desc->flags = 0;
2231
2232                 if (txd->tx_m == NULL)
2233                         continue;
2234                 /* Reclaim transmitted mbufs. */
2235                 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2236                     BUS_DMASYNC_POSTWRITE);
2237                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2238                 m_freem(txd->tx_m);
2239                 txd->tx_m = NULL;
2240         }
2241
2242         if (prog > 0) {
2243                 sc->age_cdata.age_tx_cons = cons;
2244
2245                 /*
2246                  * Unarm watchdog timer only when there are no pending
2247                  * Tx descriptors in queue.
2248                  */
2249                 if (sc->age_cdata.age_tx_cnt == 0)
2250                         sc->age_watchdog_timer = 0;
2251                 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2252                     sc->age_cdata.age_tx_ring_map,
2253                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2254         }
2255 }
2256
2257 /* Receive a frame. */
2258 static void
2259 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2260 {
2261         struct age_rxdesc *rxd;
2262         struct rx_desc *desc;
2263         struct ifnet *ifp;
2264         struct mbuf *mp, *m;
2265         uint32_t status, index, vtag;
2266         int count, nsegs, pktlen;
2267         int rx_cons;
2268
2269         AGE_LOCK_ASSERT(sc);
2270
2271         ifp = sc->age_ifp;
2272         status = le32toh(rxrd->flags);
2273         index = le32toh(rxrd->index);
2274         rx_cons = AGE_RX_CONS(index);
2275         nsegs = AGE_RX_NSEGS(index);
2276
2277         sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2278         if ((status & AGE_RRD_ERROR) != 0 &&
2279             (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2280             AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) {
2281                 /*
2282                  * We want to pass the following frames to upper
2283                  * layer regardless of error status of Rx return
2284                  * ring.
2285                  *
2286                  *  o IP/TCP/UDP checksum is bad.
2287                  *  o frame length and protocol specific length
2288                  *     does not match.
2289                  */
2290                 sc->age_cdata.age_rx_cons += nsegs;
2291                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2292                 return;
2293         }
2294
2295         pktlen = 0;
2296         for (count = 0; count < nsegs; count++,
2297             AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2298                 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2299                 mp = rxd->rx_m;
2300                 desc = rxd->rx_desc;
2301                 /* Add a new receive buffer to the ring. */
2302                 if (age_newbuf(sc, rxd) != 0) {
2303                         ifp->if_iqdrops++;
2304                         /* Reuse Rx buffers. */
2305                         if (sc->age_cdata.age_rxhead != NULL) {
2306                                 m_freem(sc->age_cdata.age_rxhead);
2307                                 AGE_RXCHAIN_RESET(sc);
2308                         }
2309                         break;
2310                 }
2311
2312                 /* The length of the first mbuf is computed last. */
2313                 if (count != 0) {
2314                         mp->m_len = AGE_RX_BYTES(le32toh(desc->len));
2315                         pktlen += mp->m_len;
2316                 }
2317
2318                 /* Chain received mbufs. */
2319                 if (sc->age_cdata.age_rxhead == NULL) {
2320                         sc->age_cdata.age_rxhead = mp;
2321                         sc->age_cdata.age_rxtail = mp;
2322                 } else {
2323                         mp->m_flags &= ~M_PKTHDR;
2324                         sc->age_cdata.age_rxprev_tail =
2325                             sc->age_cdata.age_rxtail;
2326                         sc->age_cdata.age_rxtail->m_next = mp;
2327                         sc->age_cdata.age_rxtail = mp;
2328                 }
2329
2330                 if (count == nsegs - 1) {
2331                         /*
2332                          * It seems that L1 controller has no way
2333                          * to tell hardware to strip CRC bytes.
2334                          */
2335                         sc->age_cdata.age_rxlen -= ETHER_CRC_LEN;
2336                         if (nsegs > 1) {
2337                                 /* Remove the CRC bytes in chained mbufs. */
2338                                 pktlen -= ETHER_CRC_LEN;
2339                                 if (mp->m_len <= ETHER_CRC_LEN) {
2340                                         sc->age_cdata.age_rxtail =
2341                                             sc->age_cdata.age_rxprev_tail;
2342                                         sc->age_cdata.age_rxtail->m_len -=
2343                                             (ETHER_CRC_LEN - mp->m_len);
2344                                         sc->age_cdata.age_rxtail->m_next = NULL;
2345                                         m_freem(mp);
2346                                 } else {
2347                                         mp->m_len -= ETHER_CRC_LEN;
2348                                 }
2349                         }
2350
2351                         m = sc->age_cdata.age_rxhead;
2352                         m->m_flags |= M_PKTHDR;
2353                         m->m_pkthdr.rcvif = ifp;
2354                         m->m_pkthdr.len = sc->age_cdata.age_rxlen;
2355                         /* Set the first mbuf length. */
2356                         m->m_len = sc->age_cdata.age_rxlen - pktlen;
2357
2358                         /*
2359                          * Set checksum information.
2360                          * It seems that L1 controller can compute partial
2361                          * checksum. The partial checksum value can be used
2362                          * to accelerate checksum computation for fragmented
2363                          * TCP/UDP packets. Upper network stack already
2364                          * takes advantage of the partial checksum value in
2365                          * IP reassembly stage. But I'm not sure the
2366                          * correctness of the partial hardware checksum
2367                          * assistance due to lack of data sheet. If it is
2368                          * proven to work on L1 I'll enable it.
2369                          */
2370                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2371                             (status & AGE_RRD_IPV4) != 0) {
2372                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2373                                 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2374                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2375                                 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2376                                     (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2377                                         m->m_pkthdr.csum_flags |=
2378                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2379                                         m->m_pkthdr.csum_data = 0xffff;
2380                                 }
2381                                 /*
2382                                  * Don't mark bad checksum for TCP/UDP frames
2383                                  * as fragmented frames may always have set
2384                                  * bad checksummed bit of descriptor status.
2385                                  */
2386                         }
2387
2388                         /* Check for VLAN tagged frames. */
2389                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2390                             (status & AGE_RRD_VLAN) != 0) {
2391                                 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2392                                 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2393                                 m->m_flags |= M_VLANTAG;
2394                         }
2395
2396                         /* Pass it on. */
2397                         AGE_UNLOCK(sc);
2398                         (*ifp->if_input)(ifp, m);
2399                         AGE_LOCK(sc);
2400
2401                         /* Reset mbuf chains. */
2402                         AGE_RXCHAIN_RESET(sc);
2403                 }
2404         }
2405
2406         if (count != nsegs) {
2407                 sc->age_cdata.age_rx_cons += nsegs;
2408                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2409         } else
2410                 sc->age_cdata.age_rx_cons = rx_cons;
2411 }
2412
2413 static int
2414 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2415 {
2416         struct rx_rdesc *rxrd;
2417         int rr_cons, nsegs, pktlen, prog;
2418
2419         AGE_LOCK_ASSERT(sc);
2420
2421         rr_cons = sc->age_cdata.age_rr_cons;
2422         if (rr_cons == rr_prod)
2423                 return (0);
2424
2425         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2426             sc->age_cdata.age_rr_ring_map,
2427             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2428
2429         for (prog = 0; rr_cons != rr_prod; prog++) {
2430                 if (count <= 0)
2431                         break;
2432                 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2433                 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2434                 if (nsegs == 0)
2435                         break;
2436                 /*
2437                  * Check number of segments against received bytes.
2438                  * Non-matching value would indicate that hardware
2439                  * is still trying to update Rx return descriptors.
2440                  * I'm not sure whether this check is really needed.
2441                  */
2442                 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2443                 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) /
2444                     (MCLBYTES - ETHER_ALIGN)))
2445                         break;
2446
2447                 prog++;
2448                 /* Received a frame. */
2449                 age_rxeof(sc, rxrd);
2450                 /* Clear return ring. */
2451                 rxrd->index = 0;
2452                 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2453         }
2454
2455         if (prog > 0) {
2456                 /* Update the consumer index. */
2457                 sc->age_cdata.age_rr_cons = rr_cons;
2458
2459                 /* Sync descriptors. */
2460                 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2461                     sc->age_cdata.age_rr_ring_map,
2462                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2463
2464                 /* Notify hardware availability of new Rx buffers. */
2465                 AGE_COMMIT_MBOX(sc);
2466         }
2467
2468         return (count > 0 ? 0 : EAGAIN);
2469 }
2470
2471 static void
2472 age_tick(void *arg)
2473 {
2474         struct age_softc *sc;
2475         struct mii_data *mii;
2476
2477         sc = (struct age_softc *)arg;
2478
2479         AGE_LOCK_ASSERT(sc);
2480
2481         mii = device_get_softc(sc->age_miibus);
2482         mii_tick(mii);
2483         age_watchdog(sc);
2484         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2485 }
2486
2487 static void
2488 age_reset(struct age_softc *sc)
2489 {
2490         uint32_t reg;
2491         int i;
2492
2493         CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2494         CSR_READ_4(sc, AGE_MASTER_CFG);
2495         DELAY(1000);
2496         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2497                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2498                         break;
2499                 DELAY(10);
2500         }
2501
2502         if (i == 0)
2503                 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2504         /* Initialize PCIe module. From Linux. */
2505         CSR_WRITE_4(sc, 0x12FC, 0x6500);
2506         CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2507 }
2508
2509 static void
2510 age_init(void *xsc)
2511 {
2512         struct age_softc *sc;
2513
2514         sc = (struct age_softc *)xsc;
2515         AGE_LOCK(sc);
2516         age_init_locked(sc);
2517         AGE_UNLOCK(sc);
2518 }
2519
2520 static void
2521 age_init_locked(struct age_softc *sc)
2522 {
2523         struct ifnet *ifp;
2524         struct mii_data *mii;
2525         uint8_t eaddr[ETHER_ADDR_LEN];
2526         bus_addr_t paddr;
2527         uint32_t reg, fsize;
2528         uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2529         int error;
2530
2531         AGE_LOCK_ASSERT(sc);
2532
2533         ifp = sc->age_ifp;
2534         mii = device_get_softc(sc->age_miibus);
2535
2536         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2537                 return;
2538
2539         /*
2540          * Cancel any pending I/O.
2541          */
2542         age_stop(sc);
2543
2544         /*
2545          * Reset the chip to a known state.
2546          */
2547         age_reset(sc);
2548
2549         /* Initialize descriptors. */
2550         error = age_init_rx_ring(sc);
2551         if (error != 0) {
2552                 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2553                 age_stop(sc);
2554                 return;
2555         }
2556         age_init_rr_ring(sc);
2557         age_init_tx_ring(sc);
2558         age_init_cmb_block(sc);
2559         age_init_smb_block(sc);
2560
2561         /* Reprogram the station address. */
2562         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2563         CSR_WRITE_4(sc, AGE_PAR0,
2564             eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2565         CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2566
2567         /* Set descriptor base addresses. */
2568         paddr = sc->age_rdata.age_tx_ring_paddr;
2569         CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2570         paddr = sc->age_rdata.age_rx_ring_paddr;
2571         CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2572         paddr = sc->age_rdata.age_rr_ring_paddr;
2573         CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2574         paddr = sc->age_rdata.age_tx_ring_paddr;
2575         CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2576         paddr = sc->age_rdata.age_cmb_block_paddr;
2577         CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2578         paddr = sc->age_rdata.age_smb_block_paddr;
2579         CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2580         /* Set Rx/Rx return descriptor counter. */
2581         CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2582             ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2583             DESC_RRD_CNT_MASK) |
2584             ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2585         /* Set Tx descriptor counter. */
2586         CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2587             (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2588
2589         /* Tell hardware that we're ready to load descriptors. */
2590         CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2591
2592         /*
2593          * Initialize mailbox register.
2594          * Updated producer/consumer index information is exchanged
2595          * through this mailbox register. However Tx producer and
2596          * Rx return consumer/Rx producer are all shared such that
2597          * it's hard to separate code path between Tx and Rx without
2598          * locking. If L1 hardware have a separate mail box register
2599          * for Tx and Rx consumer/producer management we could have
2600          * indepent Tx/Rx handler which in turn Rx handler could have
2601          * been run without any locking.
2602          */
2603         AGE_COMMIT_MBOX(sc);
2604
2605         /* Configure IPG/IFG parameters. */
2606         CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2607             ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2608             ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2609             ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2610             ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2611
2612         /* Set parameters for half-duplex media. */
2613         CSR_WRITE_4(sc, AGE_HDPX_CFG,
2614             ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2615             HDPX_CFG_LCOL_MASK) |
2616             ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2617             HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2618             ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2619             HDPX_CFG_ABEBT_MASK) |
2620             ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2621             HDPX_CFG_JAMIPG_MASK));
2622
2623         /* Configure interrupt moderation timer. */
2624         CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2625         reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2626         reg &= ~MASTER_MTIMER_ENB;
2627         if (AGE_USECS(sc->age_int_mod) == 0)
2628                 reg &= ~MASTER_ITIMER_ENB;
2629         else
2630                 reg |= MASTER_ITIMER_ENB;
2631         CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2632         if (bootverbose)
2633                 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2634                     sc->age_int_mod);
2635         CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2636
2637         /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2638         if (ifp->if_mtu < ETHERMTU)
2639                 sc->age_max_frame_size = ETHERMTU;
2640         else
2641                 sc->age_max_frame_size = ifp->if_mtu;
2642         sc->age_max_frame_size += ETHER_HDR_LEN +
2643             sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2644         CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2645         /* Configure jumbo frame. */
2646         fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2647         CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2648             (((fsize / sizeof(uint64_t)) <<
2649             RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2650             ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2651             RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2652             ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2653             RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2654
2655         /* Configure flow-control parameters. From Linux. */
2656         if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2657                 /*
2658                  * Magic workaround for old-L1.
2659                  * Don't know which hw revision requires this magic.
2660                  */
2661                 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2662                 /*
2663                  * Another magic workaround for flow-control mode
2664                  * change. From Linux.
2665                  */
2666                 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2667         }
2668         /*
2669          * TODO
2670          *  Should understand pause parameter relationships between FIFO
2671          *  size and number of Rx descriptors and Rx return descriptors.
2672          *
2673          *  Magic parameters came from Linux.
2674          */
2675         switch (sc->age_chip_rev) {
2676         case 0x8001:
2677         case 0x9001:
2678         case 0x9002:
2679         case 0x9003:
2680                 rxf_hi = AGE_RX_RING_CNT / 16;
2681                 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2682                 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2683                 rrd_lo = AGE_RR_RING_CNT / 16;
2684                 break;
2685         default:
2686                 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2687                 rxf_lo = reg / 16;
2688                 if (rxf_lo < 192)
2689                         rxf_lo = 192;
2690                 rxf_hi = (reg * 7) / 8;
2691                 if (rxf_hi < rxf_lo)
2692                         rxf_hi = rxf_lo + 16;
2693                 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2694                 rrd_lo = reg / 8;
2695                 rrd_hi = (reg * 7) / 8;
2696                 if (rrd_lo < 2)
2697                         rrd_lo = 2;
2698                 if (rrd_hi < rrd_lo)
2699                         rrd_hi = rrd_lo + 3;
2700                 break;
2701         }
2702         CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2703             ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2704             RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2705             ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2706             RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2707         CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2708             ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2709             RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2710             ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2711             RXQ_RRD_PAUSE_THRESH_HI_MASK));
2712
2713         /* Configure RxQ. */
2714         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2715             ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2716             RXQ_CFG_RD_BURST_MASK) |
2717             ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2718             RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2719             ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2720             RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2721             RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2722
2723         /* Configure TxQ. */
2724         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2725             ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2726             TXQ_CFG_TPD_BURST_MASK) |
2727             ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2728             TXQ_CFG_TX_FIFO_BURST_MASK) |
2729             ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2730             TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2731             TXQ_CFG_ENB);
2732
2733         CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2734             (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2735             TX_JUMBO_TPD_TH_MASK) |
2736             ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2737             TX_JUMBO_TPD_IPG_MASK));
2738         /* Configure DMA parameters. */
2739         CSR_WRITE_4(sc, AGE_DMA_CFG,
2740             DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2741             sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2742             sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2743
2744         /* Configure CMB DMA write threshold. */
2745         CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2746             ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2747             CMB_WR_THRESH_RRD_MASK) |
2748             ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2749             CMB_WR_THRESH_TPD_MASK));
2750
2751         /* Set CMB/SMB timer and enable them. */
2752         CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2753             ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2754             ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2755         /* Request SMB updates for every seconds. */
2756         CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2757         CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2758
2759         /*
2760          * Disable all WOL bits as WOL can interfere normal Rx
2761          * operation.
2762          */
2763         CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2764
2765         /*
2766          * Configure Tx/Rx MACs.
2767          *  - Auto-padding for short frames.
2768          *  - Enable CRC generation.
2769          *  Start with full-duplex/1000Mbps media. Actual reconfiguration
2770          *  of MAC is followed after link establishment.
2771          */
2772         CSR_WRITE_4(sc, AGE_MAC_CFG,
2773             MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2774             MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2775             ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2776             MAC_CFG_PREAMBLE_MASK));
2777         /* Set up the receive filter. */
2778         age_rxfilter(sc);
2779         age_rxvlan(sc);
2780
2781         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2782         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2783                 reg |= MAC_CFG_RXCSUM_ENB;
2784
2785         /* Ack all pending interrupts and clear it. */
2786         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2787         CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2788
2789         /* Finally enable Tx/Rx MAC. */
2790         CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2791
2792         sc->age_flags &= ~AGE_FLAG_LINK;
2793         /* Switch to the current media. */
2794         mii_mediachg(mii);
2795
2796         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2797
2798         ifp->if_drv_flags |= IFF_DRV_RUNNING;
2799         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2800 }
2801
2802 static void
2803 age_stop(struct age_softc *sc)
2804 {
2805         struct ifnet *ifp;
2806         struct age_txdesc *txd;
2807         struct age_rxdesc *rxd;
2808         uint32_t reg;
2809         int i;
2810
2811         AGE_LOCK_ASSERT(sc);
2812         /*
2813          * Mark the interface down and cancel the watchdog timer.
2814          */
2815         ifp = sc->age_ifp;
2816         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2817         sc->age_flags &= ~AGE_FLAG_LINK;
2818         callout_stop(&sc->age_tick_ch);
2819         sc->age_watchdog_timer = 0;
2820
2821         /*
2822          * Disable interrupts.
2823          */
2824         CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2825         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2826         /* Stop CMB/SMB updates. */
2827         CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2828         /* Stop Rx/Tx MAC. */
2829         age_stop_rxmac(sc);
2830         age_stop_txmac(sc);
2831         /* Stop DMA. */
2832         CSR_WRITE_4(sc, AGE_DMA_CFG,
2833             CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2834         /* Stop TxQ/RxQ. */
2835         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2836             CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2837         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2838             CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2839         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2840                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2841                         break;
2842                 DELAY(10);
2843         }
2844         if (i == 0)
2845                 device_printf(sc->age_dev,
2846                     "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2847
2848          /* Reclaim Rx buffers that have been processed. */
2849         if (sc->age_cdata.age_rxhead != NULL)
2850                 m_freem(sc->age_cdata.age_rxhead);
2851         AGE_RXCHAIN_RESET(sc);
2852         /*
2853          * Free RX and TX mbufs still in the queues.
2854          */
2855         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2856                 rxd = &sc->age_cdata.age_rxdesc[i];
2857                 if (rxd->rx_m != NULL) {
2858                         bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2859                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2860                         bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2861                             rxd->rx_dmamap);
2862                         m_freem(rxd->rx_m);
2863                         rxd->rx_m = NULL;
2864                 }
2865         }
2866         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2867                 txd = &sc->age_cdata.age_txdesc[i];
2868                 if (txd->tx_m != NULL) {
2869                         bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2870                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2871                         bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2872                             txd->tx_dmamap);
2873                         m_freem(txd->tx_m);
2874                         txd->tx_m = NULL;
2875                 }
2876         }
2877 }
2878
2879 static void
2880 age_stop_txmac(struct age_softc *sc)
2881 {
2882         uint32_t reg;
2883         int i;
2884
2885         AGE_LOCK_ASSERT(sc);
2886
2887         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2888         if ((reg & MAC_CFG_TX_ENB) != 0) {
2889                 reg &= ~MAC_CFG_TX_ENB;
2890                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2891         }
2892         /* Stop Tx DMA engine. */
2893         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2894         if ((reg & DMA_CFG_RD_ENB) != 0) {
2895                 reg &= ~DMA_CFG_RD_ENB;
2896                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2897         }
2898         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2899                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2900                     (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2901                         break;
2902                 DELAY(10);
2903         }
2904         if (i == 0)
2905                 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2906 }
2907
2908 static void
2909 age_stop_rxmac(struct age_softc *sc)
2910 {
2911         uint32_t reg;
2912         int i;
2913
2914         AGE_LOCK_ASSERT(sc);
2915
2916         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2917         if ((reg & MAC_CFG_RX_ENB) != 0) {
2918                 reg &= ~MAC_CFG_RX_ENB;
2919                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2920         }
2921         /* Stop Rx DMA engine. */
2922         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2923         if ((reg & DMA_CFG_WR_ENB) != 0) {
2924                 reg &= ~DMA_CFG_WR_ENB;
2925                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2926         }
2927         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2928                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2929                     (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2930                         break;
2931                 DELAY(10);
2932         }
2933         if (i == 0)
2934                 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2935 }
2936
2937 static void
2938 age_init_tx_ring(struct age_softc *sc)
2939 {
2940         struct age_ring_data *rd;
2941         struct age_txdesc *txd;
2942         int i;
2943
2944         AGE_LOCK_ASSERT(sc);
2945
2946         sc->age_cdata.age_tx_prod = 0;
2947         sc->age_cdata.age_tx_cons = 0;
2948         sc->age_cdata.age_tx_cnt = 0;
2949
2950         rd = &sc->age_rdata;
2951         bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2952         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2953                 txd = &sc->age_cdata.age_txdesc[i];
2954                 txd->tx_desc = &rd->age_tx_ring[i];
2955                 txd->tx_m = NULL;
2956         }
2957
2958         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2959             sc->age_cdata.age_tx_ring_map,
2960             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2961 }
2962
2963 static int
2964 age_init_rx_ring(struct age_softc *sc)
2965 {
2966         struct age_ring_data *rd;
2967         struct age_rxdesc *rxd;
2968         int i;
2969
2970         AGE_LOCK_ASSERT(sc);
2971
2972         sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
2973         sc->age_morework = 0;
2974         rd = &sc->age_rdata;
2975         bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
2976         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2977                 rxd = &sc->age_cdata.age_rxdesc[i];
2978                 rxd->rx_m = NULL;
2979                 rxd->rx_desc = &rd->age_rx_ring[i];
2980                 if (age_newbuf(sc, rxd) != 0)
2981                         return (ENOBUFS);
2982         }
2983
2984         bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2985             sc->age_cdata.age_rx_ring_map,
2986             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2987
2988         return (0);
2989 }
2990
2991 static void
2992 age_init_rr_ring(struct age_softc *sc)
2993 {
2994         struct age_ring_data *rd;
2995
2996         AGE_LOCK_ASSERT(sc);
2997
2998         sc->age_cdata.age_rr_cons = 0;
2999         AGE_RXCHAIN_RESET(sc);
3000
3001         rd = &sc->age_rdata;
3002         bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3003         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3004             sc->age_cdata.age_rr_ring_map,
3005             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3006 }
3007
3008 static void
3009 age_init_cmb_block(struct age_softc *sc)
3010 {
3011         struct age_ring_data *rd;
3012
3013         AGE_LOCK_ASSERT(sc);
3014
3015         rd = &sc->age_rdata;
3016         bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3017         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3018             sc->age_cdata.age_cmb_block_map,
3019             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3020 }
3021
3022 static void
3023 age_init_smb_block(struct age_softc *sc)
3024 {
3025         struct age_ring_data *rd;
3026
3027         AGE_LOCK_ASSERT(sc);
3028
3029         rd = &sc->age_rdata;
3030         bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3031         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3032             sc->age_cdata.age_smb_block_map,
3033             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3034 }
3035
3036 static int
3037 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3038 {
3039         struct rx_desc *desc;
3040         struct mbuf *m;
3041         bus_dma_segment_t segs[1];
3042         bus_dmamap_t map;
3043         int nsegs;
3044
3045         AGE_LOCK_ASSERT(sc);
3046
3047         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3048         if (m == NULL)
3049                 return (ENOBUFS);
3050         m->m_len = m->m_pkthdr.len = MCLBYTES;
3051         m_adj(m, ETHER_ALIGN);
3052
3053         if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3054             sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3055                 m_freem(m);
3056                 return (ENOBUFS);
3057         }
3058         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3059
3060         if (rxd->rx_m != NULL) {
3061                 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3062                     BUS_DMASYNC_POSTREAD);
3063                 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3064         }
3065         map = rxd->rx_dmamap;
3066         rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3067         sc->age_cdata.age_rx_sparemap = map;
3068         bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3069             BUS_DMASYNC_PREREAD);
3070         rxd->rx_m = m;
3071
3072         desc = rxd->rx_desc;
3073         desc->addr = htole64(segs[0].ds_addr);
3074         desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3075             AGE_RD_LEN_SHIFT);
3076         return (0);
3077 }
3078
3079 static void
3080 age_rxvlan(struct age_softc *sc)
3081 {
3082         struct ifnet *ifp;
3083         uint32_t reg;
3084
3085         AGE_LOCK_ASSERT(sc);
3086
3087         ifp = sc->age_ifp;
3088         reg = CSR_READ_4(sc, AGE_MAC_CFG);
3089         reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3090         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3091                 reg |= MAC_CFG_VLAN_TAG_STRIP;
3092         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3093 }
3094
3095 static void
3096 age_rxfilter(struct age_softc *sc)
3097 {
3098         struct ifnet *ifp;
3099         struct ifmultiaddr *ifma;
3100         uint32_t crc;
3101         uint32_t mchash[2];
3102         uint32_t rxcfg;
3103
3104         AGE_LOCK_ASSERT(sc);
3105
3106         ifp = sc->age_ifp;
3107
3108         rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3109         rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3110         if ((ifp->if_flags & IFF_BROADCAST) != 0)
3111                 rxcfg |= MAC_CFG_BCAST;
3112         if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3113                 if ((ifp->if_flags & IFF_PROMISC) != 0)
3114                         rxcfg |= MAC_CFG_PROMISC;
3115                 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3116                         rxcfg |= MAC_CFG_ALLMULTI;
3117                 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3118                 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3119                 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3120                 return;
3121         }
3122
3123         /* Program new filter. */
3124         bzero(mchash, sizeof(mchash));
3125
3126         if_maddr_rlock(ifp);
3127         TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) {
3128                 if (ifma->ifma_addr->sa_family != AF_LINK)
3129                         continue;
3130                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3131                     ifma->ifma_addr), ETHER_ADDR_LEN);
3132                 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3133         }
3134         if_maddr_runlock(ifp);
3135
3136         CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3137         CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3138         CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3139 }
3140
3141 static int
3142 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3143 {
3144         struct age_softc *sc;
3145         struct age_stats *stats;
3146         int error, result;
3147
3148         result = -1;
3149         error = sysctl_handle_int(oidp, &result, 0, req);
3150
3151         if (error != 0 || req->newptr == NULL)
3152                 return (error);
3153
3154         if (result != 1)
3155                 return (error);
3156
3157         sc = (struct age_softc *)arg1;
3158         stats = &sc->age_stat;
3159         printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3160         printf("Transmit good frames : %ju\n",
3161             (uintmax_t)stats->tx_frames);
3162         printf("Transmit good broadcast frames : %ju\n",
3163             (uintmax_t)stats->tx_bcast_frames);
3164         printf("Transmit good multicast frames : %ju\n",
3165             (uintmax_t)stats->tx_mcast_frames);
3166         printf("Transmit pause control frames : %u\n",
3167             stats->tx_pause_frames);
3168         printf("Transmit control frames : %u\n",
3169             stats->tx_control_frames);
3170         printf("Transmit frames with excessive deferrals : %u\n",
3171             stats->tx_excess_defer);
3172         printf("Transmit deferrals : %u\n",
3173             stats->tx_deferred);
3174         printf("Transmit good octets : %ju\n",
3175             (uintmax_t)stats->tx_bytes);
3176         printf("Transmit good broadcast octets : %ju\n",
3177             (uintmax_t)stats->tx_bcast_bytes);
3178         printf("Transmit good multicast octets : %ju\n",
3179             (uintmax_t)stats->tx_mcast_bytes);
3180         printf("Transmit frames 64 bytes : %ju\n",
3181             (uintmax_t)stats->tx_pkts_64);
3182         printf("Transmit frames 65 to 127 bytes : %ju\n",
3183             (uintmax_t)stats->tx_pkts_65_127);
3184         printf("Transmit frames 128 to 255 bytes : %ju\n",
3185             (uintmax_t)stats->tx_pkts_128_255);
3186         printf("Transmit frames 256 to 511 bytes : %ju\n",
3187             (uintmax_t)stats->tx_pkts_256_511);
3188         printf("Transmit frames 512 to 1024 bytes : %ju\n",
3189             (uintmax_t)stats->tx_pkts_512_1023);
3190         printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3191             (uintmax_t)stats->tx_pkts_1024_1518);
3192         printf("Transmit frames 1519 to MTU bytes : %ju\n",
3193             (uintmax_t)stats->tx_pkts_1519_max);
3194         printf("Transmit single collisions : %u\n",
3195             stats->tx_single_colls);
3196         printf("Transmit multiple collisions : %u\n",
3197             stats->tx_multi_colls);
3198         printf("Transmit late collisions : %u\n",
3199             stats->tx_late_colls);
3200         printf("Transmit abort due to excessive collisions : %u\n",
3201             stats->tx_excess_colls);
3202         printf("Transmit underruns due to FIFO underruns : %u\n",
3203             stats->tx_underrun);
3204         printf("Transmit descriptor write-back errors : %u\n",
3205             stats->tx_desc_underrun);
3206         printf("Transmit frames with length mismatched frame size : %u\n",
3207             stats->tx_lenerrs);
3208         printf("Transmit frames with truncated due to MTU size : %u\n",
3209             stats->tx_lenerrs);
3210
3211         printf("Receive good frames : %ju\n",
3212             (uintmax_t)stats->rx_frames);
3213         printf("Receive good broadcast frames : %ju\n",
3214             (uintmax_t)stats->rx_bcast_frames);
3215         printf("Receive good multicast frames : %ju\n",
3216             (uintmax_t)stats->rx_mcast_frames);
3217         printf("Receive pause control frames : %u\n",
3218             stats->rx_pause_frames);
3219         printf("Receive control frames : %u\n",
3220             stats->rx_control_frames);
3221         printf("Receive CRC errors : %u\n",
3222             stats->rx_crcerrs);
3223         printf("Receive frames with length errors : %u\n",
3224             stats->rx_lenerrs);
3225         printf("Receive good octets : %ju\n",
3226             (uintmax_t)stats->rx_bytes);
3227         printf("Receive good broadcast octets : %ju\n",
3228             (uintmax_t)stats->rx_bcast_bytes);
3229         printf("Receive good multicast octets : %ju\n",
3230             (uintmax_t)stats->rx_mcast_bytes);
3231         printf("Receive frames too short : %u\n",
3232             stats->rx_runts);
3233         printf("Receive fragmented frames : %ju\n",
3234             (uintmax_t)stats->rx_fragments);
3235         printf("Receive frames 64 bytes : %ju\n",
3236             (uintmax_t)stats->rx_pkts_64);
3237         printf("Receive frames 65 to 127 bytes : %ju\n",
3238             (uintmax_t)stats->rx_pkts_65_127);
3239         printf("Receive frames 128 to 255 bytes : %ju\n",
3240             (uintmax_t)stats->rx_pkts_128_255);
3241         printf("Receive frames 256 to 511 bytes : %ju\n",
3242             (uintmax_t)stats->rx_pkts_256_511);
3243         printf("Receive frames 512 to 1024 bytes : %ju\n",
3244             (uintmax_t)stats->rx_pkts_512_1023);
3245         printf("Receive frames 1024 to 1518 bytes : %ju\n",
3246             (uintmax_t)stats->rx_pkts_1024_1518);
3247         printf("Receive frames 1519 to MTU bytes : %ju\n",
3248             (uintmax_t)stats->rx_pkts_1519_max);
3249         printf("Receive frames too long : %ju\n",
3250             (uint64_t)stats->rx_pkts_truncated);
3251         printf("Receive frames with FIFO overflow : %u\n",
3252             stats->rx_fifo_oflows);
3253         printf("Receive frames with return descriptor overflow : %u\n",
3254             stats->rx_desc_oflows);
3255         printf("Receive frames with alignment errors : %u\n",
3256             stats->rx_alignerrs);
3257         printf("Receive frames dropped due to address filtering : %ju\n",
3258             (uint64_t)stats->rx_pkts_filtered);
3259
3260         return (error);
3261 }
3262
3263 static int
3264 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3265 {
3266         int error, value;
3267
3268         if (arg1 == NULL)
3269                 return (EINVAL);
3270         value = *(int *)arg1;
3271         error = sysctl_handle_int(oidp, &value, 0, req);
3272         if (error || req->newptr == NULL)
3273                 return (error);
3274         if (value < low || value > high)
3275                 return (EINVAL);
3276         *(int *)arg1 = value;
3277
3278         return (0);
3279 }
3280
3281 static int
3282 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3283 {
3284         return (sysctl_int_range(oidp, arg1, arg2, req,
3285             AGE_PROC_MIN, AGE_PROC_MAX));
3286 }
3287
3288 static int
3289 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3290 {
3291
3292         return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3293             AGE_IM_TIMER_MAX));
3294 }