2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #include "opt_atpic.h"
38 #include "opt_compat.h"
39 #include "opt_hwpmc_hooks.h"
40 #include "opt_kdtrace.h"
42 #include <machine/asmacros.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/specialreg.h>
51 .globl dtrace_invop_jump_addr
53 .type dtrace_invop_jump_addr,@object
54 .size dtrace_invop_jump_addr,8
55 dtrace_invop_jump_addr:
57 .globl dtrace_invop_calltrap_addr
59 .type dtrace_invop_calltrap_addr,@object
60 .size dtrace_invop_calltrap_addr,8
61 dtrace_invop_calltrap_addr:
66 ENTRY(start_exceptions)
69 /*****************************************************************************/
71 /*****************************************************************************/
73 * Trap and fault vector routines.
75 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
76 * state on the stack but also disables interrupts. This is important for
77 * us for the use of the swapgs instruction. We cannot be interrupted
78 * until the GS.base value is correct. For most traps, we automatically
79 * then enable interrupts if the interrupted context had them enabled.
80 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
82 * The cpu will push a certain amount of state onto the kernel stack for
83 * the current process. See amd64/include/frame.h.
84 * This includes the current RFLAGS (status register, which includes
85 * the interrupt disable state prior to the trap), the code segment register,
86 * and the return instruction pointer are pushed by the cpu. The cpu
87 * will also push an 'error' code for certain traps. We push a dummy
88 * error code for those traps where the cpu doesn't in order to maintain
89 * a consistent frame. We also push a contrived 'trap number'.
91 * The cpu does not push the general registers, we must do that, and we
92 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
93 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
94 * must load them with appropriate values for supervisor mode operation.
100 /* Traps that we leave interrupts disabled for.. */
101 #define TRAP_NOEN(a) \
103 movl $(a),TF_TRAPNO(%rsp) ; \
104 movq $0,TF_ADDR(%rsp) ; \
105 movq $0,TF_ERR(%rsp) ; \
113 TRAP_NOEN(T_DTRACE_RET)
116 /* Regular traps; The cpu does not supply tf_err for these. */
119 movl $(a),TF_TRAPNO(%rsp) ; \
120 movq $0,TF_ADDR(%rsp) ; \
121 movq $0,TF_ERR(%rsp) ; \
144 /* This group of traps have tf_err already pushed by the cpu */
145 #define TRAP_ERR(a) \
147 movl $(a),TF_TRAPNO(%rsp) ; \
148 movq $0,TF_ADDR(%rsp) ; \
160 * alltraps entry point. Use swapgs if this is the first time in the
161 * kernel from userland. Reenable interrupts if they were enabled
162 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
166 .type alltraps,@function
168 movq %rdi,TF_RDI(%rsp)
169 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
170 jz alltraps_testi /* already running with kernel GS.base */
172 movq PCPU(CURPCB),%rdi
173 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
179 testl $PSL_I,TF_RFLAGS(%rsp)
180 jz alltraps_pushregs_no_rdi
182 alltraps_pushregs_no_rdi:
183 movq %rsi,TF_RSI(%rsp)
184 movq %rdx,TF_RDX(%rsp)
185 movq %rcx,TF_RCX(%rsp)
188 movq %rax,TF_RAX(%rsp)
189 movq %rbx,TF_RBX(%rsp)
190 movq %rbp,TF_RBP(%rsp)
191 movq %r10,TF_R10(%rsp)
192 movq %r11,TF_R11(%rsp)
193 movq %r12,TF_R12(%rsp)
194 movq %r13,TF_R13(%rsp)
195 movq %r14,TF_R14(%rsp)
196 movq %r15,TF_R15(%rsp)
197 movl $TF_HASSEGS,TF_FLAGS(%rsp)
199 FAKE_MCOUNT(TF_RIP(%rsp))
202 * DTrace Function Boundary Trace (fbt) probes are triggered
203 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
204 * interrupt. For all other trap types, just handle them in
207 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
210 /* Check if there is no DTrace hook registered. */
211 cmpq $0,dtrace_invop_jump_addr
215 * Set our jump address for the jump back in the event that
216 * the breakpoint wasn't caused by DTrace at all.
218 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
220 /* Jump to the code hooked in by DTrace. */
221 movq dtrace_invop_jump_addr,%rax
222 jmpq *dtrace_invop_jump_addr
225 .type calltrap,@function
230 jmp doreti /* Handle any pending ASTs */
233 * alltraps_noen entry point. Unlike alltraps above, we want to
234 * leave the interrupts disabled. This corresponds to
235 * SDT_SYS386IGT on the i386 port.
239 .type alltraps_noen,@function
241 movq %rdi,TF_RDI(%rsp)
242 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
243 jz 1f /* already running with kernel GS.base */
245 movq PCPU(CURPCB),%rdi
246 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
247 1: movw %fs,TF_FS(%rsp)
251 jmp alltraps_pushregs_no_rdi
255 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
256 movq $0,TF_ADDR(%rsp)
258 movq %rdi,TF_RDI(%rsp)
259 movq %rsi,TF_RSI(%rsp)
260 movq %rdx,TF_RDX(%rsp)
261 movq %rcx,TF_RCX(%rsp)
264 movq %rax,TF_RAX(%rsp)
265 movq %rbx,TF_RBX(%rsp)
266 movq %rbp,TF_RBP(%rsp)
267 movq %r10,TF_R10(%rsp)
268 movq %r11,TF_R11(%rsp)
269 movq %r12,TF_R12(%rsp)
270 movq %r13,TF_R13(%rsp)
271 movq %r14,TF_R14(%rsp)
272 movq %r15,TF_R15(%rsp)
277 movl $TF_HASSEGS,TF_FLAGS(%rsp)
279 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
280 jz 1f /* already running with kernel GS.base */
284 call dblfault_handler
291 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
292 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
293 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
294 jz 1f /* already running with kernel GS.base */
296 movq PCPU(CURPCB),%rdi
297 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
298 1: movq %cr2,%rdi /* preserve %cr2 before .. */
299 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
304 testl $PSL_I,TF_RFLAGS(%rsp)
305 jz alltraps_pushregs_no_rdi
307 jmp alltraps_pushregs_no_rdi
310 * We have to special-case this one. If we get a trap in doreti() at
311 * the iretq stage, we'll reenter with the wrong gs state. We'll have
312 * to do a special the swapgs in this case even coming from the kernel.
313 * XXX linux has a trap handler for their equivalent of load_gs().
317 movl $T_PROTFLT,TF_TRAPNO(%rsp)
318 movq $0,TF_ADDR(%rsp)
319 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
320 leaq doreti_iret(%rip),%rdi
321 cmpq %rdi,TF_RIP(%rsp)
322 je 1f /* kernel but with user gsbase!! */
323 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
324 jz 2f /* already running with kernel GS.base */
326 2: movq PCPU(CURPCB),%rdi
327 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
332 testl $PSL_I,TF_RFLAGS(%rsp)
333 jz alltraps_pushregs_no_rdi
335 jmp alltraps_pushregs_no_rdi
338 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
339 * and the new privilige level. We are still running on the old user stack
340 * pointer. We have to juggle a few things around to find our stack etc.
341 * swapgs gives us access to our PCPU space only.
343 * We do not support invoking this from a custom %cs or %ss (e.g. using
344 * entries from an LDT).
348 movq %rsp,PCPU(SCRATCH_RSP)
350 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
352 /* defer TF_RSP till we have a spare register */
353 movq %r11,TF_RFLAGS(%rsp)
354 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
355 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
356 movq %r11,TF_RSP(%rsp) /* user stack pointer */
361 movq PCPU(CURPCB),%r11
362 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
364 movq $KUDSEL,TF_SS(%rsp)
365 movq $KUCSEL,TF_CS(%rsp)
367 movq %rdi,TF_RDI(%rsp) /* arg 1 */
368 movq %rsi,TF_RSI(%rsp) /* arg 2 */
369 movq %rdx,TF_RDX(%rsp) /* arg 3 */
370 movq %r10,TF_RCX(%rsp) /* arg 4 */
371 movq %r8,TF_R8(%rsp) /* arg 5 */
372 movq %r9,TF_R9(%rsp) /* arg 6 */
373 movq %rax,TF_RAX(%rsp) /* syscall number */
374 movq %rbx,TF_RBX(%rsp) /* C preserved */
375 movq %rbp,TF_RBP(%rsp) /* C preserved */
376 movq %r12,TF_R12(%rsp) /* C preserved */
377 movq %r13,TF_R13(%rsp) /* C preserved */
378 movq %r14,TF_R14(%rsp) /* C preserved */
379 movq %r15,TF_R15(%rsp) /* C preserved */
380 movl $TF_HASSEGS,TF_FLAGS(%rsp)
382 FAKE_MCOUNT(TF_RIP(%rsp))
383 movq PCPU(CURTHREAD),%rdi
384 movq %rsp,TD_FRAME(%rdi)
385 movl TF_RFLAGS(%rsp),%esi
388 1: movq PCPU(CURPCB),%rax
389 /* Disable interrupts before testing PCB_FULL_IRET. */
391 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
393 /* Check for and handle AST's on return to userland. */
394 movq PCPU(CURTHREAD),%rax
395 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
397 /* Restore preserved registers. */
399 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
400 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
401 movq TF_RDX(%rsp),%rdx /* return value 2 */
402 movq TF_RAX(%rsp),%rax /* return value 1 */
403 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
404 movq TF_RIP(%rsp),%rcx /* original %rip */
405 movq TF_RSP(%rsp),%rsp /* user stack pointer */
409 2: /* AST scheduled. */
415 3: /* Requested full context restore, use doreti for that. */
420 * Here for CYA insurance, in case a "syscall" instruction gets
421 * issued from 32 bit compatability mode. MSR_CSTAR has to point
422 * to *something* if EFER_SCE is enabled.
424 IDTVEC(fast_syscall32)
428 * NMI handling is special.
430 * First, NMIs do not respect the state of the processor's RFLAGS.IF
431 * bit. The NMI handler may be entered at any time, including when
432 * the processor is in a critical section with RFLAGS.IF == 0.
433 * The processor's GS.base value could be invalid on entry to the
436 * Second, the processor treats NMIs specially, blocking further NMIs
437 * until an 'iretq' instruction is executed. We thus need to execute
438 * the NMI handler with interrupts disabled, to prevent a nested interrupt
439 * from executing an 'iretq' instruction and inadvertently taking the
440 * processor out of NMI mode.
442 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
443 * GS.base value for the processor is stored just above the bottom of its
444 * NMI stack. For NMIs taken from kernel mode, the current value in
445 * the processor's GS.base is saved at entry to C-preserved register %r12,
446 * the canonical value for GS.base is then loaded into the processor, and
447 * the saved value is restored at exit time. For NMIs taken from user mode,
448 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
453 movl $(T_NMI),TF_TRAPNO(%rsp)
454 movq $0,TF_ADDR(%rsp)
456 movq %rdi,TF_RDI(%rsp)
457 movq %rsi,TF_RSI(%rsp)
458 movq %rdx,TF_RDX(%rsp)
459 movq %rcx,TF_RCX(%rsp)
462 movq %rax,TF_RAX(%rsp)
463 movq %rbx,TF_RBX(%rsp)
464 movq %rbp,TF_RBP(%rsp)
465 movq %r10,TF_R10(%rsp)
466 movq %r11,TF_R11(%rsp)
467 movq %r12,TF_R12(%rsp)
468 movq %r13,TF_R13(%rsp)
469 movq %r14,TF_R14(%rsp)
470 movq %r15,TF_R15(%rsp)
475 movl $TF_HASSEGS,TF_FLAGS(%rsp)
478 testb $SEL_RPL_MASK,TF_CS(%rsp)
479 jnz nmi_fromuserspace
481 * We've interrupted the kernel. Preserve GS.base in %r12.
483 movl $MSR_GSBASE,%ecx
488 /* Retrieve and load the canonical value for GS.base. */
489 movq TF_SIZE(%rsp),%rdx
497 /* Note: this label is also used by ddb and gdb: */
499 FAKE_MCOUNT(TF_RIP(%rsp))
505 * Capture a userspace callchain if needed.
507 * - Check if the current trap was from user mode.
508 * - Check if the current thread is valid.
509 * - Check if the thread requires a user call chain to be
512 * We are still in NMI mode at this point.
515 jz nocallchain /* not from userspace */
516 movq PCPU(CURTHREAD),%rax
517 orq %rax,%rax /* curthread present? */
519 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
522 * A user callchain is to be captured, so:
523 * - Move execution to the regular kernel stack, to allow for
524 * nested NMI interrupts.
525 * - Take the processor out of "NMI" mode by faking an "iret".
526 * - Enable interrupts, so that copyin() can work.
528 movq %rsp,%rsi /* source stack pointer */
532 movq %rdx,%rdi /* destination stack pointer */
534 shrq $3,%rcx /* trap frame size in long words */
537 movsq /* copy trapframe */
540 pushq %rax /* tf_ss */
541 pushq %rdx /* tf_rsp (on kernel stack) */
542 pushfq /* tf_rflags */
544 pushq %rax /* tf_cs */
545 pushq $outofnmi /* tf_rip */
549 * At this point the processor has exited NMI mode and is running
550 * with interrupts turned off on the normal kernel stack.
552 * If a pending NMI gets recognized at or after this point, it
553 * will cause a kernel callchain to be traced.
555 * We turn interrupts back on, and call the user callchain capture hook.
560 movq PCPU(CURTHREAD),%rdi /* thread */
561 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
562 movq %rsp,%rdx /* frame */
572 * Put back the preserved MSR_GSBASE value.
574 movl $MSR_GSBASE,%ecx
580 movq TF_RDI(%rsp),%rdi
581 movq TF_RSI(%rsp),%rsi
582 movq TF_RDX(%rsp),%rdx
583 movq TF_RCX(%rsp),%rcx
586 movq TF_RAX(%rsp),%rax
587 movq TF_RBX(%rsp),%rbx
588 movq TF_RBP(%rsp),%rbp
589 movq TF_R10(%rsp),%r10
590 movq TF_R11(%rsp),%r11
591 movq TF_R12(%rsp),%r12
592 movq TF_R13(%rsp),%r13
593 movq TF_R14(%rsp),%r14
594 movq TF_R15(%rsp),%r15
598 ENTRY(fork_trampoline)
599 movq %r12,%rdi /* function */
600 movq %rbx,%rsi /* arg1 */
601 movq %rsp,%rdx /* trapframe pointer */
604 jmp doreti /* Handle any ASTs */
607 * To efficiently implement classification of trap and interrupt handlers
608 * for profiling, there must be only trap handlers between the labels btrap
609 * and bintr, and only interrupt handlers between the labels bintr and
610 * eintr. This is implemented (partly) by including files that contain
611 * some of the handlers. Before including the files, set up a normal asm
612 * environment so that the included files doen't need to know that they are
616 #ifdef COMPAT_FREEBSD32
622 #include <amd64/ia32/ia32_exception.S>
631 #include <amd64/amd64/apic_vector.S>
639 #include <amd64/amd64/atpic_vector.S>
646 * void doreti(struct trapframe)
648 * Handle return from interrupts, traps and syscalls.
652 .type doreti,@function
654 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
656 * Check if ASTs can be handled now.
658 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
659 jz doreti_exit /* can't handle ASTs now if not */
663 * Check for ASTs atomically with returning. Disabling CPU
664 * interrupts provides sufficient locking even in the SMP case,
665 * since we will be informed of any new ASTs by an IPI.
668 movq PCPU(CURTHREAD),%rax
669 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
672 movq %rsp,%rdi /* pass a pointer to the trapframe */
677 * doreti_exit: pop registers, iret.
679 * The segment register pop is a special case, since it may
680 * fault if (for example) a sigreturn specifies bad segment
681 * registers. The fault is handled in trap.c.
685 movq PCPU(CURPCB),%r8
688 * Do not reload segment registers for kernel.
689 * Since we do not reload segments registers with sane
690 * values on kernel entry, descriptors referenced by
691 * segments registers might be not valid. This is fatal
692 * for user mode, but is not a problem for the kernel.
694 testb $SEL_RPL_MASK,TF_CS(%rsp)
696 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
698 testl $TF_HASSEGS,TF_FLAGS(%rsp)
702 /* Restore %fs and fsbase */
709 movl $MSR_FSBASE,%ecx
710 movl PCB_FSBASE(%r8),%eax
711 movl PCB_FSBASE+4(%r8),%edx
716 /* Restore %gs and gsbase */
720 movl $MSR_GSBASE,%ecx
729 movl $MSR_KGSBASE,%ecx
730 movl PCB_GSBASE(%r8),%eax
731 movl PCB_GSBASE+4(%r8),%edx
743 movq TF_RDI(%rsp),%rdi
744 movq TF_RSI(%rsp),%rsi
745 movq TF_RDX(%rsp),%rdx
746 movq TF_RCX(%rsp),%rcx
749 movq TF_RAX(%rsp),%rax
750 movq TF_RBX(%rsp),%rbx
751 movq TF_RBP(%rsp),%rbp
752 movq TF_R10(%rsp),%r10
753 movq TF_R11(%rsp),%r11
754 movq TF_R12(%rsp),%r12
755 movq TF_R13(%rsp),%r13
756 movq TF_R14(%rsp),%r14
757 movq TF_R15(%rsp),%r15
758 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
759 jz 1f /* keep running with kernel GS.base */
763 addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */
772 movw $KUF32SEL,TF_FS(%rsp)
773 movw $KUG32SEL,TF_GS(%rsp)
777 * doreti_iret_fault. Alternative return code for
778 * the case where we get a fault in the doreti_exit code
779 * above. trap() (amd64/amd64/trap.c) catches this specific
780 * case, sends the process a signal and continues in the
781 * corresponding place in the code below.
784 .globl doreti_iret_fault
786 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
787 testl $PSL_I,TF_RFLAGS(%rsp)
795 movl $TF_HASSEGS,TF_FLAGS(%rsp)
796 movq %rdi,TF_RDI(%rsp)
797 movq %rsi,TF_RSI(%rsp)
798 movq %rdx,TF_RDX(%rsp)
799 movq %rcx,TF_RCX(%rsp)
802 movq %rax,TF_RAX(%rsp)
803 movq %rbx,TF_RBX(%rsp)
804 movq %rbp,TF_RBP(%rsp)
805 movq %r10,TF_R10(%rsp)
806 movq %r11,TF_R11(%rsp)
807 movq %r12,TF_R12(%rsp)
808 movq %r13,TF_R13(%rsp)
809 movq %r14,TF_R14(%rsp)
810 movq %r15,TF_R15(%rsp)
811 movl $T_PROTFLT,TF_TRAPNO(%rsp)
812 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
813 movq $0,TF_ADDR(%rsp)
814 FAKE_MCOUNT(TF_RIP(%rsp))
820 movl $T_PROTFLT,TF_TRAPNO(%rsp)
823 movw $KUDSEL,TF_DS(%rsp)
829 movl $T_PROTFLT,TF_TRAPNO(%rsp)
832 movw $KUDSEL,TF_ES(%rsp)
838 movl $T_PROTFLT,TF_TRAPNO(%rsp)
841 movw $KUF32SEL,TF_FS(%rsp)
848 movl $T_PROTFLT,TF_TRAPNO(%rsp)
851 movw $KUG32SEL,TF_GS(%rsp)
855 .globl fsbase_load_fault
857 movl $T_PROTFLT,TF_TRAPNO(%rsp)
860 movq PCPU(CURTHREAD),%r8
862 movq $0,PCB_FSBASE(%r8)
866 .globl gsbase_load_fault
868 movl $T_PROTFLT,TF_TRAPNO(%rsp)
871 movq PCPU(CURTHREAD),%r8
873 movq $0,PCB_GSBASE(%r8)
877 ENTRY(end_exceptions)