1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PEMX_TYPEDEFS_H__
53 #define __CVMX_PEMX_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
60 cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
61 return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
64 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
71 cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id);
72 return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull;
75 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
82 cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
83 return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull;
86 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
93 cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
94 return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull;
97 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
104 cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id);
105 return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull;
108 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
115 cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id);
116 return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull;
119 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
126 cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
127 return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull;
130 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
137 cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
138 return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull;
141 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
148 cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
149 return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull;
152 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
155 static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
159 cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
160 return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull;
163 #define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
166 static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
170 cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
171 return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull;
174 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
177 static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
181 cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id);
182 return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull;
185 #define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
192 cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id);
193 return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull;
196 #define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
199 static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
203 cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id);
204 return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull;
207 #define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
210 static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
213 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
214 cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
215 return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull;
218 #define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
221 static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
225 cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
226 return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull;
229 #define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
232 static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
236 cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
237 return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull;
240 #define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
243 static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
247 cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
248 return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
251 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
254 static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
257 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
258 cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
259 return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
262 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
264 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
265 static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
269 cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
270 return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull;
273 #define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
277 * cvmx_pem#_bar1_index#
279 * PEM_BAR1_INDEXX = PEM BAR1 IndexX Register
281 * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
283 union cvmx_pemx_bar1_indexx
286 struct cvmx_pemx_bar1_indexx_s
288 #if __BYTE_ORDER == __BIG_ENDIAN
289 uint64_t reserved_20_63 : 44;
290 uint64_t addr_idx : 16; /**< Address bits [37:22] sent to L2C */
291 uint64_t ca : 1; /**< Set '1' when access is not to be cached in L2. */
292 uint64_t end_swp : 2; /**< Endian Swap Mode */
293 uint64_t addr_v : 1; /**< Set '1' when the selected address range is valid. */
296 uint64_t end_swp : 2;
298 uint64_t addr_idx : 16;
299 uint64_t reserved_20_63 : 44;
302 struct cvmx_pemx_bar1_indexx_s cn63xx;
303 struct cvmx_pemx_bar1_indexx_s cn63xxp1;
305 typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t;
310 * PEM_BAR_CTUS = PEM BAR Control
312 * Contains control for BAR accesses.
314 union cvmx_pemx_bar_ctl
317 struct cvmx_pemx_bar_ctl_s
319 #if __BYTE_ORDER == __BIG_ENDIAN
320 uint64_t reserved_7_63 : 57;
321 uint64_t bar1_siz : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
322 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
323 0 and 7 are reserved. */
324 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when
325 clear '0' BAR2 access will cause UR responses. */
326 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[39:38] to
327 determine the endian swap mode. */
328 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[40] to
329 determine the L2 cache attribute.
330 Not cached in L2 if XOR result is 1 */
332 uint64_t bar2_cax : 1;
333 uint64_t bar2_esx : 2;
334 uint64_t bar2_enb : 1;
335 uint64_t bar1_siz : 3;
336 uint64_t reserved_7_63 : 57;
339 struct cvmx_pemx_bar_ctl_s cn63xx;
340 struct cvmx_pemx_bar_ctl_s cn63xxp1;
342 typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
345 * cvmx_pem#_bist_status
347 * PEM_BIST_STATUS = PEM Bist Status
349 * Contains the diffrent interrupt summary bits of the PEM.
351 union cvmx_pemx_bist_status
354 struct cvmx_pemx_bist_status_s
356 #if __BYTE_ORDER == __BIG_ENDIAN
357 uint64_t reserved_8_63 : 56;
358 uint64_t retry : 1; /**< Retry Buffer. */
359 uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */
360 uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */
361 uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */
362 uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */
363 uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */
364 uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */
365 uint64_t sot : 1; /**< SOT Buffer. */
370 uint64_t rqdata3 : 1;
371 uint64_t rqdata2 : 1;
372 uint64_t rqdata1 : 1;
373 uint64_t rqdata0 : 1;
375 uint64_t reserved_8_63 : 56;
378 struct cvmx_pemx_bist_status_s cn63xx;
379 struct cvmx_pemx_bist_status_s cn63xxp1;
381 typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
384 * cvmx_pem#_bist_status2
386 * PEM(0..1)_BIST_STATUS2 = PEM BIST Status Register
388 * Results from BIST runs of PEM's memories.
390 union cvmx_pemx_bist_status2
393 struct cvmx_pemx_bist_status2_s
395 #if __BYTE_ORDER == __BIG_ENDIAN
396 uint64_t reserved_10_63 : 54;
397 uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */
398 uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */
399 uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */
400 uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */
401 uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */
402 uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */
403 uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */
404 uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */
405 uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */
406 uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */
409 uint64_t pef_tc0 : 1;
410 uint64_t pef_tcf1 : 1;
411 uint64_t pef_tnf : 1;
412 uint64_t pef_tpf0 : 1;
413 uint64_t pef_tpf1 : 1;
414 uint64_t peai_p2e : 1;
417 uint64_t e2p_cpl : 1;
418 uint64_t reserved_10_63 : 54;
421 struct cvmx_pemx_bist_status2_s cn63xx;
422 struct cvmx_pemx_bist_status2_s cn63xxp1;
424 typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
429 * PEM_CFG_RD = PEM Configuration Read
431 * Allows read access to the configuration in the PCIe Core.
433 union cvmx_pemx_cfg_rd
436 struct cvmx_pemx_cfg_rd_s
438 #if __BYTE_ORDER == __BIG_ENDIAN
439 uint64_t data : 32; /**< Data. */
440 uint64_t addr : 32; /**< Address to read. A write to this register
441 starts a read operation. */
447 struct cvmx_pemx_cfg_rd_s cn63xx;
448 struct cvmx_pemx_cfg_rd_s cn63xxp1;
450 typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
455 * PEM_CFG_WR = PEM Configuration Write
457 * Allows write access to the configuration in the PCIe Core.
459 union cvmx_pemx_cfg_wr
462 struct cvmx_pemx_cfg_wr_s
464 #if __BYTE_ORDER == __BIG_ENDIAN
465 uint64_t data : 32; /**< Data to write. A write to this register starts
466 a write operation. */
467 uint64_t addr : 32; /**< Address to write. A write to this register starts
468 a write operation. */
474 struct cvmx_pemx_cfg_wr_s cn63xx;
475 struct cvmx_pemx_cfg_wr_s cn63xxp1;
477 typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
480 * cvmx_pem#_cpl_lut_valid
482 * PEM_CPL_LUT_VALID = PEM Cmpletion Lookup Table Valid
484 * Bit set for outstanding tag read.
486 union cvmx_pemx_cpl_lut_valid
489 struct cvmx_pemx_cpl_lut_valid_s
491 #if __BYTE_ORDER == __BIG_ENDIAN
492 uint64_t reserved_32_63 : 32;
493 uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag
494 expecting a completion. */
497 uint64_t reserved_32_63 : 32;
500 struct cvmx_pemx_cpl_lut_valid_s cn63xx;
501 struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
503 typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t;
506 * cvmx_pem#_ctl_status
508 * PEM_CTL_STATUS = PEM Control Status
510 * General control and status of the PEM.
512 union cvmx_pemx_ctl_status
515 struct cvmx_pemx_ctl_status_s
517 #if __BYTE_ORDER == __BIG_ENDIAN
518 uint64_t reserved_48_63 : 16;
519 uint64_t auto_sd : 1; /**< Link Hardware Autonomous Speed Disable. */
520 uint64_t dnum : 5; /**< Primary bus device number. */
521 uint64_t pbus : 8; /**< Primary bus number. */
522 uint64_t reserved_32_33 : 2;
523 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a
524 CPL to a CFG RD that does not carry a Retry Status.
525 Until such time that the timeout occurs and Retry
526 Status is received for a CFG RD, the Read CFG Read
527 will be resent. A value of 0 disables retries and
528 treats a CPL Retry as a CPL UR.
529 When enabled only one CFG RD may be issued until
530 either successful completion or CPL UR. */
531 uint64_t reserved_12_15 : 4;
532 uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is
533 to the PCIe core pm_xmt_turnoff port. RC mode. */
534 uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is
535 to the PCIe core pm_xmt_pme port. EP mode. */
536 uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is
537 to the PCIe core outband_pwrup_cmd port. EP mode. */
538 uint64_t reserved_7_8 : 2;
539 uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */
540 uint64_t dly_one : 1; /**< When set the output client state machines will
541 wait one cycle before starting a new TLP out. */
542 uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the
543 link is disabled. This bit only is active when in
545 uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will
546 not wait for P-TLPs that normaly would be sent
548 uint64_t fast_lm : 1; /**< When '1' forces fast link mode. */
549 uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */
550 uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */
552 uint64_t inv_lcrc : 1;
553 uint64_t inv_ecrc : 1;
554 uint64_t fast_lm : 1;
555 uint64_t ro_ctlp : 1;
556 uint64_t lnk_enb : 1;
557 uint64_t dly_one : 1;
558 uint64_t nf_ecrc : 1;
559 uint64_t reserved_7_8 : 2;
560 uint64_t ob_p_cmd : 1;
561 uint64_t pm_xpme : 1;
562 uint64_t pm_xtoff : 1;
563 uint64_t reserved_12_15 : 4;
564 uint64_t cfg_rtry : 16;
565 uint64_t reserved_32_33 : 2;
568 uint64_t auto_sd : 1;
569 uint64_t reserved_48_63 : 16;
572 struct cvmx_pemx_ctl_status_s cn63xx;
573 struct cvmx_pemx_ctl_status_s cn63xxp1;
575 typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
580 * PEM(0..1)_DBG_INFO = PEM Debug Information
582 * General debug info.
584 union cvmx_pemx_dbg_info
587 struct cvmx_pemx_dbg_info_s
589 #if __BYTE_ORDER == __BIG_ENDIAN
590 uint64_t reserved_31_63 : 33;
591 uint64_t ecrc_e : 1; /**< Received a ECRC error.
593 uint64_t rawwpp : 1; /**< Received a write with poisoned payload
594 radm_rcvd_wreq_poisoned */
595 uint64_t racpp : 1; /**< Received a completion with poisoned payload
596 radm_rcvd_cpl_poisoned */
597 uint64_t ramtlp : 1; /**< Received a malformed TLP
599 uint64_t rarwdns : 1; /**< Recieved a request which device does not support
601 uint64_t caar : 1; /**< Completer aborted a request
603 This bit will never be set because Octeon does
604 not generate Completer Aborts. */
605 uint64_t racca : 1; /**< Received a completion with CA status
607 uint64_t racur : 1; /**< Received a completion with UR status
609 uint64_t rauc : 1; /**< Received an unexpected completion
610 radm_unexp_cpl_err */
611 uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when
612 flow control advertisements are ignored
614 uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks)
615 int_xadm_fc_prot_err */
616 uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error
617 (RxStatus = 3b100) or disparity error
618 (RxStatus = 3b111), the signal rmlh_rcvd_err will
621 uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer)
623 uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP)
625 uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error
627 uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error
629 uint64_t mre : 1; /**< Max Retries Exceeded
630 xdlh_replay_num_rlover_err */
631 uint64_t rte : 1; /**< Replay Timer Expired
632 xdlh_replay_timeout_err
633 This bit is set when the REPLAY_TIMER expires in
634 the PCIE core. The probability of this bit being
635 set will increase with the traffic load. */
636 uint64_t acto : 1; /**< A Completion Timeout Occured
637 pedc_radm_cpl_timeout */
638 uint64_t rvdm : 1; /**< Received Vendor-Defined Message
639 pedc_radm_vendor_msg */
640 uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only)
641 pedc_radm_msg_unlock */
642 uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message
644 pedc_radm_pm_to_ack */
645 uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only)
647 uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only)
649 Bit set when a message with ERR_FATAL is set. */
650 uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only)
651 pedc_radm_nonfatal_err */
652 uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only)
653 pedc_radm_correctable_err */
654 uint64_t rpoison : 1; /**< Received Poisoned TLP
655 pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */
656 uint64_t recrce : 1; /**< Received ECRC Error
657 pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */
658 uint64_t rtlplle : 1; /**< Received TLP has link layer error
659 pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */
660 uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message.
661 pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot
662 If the core receives a MSG (or Vendor Message)
663 this bit will be set. */
664 uint64_t spoison : 1; /**< Poisoned TLP sent
665 peai__client0_tlp_ep & peai__client0_tlp_hv */
667 uint64_t spoison : 1;
668 uint64_t rtlpmal : 1;
669 uint64_t rtlplle : 1;
671 uint64_t rpoison : 1;
673 uint64_t rnfemrc : 1;
676 uint64_t rptamrc : 1;
684 uint64_t dpeoosd : 1;
693 uint64_t rarwdns : 1;
698 uint64_t reserved_31_63 : 33;
701 struct cvmx_pemx_dbg_info_s cn63xx;
702 struct cvmx_pemx_dbg_info_s cn63xxp1;
704 typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
707 * cvmx_pem#_dbg_info_en
709 * PEM(0..1)_DBG_INFO_EN = PEM Debug Information Enable
711 * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set.
713 union cvmx_pemx_dbg_info_en
716 struct cvmx_pemx_dbg_info_en_s
718 #if __BYTE_ORDER == __BIG_ENDIAN
719 uint64_t reserved_31_63 : 33;
720 uint64_t ecrc_e : 1; /**< Allows PEM_DBG_INFO[30] to generate an interrupt. */
721 uint64_t rawwpp : 1; /**< Allows PEM_DBG_INFO[29] to generate an interrupt. */
722 uint64_t racpp : 1; /**< Allows PEM_DBG_INFO[28] to generate an interrupt. */
723 uint64_t ramtlp : 1; /**< Allows PEM_DBG_INFO[27] to generate an interrupt. */
724 uint64_t rarwdns : 1; /**< Allows PEM_DBG_INFO[26] to generate an interrupt. */
725 uint64_t caar : 1; /**< Allows PEM_DBG_INFO[25] to generate an interrupt. */
726 uint64_t racca : 1; /**< Allows PEM_DBG_INFO[24] to generate an interrupt. */
727 uint64_t racur : 1; /**< Allows PEM_DBG_INFO[23] to generate an interrupt. */
728 uint64_t rauc : 1; /**< Allows PEM_DBG_INFO[22] to generate an interrupt. */
729 uint64_t rqo : 1; /**< Allows PEM_DBG_INFO[21] to generate an interrupt. */
730 uint64_t fcuv : 1; /**< Allows PEM_DBG_INFO[20] to generate an interrupt. */
731 uint64_t rpe : 1; /**< Allows PEM_DBG_INFO[19] to generate an interrupt. */
732 uint64_t fcpvwt : 1; /**< Allows PEM_DBG_INFO[18] to generate an interrupt. */
733 uint64_t dpeoosd : 1; /**< Allows PEM_DBG_INFO[17] to generate an interrupt. */
734 uint64_t rtwdle : 1; /**< Allows PEM_DBG_INFO[16] to generate an interrupt. */
735 uint64_t rdwdle : 1; /**< Allows PEM_DBG_INFO[15] to generate an interrupt. */
736 uint64_t mre : 1; /**< Allows PEM_DBG_INFO[14] to generate an interrupt. */
737 uint64_t rte : 1; /**< Allows PEM_DBG_INFO[13] to generate an interrupt. */
738 uint64_t acto : 1; /**< Allows PEM_DBG_INFO[12] to generate an interrupt. */
739 uint64_t rvdm : 1; /**< Allows PEM_DBG_INFO[11] to generate an interrupt. */
740 uint64_t rumep : 1; /**< Allows PEM_DBG_INFO[10] to generate an interrupt. */
741 uint64_t rptamrc : 1; /**< Allows PEM_DBG_INFO[9] to generate an interrupt. */
742 uint64_t rpmerc : 1; /**< Allows PEM_DBG_INFO[8] to generate an interrupt. */
743 uint64_t rfemrc : 1; /**< Allows PEM_DBG_INFO[7] to generate an interrupt. */
744 uint64_t rnfemrc : 1; /**< Allows PEM_DBG_INFO[6] to generate an interrupt. */
745 uint64_t rcemrc : 1; /**< Allows PEM_DBG_INFO[5] to generate an interrupt. */
746 uint64_t rpoison : 1; /**< Allows PEM_DBG_INFO[4] to generate an interrupt. */
747 uint64_t recrce : 1; /**< Allows PEM_DBG_INFO[3] to generate an interrupt. */
748 uint64_t rtlplle : 1; /**< Allows PEM_DBG_INFO[2] to generate an interrupt. */
749 uint64_t rtlpmal : 1; /**< Allows PEM_DBG_INFO[1] to generate an interrupt. */
750 uint64_t spoison : 1; /**< Allows PEM_DBG_INFO[0] to generate an interrupt. */
752 uint64_t spoison : 1;
753 uint64_t rtlpmal : 1;
754 uint64_t rtlplle : 1;
756 uint64_t rpoison : 1;
758 uint64_t rnfemrc : 1;
761 uint64_t rptamrc : 1;
769 uint64_t dpeoosd : 1;
778 uint64_t rarwdns : 1;
783 uint64_t reserved_31_63 : 33;
786 struct cvmx_pemx_dbg_info_en_s cn63xx;
787 struct cvmx_pemx_dbg_info_en_s cn63xxp1;
789 typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
792 * cvmx_pem#_diag_status
794 * PEM_DIAG_STATUS = PEM Diagnostic Status
796 * Selection control for the cores diagnostic bus.
798 union cvmx_pemx_diag_status
801 struct cvmx_pemx_diag_status_s
803 #if __BYTE_ORDER == __BIG_ENDIAN
804 uint64_t reserved_4_63 : 60;
805 uint64_t pm_dst : 1; /**< Current power management DSTATE. */
806 uint64_t pm_stat : 1; /**< Power Management Status. */
807 uint64_t pm_en : 1; /**< Power Management Event Enable. */
808 uint64_t aux_en : 1; /**< Auxilary Power Enable. */
812 uint64_t pm_stat : 1;
814 uint64_t reserved_4_63 : 60;
817 struct cvmx_pemx_diag_status_s cn63xx;
818 struct cvmx_pemx_diag_status_s cn63xxp1;
820 typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t;
825 * PEM(0..1)_INT_ENB = PEM Interrupt Enable
827 * Enables interrupt conditions for the PEM to generate an RSL interrupt.
829 union cvmx_pemx_int_enb
832 struct cvmx_pemx_int_enb_s
834 #if __BYTE_ORDER == __BIG_ENDIAN
835 uint64_t reserved_14_63 : 50;
836 uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an
837 interrupt to the MIO. */
838 uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an
839 interrupt to the MIO. */
840 uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an
841 interrupt to the MIO. */
842 uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an
843 interrupt to the MIO. */
844 uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an
845 interrupt to the MIO. */
846 uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an
847 interrupt to the MIO. */
848 uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an
849 interrupt to the MIO. */
850 uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an
851 interrupt to the MIO. */
852 uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an
853 interrupt to the MIO. */
854 uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an
855 interrupt to the MIO. */
856 uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an
857 interrupt to the MIO. */
858 uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an
859 interrupt to the MIO. */
860 uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an
861 interrupt to the MIO. */
862 uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an
863 interrupt to the MIO. */
879 uint64_t reserved_14_63 : 50;
882 struct cvmx_pemx_int_enb_s cn63xx;
883 struct cvmx_pemx_int_enb_s cn63xxp1;
885 typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
888 * cvmx_pem#_int_enb_int
890 * PEM(0..1)_INT_ENB_INT = PEM Interrupt Enable
892 * Enables interrupt conditions for the PEM to generate an RSL interrupt.
894 union cvmx_pemx_int_enb_int
897 struct cvmx_pemx_int_enb_int_s
899 #if __BYTE_ORDER == __BIG_ENDIAN
900 uint64_t reserved_14_63 : 50;
901 uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an
902 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
903 uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an
904 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
905 uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an
906 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
907 uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an
908 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
909 uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an
910 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
911 uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an
912 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
913 uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an
914 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
915 uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an
916 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
917 uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an
918 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
919 uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an
920 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
921 uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an
922 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
923 uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an
924 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
925 uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an
926 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
927 uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an
928 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
944 uint64_t reserved_14_63 : 50;
947 struct cvmx_pemx_int_enb_int_s cn63xx;
948 struct cvmx_pemx_int_enb_int_s cn63xxp1;
950 typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
955 * Below are in pesc_csr
957 * PEM(0..1)_INT_SUM = PEM Interrupt Summary
959 * Interrupt conditions for the PEM.
961 union cvmx_pemx_int_sum
964 struct cvmx_pemx_int_sum_s
966 #if __BYTE_ORDER == __BIG_ENDIAN
967 uint64_t reserved_14_63 : 50;
968 uint64_t crs_dr : 1; /**< Had a CRS Timeout when Retries were disabled. */
969 uint64_t crs_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
970 uint64_t rdlk : 1; /**< Received Read Lock TLP. */
971 uint64_t exc : 1; /**< Set when the PEM_DBG_INFO register has a bit
972 set and its cooresponding PEM_DBG_INFO_EN bit
974 uint64_t un_bx : 1; /**< Received N-TLP for an unknown Bar. */
975 uint64_t un_b2 : 1; /**< Received N-TLP for Bar2 when bar2 is disabled. */
976 uint64_t un_b1 : 1; /**< Received N-TLP for Bar1 when bar1 index valid
978 uint64_t up_bx : 1; /**< Received P-TLP for an unknown Bar. */
979 uint64_t up_b2 : 1; /**< Received P-TLP for Bar2 when bar2 is disabeld. */
980 uint64_t up_b1 : 1; /**< Received P-TLP for Bar1 when bar1 index valid
982 uint64_t pmem : 1; /**< Recived PME MSG.
984 uint64_t pmei : 1; /**< PME Interrupt.
986 uint64_t se : 1; /**< System Error, RC Mode Only.
988 uint64_t aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
989 (cfg_aer_rc_err_int). */
1003 uint64_t crs_er : 1;
1004 uint64_t crs_dr : 1;
1005 uint64_t reserved_14_63 : 50;
1008 struct cvmx_pemx_int_sum_s cn63xx;
1009 struct cvmx_pemx_int_sum_s cn63xxp1;
1011 typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
1014 * cvmx_pem#_p2n_bar0_start
1016 * PEM_P2N_BAR0_START = PEM PCIe to Npei BAR0 Start
1018 * The starting address for addresses to forwarded to the SLI in RC Mode.
1020 union cvmx_pemx_p2n_bar0_start
1023 struct cvmx_pemx_p2n_bar0_start_s
1025 #if __BYTE_ORDER == __BIG_ENDIAN
1026 uint64_t addr : 50; /**< The starting address of the 16KB address space that
1027 is the BAR0 address space. */
1028 uint64_t reserved_0_13 : 14;
1030 uint64_t reserved_0_13 : 14;
1034 struct cvmx_pemx_p2n_bar0_start_s cn63xx;
1035 struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
1037 typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
1040 * cvmx_pem#_p2n_bar1_start
1042 * PEM_P2N_BAR1_START = PEM PCIe to Npei BAR1 Start
1044 * The starting address for addresses to forwarded to the SLI in RC Mode.
1046 union cvmx_pemx_p2n_bar1_start
1049 struct cvmx_pemx_p2n_bar1_start_s
1051 #if __BYTE_ORDER == __BIG_ENDIAN
1052 uint64_t addr : 38; /**< The starting address of the 64KB address space
1053 that is the BAR1 address space. */
1054 uint64_t reserved_0_25 : 26;
1056 uint64_t reserved_0_25 : 26;
1060 struct cvmx_pemx_p2n_bar1_start_s cn63xx;
1061 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
1063 typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
1066 * cvmx_pem#_p2n_bar2_start
1068 * PEM_P2N_BAR2_START = PEM PCIe to Npei BAR2 Start
1070 * The starting address for addresses to forwarded to the SLI in RC Mode.
1072 union cvmx_pemx_p2n_bar2_start
1075 struct cvmx_pemx_p2n_bar2_start_s
1077 #if __BYTE_ORDER == __BIG_ENDIAN
1078 uint64_t addr : 23; /**< The starting address of the 2^41 address space
1079 that is the BAR2 address space. */
1080 uint64_t reserved_0_40 : 41;
1082 uint64_t reserved_0_40 : 41;
1086 struct cvmx_pemx_p2n_bar2_start_s cn63xx;
1087 struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
1089 typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
1092 * cvmx_pem#_p2p_bar#_end
1094 * PEM_P2P_BAR#_END = PEM Peer-To-Peer BAR0 End
1096 * The ending address for addresses to forwarded to the PCIe peer port.
1098 union cvmx_pemx_p2p_barx_end
1101 struct cvmx_pemx_p2p_barx_end_s
1103 #if __BYTE_ORDER == __BIG_ENDIAN
1104 uint64_t addr : 52; /**< The ending address of the address window created
1105 this field and the PEM_P2P_BAR0_START[63:12]
1106 field. The full 64-bits of address are created by:
1107 [ADDR[63:12], 12'b0]. */
1108 uint64_t reserved_0_11 : 12;
1110 uint64_t reserved_0_11 : 12;
1114 struct cvmx_pemx_p2p_barx_end_s cn63xx;
1115 struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
1117 typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
1120 * cvmx_pem#_p2p_bar#_start
1122 * PEM_P2P_BAR#_START = PEM Peer-To-Peer BAR0 Start
1124 * The starting address and enable for addresses to forwarded to the PCIe peer port.
1126 union cvmx_pemx_p2p_barx_start
1129 struct cvmx_pemx_p2p_barx_start_s
1131 #if __BYTE_ORDER == __BIG_ENDIAN
1132 uint64_t addr : 52; /**< The starting address of the address window created
1133 by this field and the PEM_P2P_BAR0_END[63:12]
1134 field. The full 64-bits of address are created by:
1135 [ADDR[63:12], 12'b0]. */
1136 uint64_t reserved_0_11 : 12;
1138 uint64_t reserved_0_11 : 12;
1142 struct cvmx_pemx_p2p_barx_start_s cn63xx;
1143 struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
1145 typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
1148 * cvmx_pem#_tlp_credits
1150 * PEM_TLP_CREDITS = PEM TLP Credits
1152 * Specifies the number of credits the PEM for use in moving TLPs. When this register is written the credit values are
1153 * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
1155 union cvmx_pemx_tlp_credits
1158 struct cvmx_pemx_tlp_credits_s
1160 #if __BYTE_ORDER == __BIG_ENDIAN
1161 uint64_t reserved_56_63 : 8;
1162 uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer.
1163 Legal values are 0x24 to 0x80. */
1164 uint64_t pem_cpl : 8; /**< TLP credits for Completion TLPs in the Peer.
1165 Legal values are 0x24 to 0x80. */
1166 uint64_t pem_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer.
1167 Legal values are 0x4 to 0x10. */
1168 uint64_t pem_p : 8; /**< TLP credits for Posted TLPs in the Peer.
1169 Legal values are 0x24 to 0x80. */
1170 uint64_t sli_cpl : 8; /**< TLP credits for Completion TLPs in the SLI.
1171 Legal values are 0x24 to 0x80. */
1172 uint64_t sli_np : 8; /**< TLP credits for Non-Posted TLPs in the SLI.
1173 Legal values are 0x4 to 0x10. */
1174 uint64_t sli_p : 8; /**< TLP credits for Posted TLPs in the SLI.
1175 Legal values are 0x24 to 0x80. */
1178 uint64_t sli_np : 8;
1179 uint64_t sli_cpl : 8;
1181 uint64_t pem_np : 8;
1182 uint64_t pem_cpl : 8;
1183 uint64_t peai_ppf : 8;
1184 uint64_t reserved_56_63 : 8;
1187 struct cvmx_pemx_tlp_credits_s cn63xx;
1188 struct cvmx_pemx_tlp_credits_s cn63xxp1;
1190 typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t;