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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_STXX_TYPEDEFS_H__
53 #define __CVMX_STXX_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
61 cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id);
62 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
73 cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
74 return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
79 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80 static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
83 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
85 cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
86 return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
91 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
92 static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
95 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
96 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
97 cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id);
98 return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
103 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104 static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
107 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
109 cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
121 cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
122 return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull;
125 #define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
128 static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
131 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
132 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
133 cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id);
134 return CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull;
137 #define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
139 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
140 static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
143 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
145 cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
146 return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull;
149 #define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
152 static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
155 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
156 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
157 cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id);
158 return CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull;
161 #define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
167 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
169 cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
170 return CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
173 #define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
176 static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
181 cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id);
182 return CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull;
185 #define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
191 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
192 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
193 cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
194 return CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull;
197 #define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
200 static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
203 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
205 cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id);
206 return CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull;
209 #define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
215 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
216 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
217 cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id);
218 return CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull;
221 #define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
223 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
224 static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
227 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
228 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
229 cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id);
230 return CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull;
233 #define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
236 static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
239 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
241 cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id);
242 return CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull;
245 #define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
251 * STX_ARB_CTL - Spi transmit arbitration control
255 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
256 * parameter will have to be adjusted. Please see the
257 * STX_SPI4_DAT[MAX_T] section for additional information. In
258 * addition, the min_burst can only be guaranteed on the initial data
259 * burst of a given packet (i.e. the first data burst which contains
260 * the SOP tick). All subsequent bursts could be truncated by training
261 * sequences at any point during transmission and could be arbitrarily
262 * small. This mode is only for use in Spi4 mode.
264 union cvmx_stxx_arb_ctl
267 struct cvmx_stxx_arb_ctl_s
269 #if __BYTE_ORDER == __BIG_ENDIAN
270 uint64_t reserved_6_63 : 58;
271 uint64_t mintrn : 1; /**< Hold off training cycles until STX_MIN_BST[MINB]
273 uint64_t reserved_4_4 : 1;
274 uint64_t igntpa : 1; /**< User switch to ignore any TPA information from the
275 Spi interface. This CSR forces all TPA terms to
276 be masked out. It is only intended as backdoor
278 uint64_t reserved_0_2 : 3;
280 uint64_t reserved_0_2 : 3;
282 uint64_t reserved_4_4 : 1;
284 uint64_t reserved_6_63 : 58;
287 struct cvmx_stxx_arb_ctl_s cn38xx;
288 struct cvmx_stxx_arb_ctl_s cn38xxp2;
289 struct cvmx_stxx_arb_ctl_s cn58xx;
290 struct cvmx_stxx_arb_ctl_s cn58xxp1;
292 typedef union cvmx_stxx_arb_ctl cvmx_stxx_arb_ctl_t;
295 * cvmx_stx#_bckprs_cnt
298 * This register reports the total number of cycles (STX data clks -
299 * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA
300 * or is otherwise receiving backpressure.
302 * In Spi4 mode, this is defined as a loss of TPA which is indicated when
303 * the receiving device reports SATISFIED for the given port. The calendar
304 * status is brought into N2 on the spi4_tx*_sclk and synchronized into the
305 * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk
306 * clock (internally, this the stx_clk). The counter will update on the
307 * rising edge in which backpressure is reported.
309 * This register will be cleared when software writes all '1's to
310 * the STX_BCKPRS_CNT.
312 union cvmx_stxx_bckprs_cnt
315 struct cvmx_stxx_bckprs_cnt_s
317 #if __BYTE_ORDER == __BIG_ENDIAN
318 uint64_t reserved_32_63 : 32;
319 uint64_t cnt : 32; /**< Number of cycles when back-pressure is received
320 for port defined in STX_STAT_CTL[BCKPRS] */
323 uint64_t reserved_32_63 : 32;
326 struct cvmx_stxx_bckprs_cnt_s cn38xx;
327 struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
328 struct cvmx_stxx_bckprs_cnt_s cn58xx;
329 struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
331 typedef union cvmx_stxx_bckprs_cnt cvmx_stxx_bckprs_cnt_t;
336 * STX_COM_CTL - TX Common Control Register
341 * Both the calendar table and the LEN and M parameters must be
342 * completely setup before writing the Interface enable (INF_EN) and
343 * Status channel enabled (ST_EN) asserted.
345 union cvmx_stxx_com_ctl
348 struct cvmx_stxx_com_ctl_s
350 #if __BYTE_ORDER == __BIG_ENDIAN
351 uint64_t reserved_4_63 : 60;
352 uint64_t st_en : 1; /**< Status channel enabled */
353 uint64_t reserved_1_2 : 2;
354 uint64_t inf_en : 1; /**< Interface enable */
357 uint64_t reserved_1_2 : 2;
359 uint64_t reserved_4_63 : 60;
362 struct cvmx_stxx_com_ctl_s cn38xx;
363 struct cvmx_stxx_com_ctl_s cn38xxp2;
364 struct cvmx_stxx_com_ctl_s cn58xx;
365 struct cvmx_stxx_com_ctl_s cn58xxp1;
367 typedef union cvmx_stxx_com_ctl cvmx_stxx_com_ctl_t;
374 * This counts the number of consecutive DIP2 states in which the the
375 * received DIP2 is bad. The expected range is 1-15 cycles with the
376 * value of 0 meaning disabled.
379 * This counts the number of consecutive unexpected framing patterns (11)
380 * states. The expected range is 1-15 cycles with the value of 0 meaning
383 union cvmx_stxx_dip_cnt
386 struct cvmx_stxx_dip_cnt_s
388 #if __BYTE_ORDER == __BIG_ENDIAN
389 uint64_t reserved_8_63 : 56;
390 uint64_t frmmax : 4; /**< Number of consecutive unexpected framing patterns
391 before loss of sync */
392 uint64_t dipmax : 4; /**< Number of consecutive DIP2 error before loss
397 uint64_t reserved_8_63 : 56;
400 struct cvmx_stxx_dip_cnt_s cn38xx;
401 struct cvmx_stxx_dip_cnt_s cn38xxp2;
402 struct cvmx_stxx_dip_cnt_s cn58xx;
403 struct cvmx_stxx_dip_cnt_s cn58xxp1;
405 typedef union cvmx_stxx_dip_cnt cvmx_stxx_dip_cnt_t;
410 * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel
413 union cvmx_stxx_ign_cal
416 struct cvmx_stxx_ign_cal_s
418 #if __BYTE_ORDER == __BIG_ENDIAN
419 uint64_t reserved_16_63 : 48;
420 uint64_t igntpa : 16; /**< Ignore Calendar Status from Spi4 Status Channel
422 - 0: Use the status channel info
423 - 1: Grant the given port MAX_BURST1 credits */
425 uint64_t igntpa : 16;
426 uint64_t reserved_16_63 : 48;
429 struct cvmx_stxx_ign_cal_s cn38xx;
430 struct cvmx_stxx_ign_cal_s cn38xxp2;
431 struct cvmx_stxx_ign_cal_s cn58xx;
432 struct cvmx_stxx_ign_cal_s cn58xxp1;
434 typedef union cvmx_stxx_ign_cal cvmx_stxx_ign_cal_t;
440 * If the bit is enabled, then the coresponding exception condition will
441 * result in an interrupt to the system.
443 union cvmx_stxx_int_msk
446 struct cvmx_stxx_int_msk_s
448 #if __BYTE_ORDER == __BIG_ENDIAN
449 uint64_t reserved_8_63 : 56;
450 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
451 uint64_t unxfrm : 1; /**< Unexpected framing sequence */
452 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
453 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */
454 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */
455 uint64_t ovrbst : 1; /**< Transmit packet burst too big */
456 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */
457 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */
459 uint64_t calpar0 : 1;
460 uint64_t calpar1 : 1;
467 uint64_t reserved_8_63 : 56;
470 struct cvmx_stxx_int_msk_s cn38xx;
471 struct cvmx_stxx_int_msk_s cn38xxp2;
472 struct cvmx_stxx_int_msk_s cn58xx;
473 struct cvmx_stxx_int_msk_s cn58xxp1;
475 typedef union cvmx_stxx_int_msk cvmx_stxx_int_msk_t;
482 * This bit indicates that the Spi4 calendar table encountered a parity
483 * error on bank0 of the calendar table memory. This error bit is
484 * associated with the calendar table on the TX interface - the interface
485 * that drives the Spi databus. The calendar table is used in Spi4 mode
486 * when using the status channel. Parity errors can occur during normal
487 * operation when the calendar table is constantly being read for the port
488 * information, or during initialization time, when the user has access.
489 * This errors will force the the status channel to the reset state and
490 * begin driving training sequences. The status channel will also reset.
491 * Software must follow the init sequence to resynch the interface. This
492 * includes toggling INF_EN which will cancel all outstanding accumulated
496 * Identical to CALPAR0 except that it indicates that the error occured
497 * on bank1 (instead of bank0).
500 * STX can track upto a 512KB data burst. Any packet larger than that is
501 * illegal and will cause confusion in the STX state machine. BMI is
502 * responsible for throwing away these out of control packets from the
503 * input and the Execs should never generate them on the output. This is
504 * a fatal error and should have STX_INT_SYNC[OVRBST] set.
507 * FIFO where the Spi4 data ramps upto its transmit frequency has
508 * overflowed. This is a fatal error and should have
509 * STX_INT_SYNC[DATOVR] set.
512 * This bit will fire if any DIP2 error is caught by the Spi4 status
516 * This bit indicates that the number of consecutive DIP2 errors exceeds
517 * STX_DIP_CNT[MAXDIP] and that the interface should be taken down. The
518 * datapath will be notified and send continuous training sequences until
519 * software resynchronizes the interface. This error condition should
520 * have STX_INT_SYNC[NOSYNC] set.
523 * Unexpected framing data was seen on the status channel.
526 * This bit indicates that the number of consecutive unexpected framing
527 * sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken
528 * down. The datapath will be notified and send continuous training
529 * sequences until software resynchronizes the interface. This error
530 * condition should have STX_INT_SYNC[FRMERR] set.
533 * Indicates that an exception marked in STX_INT_SYNC has occured and the
534 * TX datapath is disabled. It is recommended that the OVRBST, DATOVR,
535 * NOSYNC, and FRMERR error conditions all have their bits set in the
536 * STX_INT_SYNC register.
538 union cvmx_stxx_int_reg
541 struct cvmx_stxx_int_reg_s
543 #if __BYTE_ORDER == __BIG_ENDIAN
544 uint64_t reserved_9_63 : 55;
545 uint64_t syncerr : 1; /**< Interface encountered a fatal error */
546 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
547 uint64_t unxfrm : 1; /**< Unexpected framing sequence */
548 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
549 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */
550 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */
551 uint64_t ovrbst : 1; /**< Transmit packet burst too big */
552 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */
553 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */
555 uint64_t calpar0 : 1;
556 uint64_t calpar1 : 1;
563 uint64_t syncerr : 1;
564 uint64_t reserved_9_63 : 55;
567 struct cvmx_stxx_int_reg_s cn38xx;
568 struct cvmx_stxx_int_reg_s cn38xxp2;
569 struct cvmx_stxx_int_reg_s cn58xx;
570 struct cvmx_stxx_int_reg_s cn58xxp1;
572 typedef union cvmx_stxx_int_reg cvmx_stxx_int_reg_t;
578 * If the bit is enabled, then the coresponding exception condition is flagged
579 * to be fatal. In Spi4 mode, the exception condition will result in a loss
580 * of sync condition on the Spi4 interface and the datapath will send
581 * continuous traing sequences.
583 * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and
584 * FRMERR errors as synchronization events. Software is free to
585 * synchronize the bus on other conditions, but this is the minimum
588 union cvmx_stxx_int_sync
591 struct cvmx_stxx_int_sync_s
593 #if __BYTE_ORDER == __BIG_ENDIAN
594 uint64_t reserved_8_63 : 56;
595 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
596 uint64_t unxfrm : 1; /**< Unexpected framing sequence */
597 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
598 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */
599 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */
600 uint64_t ovrbst : 1; /**< Transmit packet burst too big */
601 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */
602 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */
604 uint64_t calpar0 : 1;
605 uint64_t calpar1 : 1;
612 uint64_t reserved_8_63 : 56;
615 struct cvmx_stxx_int_sync_s cn38xx;
616 struct cvmx_stxx_int_sync_s cn38xxp2;
617 struct cvmx_stxx_int_sync_s cn58xx;
618 struct cvmx_stxx_int_sync_s cn58xxp1;
620 typedef union cvmx_stxx_int_sync cvmx_stxx_int_sync_t;
625 * STX_MIN_BST - Min Burst to enforce when inserting training sequence
628 union cvmx_stxx_min_bst
631 struct cvmx_stxx_min_bst_s
633 #if __BYTE_ORDER == __BIG_ENDIAN
634 uint64_t reserved_9_63 : 55;
635 uint64_t minb : 9; /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates
636 the number of 8B blocks to send before inserting
637 a training sequence. Normally MINB will be set
638 to GMX_TX_SPI_THRESH[THRESH]. MINB should always
639 be set to an even number (ie. multiple of 16B) */
642 uint64_t reserved_9_63 : 55;
645 struct cvmx_stxx_min_bst_s cn38xx;
646 struct cvmx_stxx_min_bst_s cn38xxp2;
647 struct cvmx_stxx_min_bst_s cn58xx;
648 struct cvmx_stxx_min_bst_s cn58xxp1;
650 typedef union cvmx_stxx_min_bst cvmx_stxx_min_bst_t;
653 * cvmx_stx#_spi4_cal#
655 * specify the RSL base addresses for the block
656 * STX_SPI4_CAL - Spi4 Calender table
657 * direct_calendar_write / direct_calendar_read
660 * There are 32 calendar table CSR's, each containing 4 entries for a
661 * total of 128 entries. In the above definition...
663 * n = calendar table offset * 4
665 * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
666 * (with n == 0). Offset 0x10 is the 16th entry in the calendar table
667 * and would contain entries (16*4) = 64, 65, 66, and 67.
670 * Calendar table entry accesses (read or write) can only occur
671 * if the interface is disabled. All other accesses will be
674 * Both the calendar table and the LEN and M parameters must be
675 * completely setup before writing the Interface enable (INF_EN) and
676 * Status channel enabled (ST_EN) asserted.
678 union cvmx_stxx_spi4_calx
681 struct cvmx_stxx_spi4_calx_s
683 #if __BYTE_ORDER == __BIG_ENDIAN
684 uint64_t reserved_17_63 : 47;
685 uint64_t oddpar : 1; /**< Odd parity over STX_SPI4_CAL[15:0]
686 (^STX_SPI4_CAL[16:0] === 1'b1) | $NS NS */
687 uint64_t prt3 : 4; /**< Status for port n+3 */
688 uint64_t prt2 : 4; /**< Status for port n+2 */
689 uint64_t prt1 : 4; /**< Status for port n+1 */
690 uint64_t prt0 : 4; /**< Status for port n+0 */
697 uint64_t reserved_17_63 : 47;
700 struct cvmx_stxx_spi4_calx_s cn38xx;
701 struct cvmx_stxx_spi4_calx_s cn38xxp2;
702 struct cvmx_stxx_spi4_calx_s cn58xx;
703 struct cvmx_stxx_spi4_calx_s cn58xxp1;
705 typedef union cvmx_stxx_spi4_calx cvmx_stxx_spi4_calx_t;
710 * STX_SPI4_DAT - Spi4 datapath channel control register
715 * * DATA_MAX_T must be in MOD 4 cycles
717 * * DATA_MAX_T must at least 0x20
719 * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce
721 * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall
722 * waiting for min bursts to complete. In the worst case, this will
723 * add the entire min burst transmission time to the interval between
724 * trainging sequence. The observed MAX_T on the Spi4 bus will be...
726 * STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4)
728 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
729 * parameter will have to be adjusted. Please see the
730 * STX_SPI4_DAT[MAX_T] section for additional information. In
731 * addition, the min_burst can only be guaranteed on the initial data
732 * burst of a given packet (i.e. the first data burst which contains
733 * the SOP tick). All subsequent bursts could be truncated by training
734 * sequences at any point during transmission and could be arbitrarily
735 * small. This mode is only for use in Spi4 mode.
737 union cvmx_stxx_spi4_dat
740 struct cvmx_stxx_spi4_dat_s
742 #if __BYTE_ORDER == __BIG_ENDIAN
743 uint64_t reserved_32_63 : 32;
744 uint64_t alpha : 16; /**< alpha (from spi4.2 spec) */
745 uint64_t max_t : 16; /**< DATA_MAX_T (from spi4.2 spec) */
749 uint64_t reserved_32_63 : 32;
752 struct cvmx_stxx_spi4_dat_s cn38xx;
753 struct cvmx_stxx_spi4_dat_s cn38xxp2;
754 struct cvmx_stxx_spi4_dat_s cn58xx;
755 struct cvmx_stxx_spi4_dat_s cn58xxp1;
757 typedef union cvmx_stxx_spi4_dat cvmx_stxx_spi4_dat_t;
760 * cvmx_stx#_spi4_stat
762 * STX_SPI4_STAT - Spi4 status channel control register
767 * Both the calendar table and the LEN and M parameters must be
768 * completely setup before writing the Interface enable (INF_EN) and
769 * Status channel enabled (ST_EN) asserted.
771 * The calendar table will only be enabled when LEN > 0.
773 * Current rev will only support LVTTL status IO.
775 union cvmx_stxx_spi4_stat
778 struct cvmx_stxx_spi4_stat_s
780 #if __BYTE_ORDER == __BIG_ENDIAN
781 uint64_t reserved_16_63 : 48;
782 uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */
783 uint64_t reserved_7_7 : 1;
784 uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */
787 uint64_t reserved_7_7 : 1;
789 uint64_t reserved_16_63 : 48;
792 struct cvmx_stxx_spi4_stat_s cn38xx;
793 struct cvmx_stxx_spi4_stat_s cn38xxp2;
794 struct cvmx_stxx_spi4_stat_s cn58xx;
795 struct cvmx_stxx_spi4_stat_s cn58xxp1;
797 typedef union cvmx_stxx_spi4_stat cvmx_stxx_spi4_stat_t;
800 * cvmx_stx#_stat_bytes_hi
802 union cvmx_stxx_stat_bytes_hi
805 struct cvmx_stxx_stat_bytes_hi_s
807 #if __BYTE_ORDER == __BIG_ENDIAN
808 uint64_t reserved_32_63 : 32;
809 uint64_t cnt : 32; /**< Number of bytes sent (CNT[63:32]) */
812 uint64_t reserved_32_63 : 32;
815 struct cvmx_stxx_stat_bytes_hi_s cn38xx;
816 struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
817 struct cvmx_stxx_stat_bytes_hi_s cn58xx;
818 struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
820 typedef union cvmx_stxx_stat_bytes_hi cvmx_stxx_stat_bytes_hi_t;
823 * cvmx_stx#_stat_bytes_lo
825 union cvmx_stxx_stat_bytes_lo
828 struct cvmx_stxx_stat_bytes_lo_s
830 #if __BYTE_ORDER == __BIG_ENDIAN
831 uint64_t reserved_32_63 : 32;
832 uint64_t cnt : 32; /**< Number of bytes sent (CNT[31:0]) */
835 uint64_t reserved_32_63 : 32;
838 struct cvmx_stxx_stat_bytes_lo_s cn38xx;
839 struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
840 struct cvmx_stxx_stat_bytes_lo_s cn58xx;
841 struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
843 typedef union cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_bytes_lo_t;
848 union cvmx_stxx_stat_ctl
851 struct cvmx_stxx_stat_ctl_s
853 #if __BYTE_ORDER == __BIG_ENDIAN
854 uint64_t reserved_5_63 : 59;
855 uint64_t clr : 1; /**< Clear all statistics counters
858 - STX_STAT_BYTES_LO */
859 uint64_t bckprs : 4; /**< The selected port for STX_BCKPRS_CNT */
863 uint64_t reserved_5_63 : 59;
866 struct cvmx_stxx_stat_ctl_s cn38xx;
867 struct cvmx_stxx_stat_ctl_s cn38xxp2;
868 struct cvmx_stxx_stat_ctl_s cn58xx;
869 struct cvmx_stxx_stat_ctl_s cn58xxp1;
871 typedef union cvmx_stxx_stat_ctl cvmx_stxx_stat_ctl_t;
874 * cvmx_stx#_stat_pkt_xmt
876 union cvmx_stxx_stat_pkt_xmt
879 struct cvmx_stxx_stat_pkt_xmt_s
881 #if __BYTE_ORDER == __BIG_ENDIAN
882 uint64_t reserved_32_63 : 32;
883 uint64_t cnt : 32; /**< Number of packets sent */
886 uint64_t reserved_32_63 : 32;
889 struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
890 struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
891 struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
892 struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
894 typedef union cvmx_stxx_stat_pkt_xmt cvmx_stxx_stat_pkt_xmt_t;