2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 * XXX this is virtually the same code as for 5212; we reuse
23 * storage in the 5212 state block; need to refactor.
26 #include "ah_internal.h"
29 #include "ar5416/ar5416.h"
30 #include "ar5416/ar5416reg.h"
31 #include "ar5416/ar5416phy.h"
34 * Anti noise immunity support. We track phy errors and react
35 * to excessive errors by adjusting the noise immunity parameters.
38 #define HAL_EP_RND(x, mul) \
39 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
40 #define BEACON_RSSI(ahp) \
41 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
42 HAL_RSSI_EP_MULTIPLIER)
45 * ANI processing tunes radio parameters according to PHY errors
46 * and related information. This is done for for noise and spur
47 * immunity in all operating modes if the device indicates it's
48 * capable at attach time. In addition, when there is a reference
49 * rssi value (e.g. beacon frames from an ap in station mode)
50 * further tuning is done.
52 * ANI_ENA indicates whether any ANI processing should be done;
53 * this is specified at attach time.
55 * ANI_ENA_RSSI indicates whether rssi-based processing should
56 * done, this is enabled based on operating mode and is meaningful
57 * only if ANI_ENA is true.
59 * ANI parameters are typically controlled only by the hal. The
60 * AniControl interface however permits manual tuning through the
64 (AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)
65 #define ANI_ENA_RSSI(ah) \
66 (AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)
68 #define ah_mibStats ah_stats.ast_mibstats
71 enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)
73 struct ath_hal_5212 *ahp = AH5212(ah);
75 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "
76 "OfdmPhyErrBase 0x%x cckPhyErrBase 0x%x\n",
77 __func__, params->ofdmPhyErrBase, params->cckPhyErrBase);
79 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
80 OS_REG_WRITE(ah, AR_FILTCCK, 0);
82 OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
83 OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
84 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
85 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
87 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save+clear counters*/
88 ar5212EnableMibCounters(ah); /* enable everything */
92 disableAniMIBCounters(struct ath_hal *ah)
94 struct ath_hal_5212 *ahp = AH5212(ah);
96 HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");
98 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save stats */
99 ar5212DisableMibCounters(ah); /* disable everything */
101 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, 0);
102 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, 0);
106 setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)
108 if (params->ofdmTrigHigh >= AR_PHY_COUNTMAX) {
109 HALDEBUG(ah, HAL_DEBUG_ANY,
110 "OFDM Trigger %d is too high for hw counters, using max\n",
111 params->ofdmTrigHigh);
112 params->ofdmPhyErrBase = 0;
114 params->ofdmPhyErrBase = AR_PHY_COUNTMAX - params->ofdmTrigHigh;
115 if (params->cckTrigHigh >= AR_PHY_COUNTMAX) {
116 HALDEBUG(ah, HAL_DEBUG_ANY,
117 "CCK Trigger %d is too high for hw counters, using max\n",
118 params->cckTrigHigh);
119 params->cckPhyErrBase = 0;
121 params->cckPhyErrBase = AR_PHY_COUNTMAX - params->cckTrigHigh;
125 * Setup ANI handling. Sets all thresholds and reset the
126 * channel statistics. Note that ar5416AniReset should be
127 * called by ar5416Reset before anything else happens and
128 * that's where we force initial settings.
131 ar5416AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,
132 const struct ar5212AniParams *params5, HAL_BOOL enable)
134 struct ath_hal_5212 *ahp = AH5212(ah);
136 if (params24 != AH_NULL) {
137 OS_MEMCPY(&ahp->ah_aniParams24, params24, sizeof(*params24));
138 setPhyErrBase(ah, &ahp->ah_aniParams24);
140 if (params5 != AH_NULL) {
141 OS_MEMCPY(&ahp->ah_aniParams5, params5, sizeof(*params5));
142 setPhyErrBase(ah, &ahp->ah_aniParams5);
145 OS_MEMZERO(ahp->ah_ani, sizeof(ahp->ah_ani));
146 /* Enable MIB Counters */
147 enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);
149 if (enable) { /* Enable ani now */
150 HALASSERT(params24 != AH_NULL && params5 != AH_NULL);
151 ahp->ah_procPhyErr |= HAL_ANI_ENA;
153 ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
158 * Cleanup any ANI state setup.
160 * This doesn't restore registers to their default settings!
163 ar5416AniDetach(struct ath_hal *ah)
165 HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");
166 disableAniMIBCounters(ah);
170 * Control Adaptive Noise Immunity Parameters
173 ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
176 struct ath_hal_5212 *ahp = AH5212(ah);
177 struct ar5212AniState *aniState = ahp->ah_curani;
178 const struct ar5212AniParams *params = AH_NULL;
181 * This function may be called before there's a current
182 * channel (eg to disable ANI.)
184 if (aniState != AH_NULL)
185 params = aniState->params;
187 OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);
189 /* These commands can't be disabled */
190 if (cmd == HAL_ANI_PRESENT)
193 if (cmd == HAL_ANI_MODE) {
195 ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
196 /* Turn off HW counters if we have them */
198 } else { /* normal/auto mode */
199 /* don't mess with state if already enabled */
200 if (! (ahp->ah_procPhyErr & HAL_ANI_ENA)) {
201 /* Enable MIB Counters */
203 * XXX use 2.4ghz params if no channel is
206 enableAniMIBCounters(ah,
207 ahp->ah_curani != AH_NULL ?
208 ahp->ah_curani->params:
209 &ahp->ah_aniParams24);
210 ahp->ah_procPhyErr |= HAL_ANI_ENA;
216 /* Check whether the particular function is enabled */
217 if (((1 << cmd) & AH5416(ah)->ah_ani_function) == 0) {
218 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: command %d disabled\n",
220 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: cmd %d; mask %x\n", __func__, cmd, AH5416(ah)->ah_ani_function);
226 case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
229 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_NOISE_IMMUNITY_LEVEL: set level = %d\n", __func__, level);
230 if (level >= params->maxNoiseImmunityLevel) {
231 HALDEBUG(ah, HAL_DEBUG_ANI,
232 "%s: immunity level out of range (%u > %u)\n",
233 __func__, level, params->maxNoiseImmunityLevel);
237 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
238 AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]);
239 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
240 AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]);
241 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
242 AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]);
243 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
244 AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]);
246 if (level > aniState->noiseImmunityLevel)
247 ahp->ah_stats.ast_ani_niup++;
248 else if (level < aniState->noiseImmunityLevel)
249 ahp->ah_stats.ast_ani_nidown++;
250 aniState->noiseImmunityLevel = level;
253 case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {
254 static const TABLE m1ThreshLow = { 127, 50 };
255 static const TABLE m2ThreshLow = { 127, 40 };
256 static const TABLE m1Thresh = { 127, 0x4d };
257 static const TABLE m2Thresh = { 127, 0x40 };
258 static const TABLE m2CountThr = { 31, 16 };
259 static const TABLE m2CountThrLow = { 63, 48 };
260 u_int on = param ? 1 : 0;
262 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: %s\n", __func__, on ? "enabled" : "disabled");
263 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
264 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);
265 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
266 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);
267 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
268 AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
269 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
270 AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
271 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
272 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
273 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
274 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
276 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
277 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
278 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
279 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
280 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
281 AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
282 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
283 AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
286 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
287 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
289 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
290 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
293 ahp->ah_stats.ast_ani_ofdmon++;
295 ahp->ah_stats.ast_ani_ofdmoff++;
296 aniState->ofdmWeakSigDetectOff = !on;
299 case HAL_ANI_CCK_WEAK_SIGNAL_THR: {
300 static const TABLE weakSigThrCck = { 8, 6 };
301 u_int high = param ? 1 : 0;
303 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_CCK_WEAK_SIGNAL_THR: %s\n", __func__, high ? "high" : "low");
304 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
305 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]);
307 ahp->ah_stats.ast_ani_cckhigh++;
309 ahp->ah_stats.ast_ani_ccklow++;
310 aniState->cckWeakSigThreshold = high;
313 case HAL_ANI_FIRSTEP_LEVEL: {
316 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_FIRSTEP_LEVEL: level = %d\n", __func__, level);
317 if (level >= params->maxFirstepLevel) {
318 HALDEBUG(ah, HAL_DEBUG_ANI,
319 "%s: firstep level out of range (%u > %u)\n",
320 __func__, level, params->maxFirstepLevel);
323 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
324 AR_PHY_FIND_SIG_FIRSTEP, params->firstep[level]);
325 if (level > aniState->firstepLevel)
326 ahp->ah_stats.ast_ani_stepup++;
327 else if (level < aniState->firstepLevel)
328 ahp->ah_stats.ast_ani_stepdown++;
329 aniState->firstepLevel = level;
332 case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
335 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: HAL_ANI_SPUR_IMMUNITY_LEVEL: level = %d\n", __func__, level);
336 if (level >= params->maxSpurImmunityLevel) {
337 HALDEBUG(ah, HAL_DEBUG_ANI,
338 "%s: spur immunity level out of range (%u > %u)\n",
339 __func__, level, params->maxSpurImmunityLevel);
342 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
343 AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]);
345 /* Only set the ext channel cycpwr_thr1 field for ht/40 */
346 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan))
347 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
348 AR_PHY_EXT_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]);
350 if (level > aniState->spurImmunityLevel)
351 ahp->ah_stats.ast_ani_spurup++;
352 else if (level < aniState->spurImmunityLevel)
353 ahp->ah_stats.ast_ani_spurdown++;
354 aniState->spurImmunityLevel = level;
357 #ifdef AH_PRIVATE_DIAG
358 case HAL_ANI_PHYERR_RESET:
359 ahp->ah_stats.ast_ani_ofdmerrs = 0;
360 ahp->ah_stats.ast_ani_cckerrs = 0;
362 #endif /* AH_PRIVATE_DIAG */
364 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: invalid cmd %u\n",
372 ar5416AniOfdmErrTrigger(struct ath_hal *ah)
374 struct ath_hal_5212 *ahp = AH5212(ah);
375 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
376 struct ar5212AniState *aniState;
377 const struct ar5212AniParams *params;
379 HALASSERT(chan != AH_NULL);
384 aniState = ahp->ah_curani;
385 params = aniState->params;
386 /* First, raise noise immunity level, up to max */
387 if ((AH5416(ah)->ah_ani_function & (1 << HAL_ANI_NOISE_IMMUNITY_LEVEL)) &&
388 (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel)) {
389 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
390 aniState->noiseImmunityLevel + 1);
393 /* then, raise spur immunity level, up to max */
394 if ((AH5416(ah)->ah_ani_function & (1 << HAL_ANI_SPUR_IMMUNITY_LEVEL)) &&
395 (aniState->spurImmunityLevel+1 < params->maxSpurImmunityLevel)) {
396 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
397 aniState->spurImmunityLevel + 1);
401 if (ANI_ENA_RSSI(ah)) {
402 int32_t rssi = BEACON_RSSI(ahp);
403 if (rssi > params->rssiThrHigh) {
405 * Beacon rssi is high, can turn off ofdm
408 if (!aniState->ofdmWeakSigDetectOff) {
410 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
413 HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
417 * If weak sig detect is already off, as last resort,
418 * raise firstep level
420 if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
421 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
422 aniState->firstepLevel + 1);
425 } else if (rssi > params->rssiThrLow) {
427 * Beacon rssi in mid range, need ofdm weak signal
428 * detect, but we can raise firststepLevel.
430 if (aniState->ofdmWeakSigDetectOff)
432 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
434 if (aniState->firstepLevel+1 < params->maxFirstepLevel)
435 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
436 aniState->firstepLevel + 1);
440 * Beacon rssi is low, if in 11b/g mode, turn off ofdm
441 * weak signal detection and zero firstepLevel to
442 * maximize CCK sensitivity
444 if (IEEE80211_IS_CHAN_CCK(chan)) {
445 if (!aniState->ofdmWeakSigDetectOff)
447 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
449 if (aniState->firstepLevel > 0)
451 HAL_ANI_FIRSTEP_LEVEL, 0);
459 ar5416AniCckErrTrigger(struct ath_hal *ah)
461 struct ath_hal_5212 *ahp = AH5212(ah);
462 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
463 struct ar5212AniState *aniState;
464 const struct ar5212AniParams *params;
466 HALASSERT(chan != AH_NULL);
471 /* first, raise noise immunity level, up to max */
472 aniState = ahp->ah_curani;
473 params = aniState->params;
474 if ((AH5416(ah)->ah_ani_function & (1 << HAL_ANI_NOISE_IMMUNITY_LEVEL) &&
475 aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel)) {
476 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
477 aniState->noiseImmunityLevel + 1);
481 if (ANI_ENA_RSSI(ah)) {
482 int32_t rssi = BEACON_RSSI(ahp);
483 if (rssi > params->rssiThrLow) {
485 * Beacon signal in mid and high range,
486 * raise firstep level.
488 if (aniState->firstepLevel+1 < params->maxFirstepLevel)
489 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
490 aniState->firstepLevel + 1);
493 * Beacon rssi is low, zero firstep level to maximize
494 * CCK sensitivity in 11b/g mode.
496 if (IEEE80211_IS_CHAN_CCK(chan)) {
497 if (aniState->firstepLevel > 0)
499 HAL_ANI_FIRSTEP_LEVEL, 0);
506 ar5416AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
508 struct ath_hal_5212 *ahp = AH5212(ah);
509 const struct ar5212AniParams *params = aniState->params;
511 aniState->listenTime = 0;
513 * NB: these are written on reset based on the
514 * ini so we must re-write them!
516 HALDEBUG(ah, HAL_DEBUG_ANI,
517 "%s: Writing ofdmbase=%u cckbase=%u\n", __func__,
518 params->ofdmPhyErrBase, params->cckPhyErrBase);
519 OS_REG_WRITE(ah, AR_PHY_ERR_1, params->ofdmPhyErrBase);
520 OS_REG_WRITE(ah, AR_PHY_ERR_2, params->cckPhyErrBase);
521 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
522 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
524 /* Clear the mib counters and save them in the stats */
525 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
526 aniState->ofdmPhyErrCount = 0;
527 aniState->cckPhyErrCount = 0;
531 * Restore/reset the ANI parameters and reset the statistics.
532 * This routine must be called for every channel change.
534 * NOTE: This is where ah_curani is set; other ani code assumes
535 * it is setup to reflect the current channel.
538 ar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,
539 HAL_OPMODE opmode, int restore)
541 struct ath_hal_5212 *ahp = AH5212(ah);
542 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
543 /* XXX bounds check ic_devdata */
544 struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];
547 if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {
548 OS_MEMZERO(aniState, sizeof(*aniState));
549 if (IEEE80211_IS_CHAN_2GHZ(chan))
550 aniState->params = &ahp->ah_aniParams24;
552 aniState->params = &ahp->ah_aniParams5;
553 ichan->privFlags |= CHANNEL_ANI_INIT;
554 HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);
556 ahp->ah_curani = aniState;
558 ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",
559 __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
560 ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
562 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",
563 __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
564 ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
566 OS_MARK(ah, AH_MARK_ANI_RESET, opmode);
569 * Turn off PHY error frame delivery while we futz with settings.
571 rxfilter = ah->ah_getRxFilter(ah);
572 ah->ah_setRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);
575 * If ANI is disabled at this point, don't set the default
576 * ANI parameter settings - leave the HAL settings there.
577 * This is (currently) needed for reliable radar detection.
580 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ANI disabled\n",
587 * Automatic processing is done only in station mode right now.
589 if (opmode == HAL_M_STA)
590 ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;
592 ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;
594 * Set all ani parameters. We either set them to initial
595 * values or restore the previous ones for the channel.
596 * XXX if ANI follows hardware, we don't care what mode we're
597 * XXX in, we should keep the ani parameters
599 if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {
600 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
601 aniState->noiseImmunityLevel);
602 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
603 aniState->spurImmunityLevel);
604 ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
605 !aniState->ofdmWeakSigDetectOff);
606 ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
607 aniState->cckWeakSigThreshold);
608 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
609 aniState->firstepLevel);
611 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
612 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
613 ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
615 ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
616 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
617 ichan->privFlags |= CHANNEL_ANI_SETUP;
621 * In case the counters haven't yet been setup; set them up.
623 enableAniMIBCounters(ah, aniState->params);
624 ar5416AniRestart(ah, aniState);
627 /* restore RX filter mask */
628 ah->ah_setRxFilter(ah, rxfilter);
632 * Process a MIB interrupt. We may potentially be invoked because
633 * any of the MIB counters overflow/trigger so don't assume we're
634 * here because a PHY error counter triggered.
637 ar5416ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
639 struct ath_hal_5212 *ahp = AH5212(ah);
640 uint32_t phyCnt1, phyCnt2;
642 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "
643 "filtofdm 0x%x filtcck 0x%x\n",
644 __func__, OS_REG_READ(ah, AR_MIBC),
645 OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
646 OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
649 * First order of business is to clear whatever caused
650 * the interrupt so we don't keep getting interrupted.
651 * We have the usual mib counters that are reset-on-read
652 * and the additional counters that appeared starting in
653 * Hainan. We collect the mib counters and explicitly
654 * zero additional counters we are not using. Anything
655 * else is reset only if it caused the interrupt.
657 /* NB: these are not reset-on-read */
658 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
659 phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
660 /* not used, always reset them in case they are the cause */
661 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
662 OS_REG_WRITE(ah, AR_FILTCCK, 0);
663 if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)
664 OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
666 /* Clear the mib counters and save them in the stats */
667 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
668 ahp->ah_stats.ast_nodestats = *stats;
671 * Check for an ani stat hitting the trigger threshold.
672 * When this happens we get a MIB interrupt and the top
673 * 2 bits of the counter register will be 0b11, hence
674 * the mask check of phyCnt?.
676 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
677 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
678 struct ar5212AniState *aniState = ahp->ah_curani;
679 const struct ar5212AniParams *params = aniState->params;
680 uint32_t ofdmPhyErrCnt, cckPhyErrCnt;
682 ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
683 ahp->ah_stats.ast_ani_ofdmerrs +=
684 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
685 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
687 cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
688 ahp->ah_stats.ast_ani_cckerrs +=
689 cckPhyErrCnt - aniState->cckPhyErrCount;
690 aniState->cckPhyErrCount = cckPhyErrCnt;
693 * NB: figure out which counter triggered. If both
694 * trigger we'll only deal with one as the processing
695 * clobbers the error counter so the trigger threshold
696 * check will never be true.
698 if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh)
699 ar5416AniOfdmErrTrigger(ah);
700 if (aniState->cckPhyErrCount > params->cckTrigHigh)
701 ar5416AniCckErrTrigger(ah);
702 /* NB: always restart to insure the h/w counters are reset */
703 ar5416AniRestart(ah, aniState);
708 ar5416AniLowerImmunity(struct ath_hal *ah)
710 struct ath_hal_5212 *ahp = AH5212(ah);
711 struct ar5212AniState *aniState;
712 const struct ar5212AniParams *params;
714 HALASSERT(ANI_ENA(ah));
716 aniState = ahp->ah_curani;
717 params = aniState->params;
718 if (ANI_ENA_RSSI(ah)) {
719 int32_t rssi = BEACON_RSSI(ahp);
720 if (rssi > params->rssiThrHigh) {
722 * Beacon signal is high, leave ofdm weak signal
723 * detection off or it may oscillate. Let it fall
726 } else if (rssi > params->rssiThrLow) {
728 * Beacon rssi in mid range, turn on ofdm weak signal
729 * detection or lower firstep level.
731 if (aniState->ofdmWeakSigDetectOff) {
733 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
737 if (aniState->firstepLevel > 0) {
738 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
739 aniState->firstepLevel - 1);
744 * Beacon rssi is low, reduce firstep level.
746 if (aniState->firstepLevel > 0) {
747 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
748 aniState->firstepLevel - 1);
753 /* then lower spur immunity level, down to zero */
754 if (aniState->spurImmunityLevel > 0) {
755 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
756 aniState->spurImmunityLevel - 1);
760 * if all else fails, lower noise immunity level down to a min value
763 if (aniState->noiseImmunityLevel > 0) {
764 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
765 aniState->noiseImmunityLevel - 1);
770 #define CLOCK_RATE 44000 /* XXX use mac_usec or similar */
771 /* convert HW counter values to ms using 11g clock rate, goo9d enough
775 * Return an approximation of the time spent ``listening'' by
776 * deducting the cycles spent tx'ing and rx'ing from the total
777 * cycle count since our last call. A return value <0 indicates
778 * an invalid/inconsistent time.
781 ar5416AniGetListenTime(struct ath_hal *ah)
783 struct ath_hal_5212 *ahp = AH5212(ah);
784 struct ar5212AniState *aniState;
785 uint32_t txFrameCount, rxFrameCount, cycleCount;
788 txFrameCount = OS_REG_READ(ah, AR_TFCNT);
789 rxFrameCount = OS_REG_READ(ah, AR_RFCNT);
790 cycleCount = OS_REG_READ(ah, AR_CCCNT);
792 aniState = ahp->ah_curani;
793 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
795 * Cycle counter wrap (or initial call); it's not possible
796 * to accurately calculate a value because the registers
797 * right shift rather than wrap--so punt and return 0.
800 ahp->ah_stats.ast_ani_lzero++;
802 int32_t ccdelta = cycleCount - aniState->cycleCount;
803 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
804 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
805 listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE;
807 aniState->cycleCount = cycleCount;
808 aniState->txFrameCount = txFrameCount;
809 aniState->rxFrameCount = rxFrameCount;
814 * Update ani stats in preparation for listen time processing.
817 updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
819 struct ath_hal_5212 *ahp = AH5212(ah);
820 const struct ar5212AniParams *params = aniState->params;
821 uint32_t phyCnt1, phyCnt2;
822 int32_t ofdmPhyErrCnt, cckPhyErrCnt;
824 /* Clear the mib counters and save them in the stats */
825 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
827 /* NB: these are not reset-on-read */
828 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
829 phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
831 /* NB: these are spec'd to never roll-over */
832 ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
833 if (ofdmPhyErrCnt < 0) {
834 HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",
835 ofdmPhyErrCnt, phyCnt1);
836 ofdmPhyErrCnt = AR_PHY_COUNTMAX;
838 ahp->ah_stats.ast_ani_ofdmerrs +=
839 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
840 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
842 cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
843 if (cckPhyErrCnt < 0) {
844 HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",
845 cckPhyErrCnt, phyCnt2);
846 cckPhyErrCnt = AR_PHY_COUNTMAX;
848 ahp->ah_stats.ast_ani_cckerrs +=
849 cckPhyErrCnt - aniState->cckPhyErrCount;
850 aniState->cckPhyErrCount = cckPhyErrCnt;
854 ar5416RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,
855 const struct ieee80211_channel *chan)
857 struct ath_hal_5212 *ahp = AH5212(ah);
858 ahp->ah_stats.ast_nodestats.ns_avgbrssi = stats->ns_avgbrssi;
862 * Do periodic processing. This routine is called from the
863 * driver's rx interrupt handler after processing frames.
866 ar5416AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)
868 struct ath_hal_5212 *ahp = AH5212(ah);
869 struct ar5212AniState *aniState = ahp->ah_curani;
870 const struct ar5212AniParams *params;
873 /* XXX can aniState be null? */
874 if (aniState == AH_NULL)
879 listenTime = ar5416AniGetListenTime(ah);
880 if (listenTime < 0) {
881 ahp->ah_stats.ast_ani_lneg++;
882 /* restart ANI period if listenTime is invalid */
883 ar5416AniRestart(ah, aniState);
885 /* XXX beware of overflow? */
886 aniState->listenTime += listenTime;
888 OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);
890 params = aniState->params;
891 if (aniState->listenTime > 5*params->period) {
893 * Check to see if need to lower immunity if
894 * 5 aniPeriods have passed
896 updateMIBStats(ah, aniState);
897 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
898 params->ofdmTrigLow/1000 &&
899 aniState->cckPhyErrCount <= aniState->listenTime *
900 params->cckTrigLow/1000)
901 ar5416AniLowerImmunity(ah);
902 ar5416AniRestart(ah, aniState);
903 } else if (aniState->listenTime > params->period) {
904 updateMIBStats(ah, aniState);
905 /* check to see if need to raise immunity */
906 if (aniState->ofdmPhyErrCount > aniState->listenTime *
907 params->ofdmTrigHigh / 1000) {
908 HALDEBUG(ah, HAL_DEBUG_ANI,
909 "%s: OFDM err %u listenTime %u\n", __func__,
910 aniState->ofdmPhyErrCount, aniState->listenTime);
911 ar5416AniOfdmErrTrigger(ah);
912 ar5416AniRestart(ah, aniState);
913 } else if (aniState->cckPhyErrCount > aniState->listenTime *
914 params->cckTrigHigh / 1000) {
915 HALDEBUG(ah, HAL_DEBUG_ANI,
916 "%s: CCK err %u listenTime %u\n", __func__,
917 aniState->ofdmPhyErrCount, aniState->listenTime);
918 ar5416AniCckErrTrigger(ah);
919 ar5416AniRestart(ah, aniState);