5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This file contains the driver for the AT91 series USB Device
35 * Thanks to "David Brownell" for helping out regarding the hardware
40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is
43 * NOTE: When the chip detects BUS-reset it will also reset the
44 * endpoints, Function-address and more.
47 #include <sys/stdint.h>
48 #include <sys/stddef.h>
49 #include <sys/param.h>
50 #include <sys/queue.h>
51 #include <sys/types.h>
52 #include <sys/systm.h>
53 #include <sys/kernel.h>
55 #include <sys/module.h>
57 #include <sys/mutex.h>
58 #include <sys/condvar.h>
59 #include <sys/sysctl.h>
61 #include <sys/unistd.h>
62 #include <sys/callout.h>
63 #include <sys/malloc.h>
66 #include <dev/usb/usb.h>
67 #include <dev/usb/usbdi.h>
69 #define USB_DEBUG_VAR at91dcidebug
71 #include <dev/usb/usb_core.h>
72 #include <dev/usb/usb_debug.h>
73 #include <dev/usb/usb_busdma.h>
74 #include <dev/usb/usb_process.h>
75 #include <dev/usb/usb_transfer.h>
76 #include <dev/usb/usb_device.h>
77 #include <dev/usb/usb_hub.h>
78 #include <dev/usb/usb_util.h>
80 #include <dev/usb/usb_controller.h>
81 #include <dev/usb/usb_bus.h>
82 #include <dev/usb/controller/at91dci.h>
84 #define AT9100_DCI_BUS2SC(bus) \
85 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \
86 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus))))
88 #define AT9100_DCI_PC2SC(pc) \
89 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
92 static int at91dcidebug = 0;
94 SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci");
95 SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW,
96 &at91dcidebug, 0, "at91dci debug level");
99 #define AT9100_DCI_INTR_ENDPT 1
103 struct usb_bus_methods at91dci_bus_methods;
104 struct usb_pipe_methods at91dci_device_bulk_methods;
105 struct usb_pipe_methods at91dci_device_ctrl_methods;
106 struct usb_pipe_methods at91dci_device_intr_methods;
107 struct usb_pipe_methods at91dci_device_isoc_fs_methods;
109 static at91dci_cmd_t at91dci_setup_rx;
110 static at91dci_cmd_t at91dci_data_rx;
111 static at91dci_cmd_t at91dci_data_tx;
112 static at91dci_cmd_t at91dci_data_tx_sync;
113 static void at91dci_device_done(struct usb_xfer *, usb_error_t);
114 static void at91dci_do_poll(struct usb_bus *);
115 static void at91dci_standard_done(struct usb_xfer *);
116 static void at91dci_root_intr(struct at91dci_softc *sc);
119 * NOTE: Some of the bits in the CSR register have inverse meaning so
120 * we need a helper macro when acknowledging events:
122 #define AT91_CSR_ACK(csr, what) do { \
123 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \
124 AT91_UDP_CSR_TXPKTRDY| \
125 AT91_UDP_CSR_RXBYTECNT) ^ (what));\
126 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \
127 AT91_UDP_CSR_RX_DATA_BK1| \
128 AT91_UDP_CSR_TXCOMP| \
129 AT91_UDP_CSR_RXSETUP| \
130 AT91_UDP_CSR_STALLSENT) ^ (what)); \
134 * Here is a list of what the chip supports.
135 * Probably it supports more than listed here!
137 static const struct usb_hw_ep_profile
138 at91dci_ep_profile[AT91_UDP_EP_MAX] = {
141 .max_in_frame_size = 8,
142 .max_out_frame_size = 8,
144 .support_control = 1,
147 .max_in_frame_size = 64,
148 .max_out_frame_size = 64,
150 .support_multi_buffer = 1,
152 .support_interrupt = 1,
153 .support_isochronous = 1,
158 .max_in_frame_size = 64,
159 .max_out_frame_size = 64,
161 .support_multi_buffer = 1,
163 .support_interrupt = 1,
164 .support_isochronous = 1,
169 /* can also do BULK */
170 .max_in_frame_size = 8,
171 .max_out_frame_size = 8,
173 .support_interrupt = 1,
178 .max_in_frame_size = 256,
179 .max_out_frame_size = 256,
181 .support_multi_buffer = 1,
183 .support_interrupt = 1,
184 .support_isochronous = 1,
189 .max_in_frame_size = 256,
190 .max_out_frame_size = 256,
192 .support_multi_buffer = 1,
194 .support_interrupt = 1,
195 .support_isochronous = 1,
202 at91dci_get_hw_ep_profile(struct usb_device *udev,
203 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
205 if (ep_addr < AT91_UDP_EP_MAX) {
206 *ppf = (at91dci_ep_profile + ep_addr);
213 at91dci_clocks_on(struct at91dci_softc *sc)
215 if (sc->sc_flags.clocks_off &&
216 sc->sc_flags.port_powered) {
220 if (sc->sc_clocks_on) {
221 (sc->sc_clocks_on) (sc->sc_clocks_arg);
223 sc->sc_flags.clocks_off = 0;
225 /* enable Transceiver */
226 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0);
231 at91dci_clocks_off(struct at91dci_softc *sc)
233 if (!sc->sc_flags.clocks_off) {
237 /* disable Transceiver */
238 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS);
240 if (sc->sc_clocks_off) {
241 (sc->sc_clocks_off) (sc->sc_clocks_arg);
243 sc->sc_flags.clocks_off = 1;
248 at91dci_pull_up(struct at91dci_softc *sc)
250 /* pullup D+, if possible */
252 if (!sc->sc_flags.d_pulled_up &&
253 sc->sc_flags.port_powered) {
254 sc->sc_flags.d_pulled_up = 1;
255 (sc->sc_pull_up) (sc->sc_pull_arg);
260 at91dci_pull_down(struct at91dci_softc *sc)
262 /* pulldown D+, if possible */
264 if (sc->sc_flags.d_pulled_up) {
265 sc->sc_flags.d_pulled_up = 0;
266 (sc->sc_pull_down) (sc->sc_pull_arg);
271 at91dci_wakeup_peer(struct at91dci_softc *sc)
273 if (!(sc->sc_flags.status_suspend)) {
277 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR);
279 /* wait 8 milliseconds */
280 /* Wait for reset to complete. */
281 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
283 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0);
287 at91dci_set_address(struct at91dci_softc *sc, uint8_t addr)
289 DPRINTFN(5, "addr=%d\n", addr);
291 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr |
296 at91dci_setup_rx(struct at91dci_td *td)
298 struct at91dci_softc *sc;
299 struct usb_device_request req;
304 /* read out FIFO status */
305 csr = bus_space_read_4(td->io_tag, td->io_hdl,
308 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
311 temp &= (AT91_UDP_CSR_RX_DATA_BK0 |
312 AT91_UDP_CSR_RX_DATA_BK1 |
313 AT91_UDP_CSR_STALLSENT |
314 AT91_UDP_CSR_RXSETUP |
315 AT91_UDP_CSR_TXCOMP);
317 if (!(csr & AT91_UDP_CSR_RXSETUP)) {
320 /* clear did stall */
323 /* get the packet byte count */
324 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
326 /* verify data length */
327 if (count != td->remainder) {
328 DPRINTFN(0, "Invalid SETUP packet "
329 "length, %d bytes\n", count);
332 if (count != sizeof(req)) {
333 DPRINTFN(0, "Unsupported SETUP packet "
334 "length, %d bytes\n", count);
338 bus_space_read_multi_1(td->io_tag, td->io_hdl,
339 td->fifo_reg, (void *)&req, sizeof(req));
341 /* copy data into real buffer */
342 usbd_copy_in(td->pc, 0, &req, sizeof(req));
344 td->offset = sizeof(req);
347 /* get pointer to softc */
348 sc = AT9100_DCI_PC2SC(td->pc);
350 /* sneak peek the set address */
351 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
352 (req.bRequest == UR_SET_ADDRESS)) {
353 sc->sc_dv_addr = req.wValue[0] & 0x7F;
355 sc->sc_dv_addr = 0xFF;
358 /* sneak peek the endpoint direction */
359 if (req.bmRequestType & UE_DIR_IN) {
360 csr |= AT91_UDP_CSR_DIR;
362 csr &= ~AT91_UDP_CSR_DIR;
365 /* write the direction of the control transfer */
366 AT91_CSR_ACK(csr, temp);
367 bus_space_write_4(td->io_tag, td->io_hdl,
368 td->status_reg, csr);
369 return (0); /* complete */
372 /* abort any ongoing transfer */
373 if (!td->did_stall) {
374 DPRINTFN(5, "stalling\n");
375 temp |= AT91_UDP_CSR_FORCESTALL;
379 /* clear interrupts, if any */
381 DPRINTFN(5, "clearing 0x%08x\n", temp);
382 AT91_CSR_ACK(csr, temp);
383 bus_space_write_4(td->io_tag, td->io_hdl,
384 td->status_reg, csr);
386 return (1); /* not complete */
391 at91dci_data_rx(struct at91dci_td *td)
393 struct usb_page_search buf_res;
400 to = 2; /* don't loop forever! */
403 /* check if any of the FIFO banks have data */
405 /* read out FIFO status */
406 csr = bus_space_read_4(td->io_tag, td->io_hdl,
409 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
411 if (csr & AT91_UDP_CSR_RXSETUP) {
412 if (td->remainder == 0) {
414 * We are actually complete and have
415 * received the next SETUP
417 DPRINTFN(5, "faking complete\n");
418 return (0); /* complete */
421 * USB Host Aborted the transfer.
424 return (0); /* complete */
426 /* Make sure that "STALLSENT" gets cleared */
428 temp &= AT91_UDP_CSR_STALLSENT;
431 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 |
432 AT91_UDP_CSR_RX_DATA_BK1))) {
435 AT91_CSR_ACK(csr, temp);
436 bus_space_write_4(td->io_tag, td->io_hdl,
437 td->status_reg, csr);
439 return (1); /* not complete */
441 /* get the packet byte count */
442 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
444 /* verify the packet byte count */
445 if (count != td->max_packet_size) {
446 if (count < td->max_packet_size) {
447 /* we have a short packet */
451 /* invalid USB packet */
453 return (0); /* we are complete */
456 /* verify the packet byte count */
457 if (count > td->remainder) {
458 /* invalid USB packet */
460 return (0); /* we are complete */
463 usbd_get_page(td->pc, td->offset, &buf_res);
465 /* get correct length */
466 if (buf_res.length > count) {
467 buf_res.length = count;
470 bus_space_read_multi_1(td->io_tag, td->io_hdl,
471 td->fifo_reg, buf_res.buffer, buf_res.length);
473 /* update counters */
474 count -= buf_res.length;
475 td->offset += buf_res.length;
476 td->remainder -= buf_res.length;
479 /* clear status bits */
480 if (td->support_multi_buffer) {
483 temp |= AT91_UDP_CSR_RX_DATA_BK1;
486 temp |= AT91_UDP_CSR_RX_DATA_BK0;
489 temp |= (AT91_UDP_CSR_RX_DATA_BK0 |
490 AT91_UDP_CSR_RX_DATA_BK1);
494 AT91_CSR_ACK(csr, temp);
495 bus_space_write_4(td->io_tag, td->io_hdl,
496 td->status_reg, csr);
499 * NOTE: We may have to delay a little bit before
500 * proceeding after clearing the DATA_BK bits.
503 /* check if we are complete */
504 if ((td->remainder == 0) || got_short) {
506 /* we are complete */
509 /* else need to receive a zero length packet */
514 return (1); /* not complete */
518 at91dci_data_tx(struct at91dci_td *td)
520 struct usb_page_search buf_res;
526 to = 2; /* don't loop forever! */
530 /* read out FIFO status */
531 csr = bus_space_read_4(td->io_tag, td->io_hdl,
534 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
536 if (csr & AT91_UDP_CSR_RXSETUP) {
538 * The current transfer was aborted
542 return (0); /* complete */
544 /* Make sure that "STALLSENT" gets cleared */
546 temp &= AT91_UDP_CSR_STALLSENT;
548 if (csr & AT91_UDP_CSR_TXPKTRDY) {
551 AT91_CSR_ACK(csr, temp);
552 bus_space_write_4(td->io_tag, td->io_hdl,
553 td->status_reg, csr);
555 return (1); /* not complete */
557 /* clear TXCOMP and set TXPKTRDY */
558 temp |= (AT91_UDP_CSR_TXCOMP |
559 AT91_UDP_CSR_TXPKTRDY);
562 count = td->max_packet_size;
563 if (td->remainder < count) {
564 /* we have a short packet */
566 count = td->remainder;
570 usbd_get_page(td->pc, td->offset, &buf_res);
572 /* get correct length */
573 if (buf_res.length > count) {
574 buf_res.length = count;
577 bus_space_write_multi_1(td->io_tag, td->io_hdl,
578 td->fifo_reg, buf_res.buffer, buf_res.length);
580 /* update counters */
581 count -= buf_res.length;
582 td->offset += buf_res.length;
583 td->remainder -= buf_res.length;
587 AT91_CSR_ACK(csr, temp);
588 bus_space_write_4(td->io_tag, td->io_hdl,
589 td->status_reg, csr);
591 /* check remainder */
592 if (td->remainder == 0) {
594 return (0); /* complete */
596 /* else we need to transmit a short packet */
601 return (1); /* not complete */
605 at91dci_data_tx_sync(struct at91dci_td *td)
607 struct at91dci_softc *sc;
615 /* read out FIFO status */
616 csr = bus_space_read_4(td->io_tag, td->io_hdl,
619 DPRINTFN(5, "csr=0x%08x\n", csr);
621 if (csr & AT91_UDP_CSR_RXSETUP) {
622 DPRINTFN(5, "faking complete\n");
624 return (0); /* complete */
627 temp &= (AT91_UDP_CSR_STALLSENT |
628 AT91_UDP_CSR_TXCOMP);
631 if (csr & AT91_UDP_CSR_TXPKTRDY) {
634 if (!(csr & AT91_UDP_CSR_TXCOMP)) {
637 sc = AT9100_DCI_PC2SC(td->pc);
638 if (sc->sc_dv_addr != 0xFF) {
640 * The AT91 has a special requirement with regard to
641 * setting the address and that is to write the new
642 * address before clearing TXCOMP:
644 at91dci_set_address(sc, sc->sc_dv_addr);
647 AT91_CSR_ACK(csr, temp);
648 bus_space_write_4(td->io_tag, td->io_hdl,
649 td->status_reg, csr);
651 return (0); /* complete */
656 AT91_CSR_ACK(csr, temp);
657 bus_space_write_4(td->io_tag, td->io_hdl,
658 td->status_reg, csr);
660 return (1); /* not complete */
664 at91dci_xfer_do_fifo(struct usb_xfer *xfer)
666 struct at91dci_softc *sc;
667 struct at91dci_td *td;
672 td = xfer->td_transfer_cache;
674 if ((td->func) (td)) {
675 /* operation in progress */
678 if (((void *)td) == xfer->td_transfer_last) {
683 } else if (td->remainder > 0) {
685 * We had a short transfer. If there is no alternate
686 * next, stop processing !
693 * Fetch the next transfer descriptor and transfer
694 * some flags to the next transfer descriptor
700 xfer->td_transfer_cache = td;
704 return (1); /* not complete */
707 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
708 temp = (xfer->endpointno & UE_ADDR);
710 /* update FIFO bank flag and multi buffer */
712 sc->sc_ep_flags[temp].fifo_bank = 1;
714 sc->sc_ep_flags[temp].fifo_bank = 0;
717 /* compute all actual lengths */
719 at91dci_standard_done(xfer);
721 return (0); /* complete */
725 at91dci_interrupt_poll(struct at91dci_softc *sc)
727 struct usb_xfer *xfer;
730 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
731 if (!at91dci_xfer_do_fifo(xfer)) {
732 /* queue has been modified */
739 at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on)
741 DPRINTFN(5, "vbus = %u\n", is_on);
743 USB_BUS_LOCK(&sc->sc_bus);
745 if (!sc->sc_flags.status_vbus) {
746 sc->sc_flags.status_vbus = 1;
748 /* complete root HUB interrupt endpoint */
749 at91dci_root_intr(sc);
752 if (sc->sc_flags.status_vbus) {
753 sc->sc_flags.status_vbus = 0;
754 sc->sc_flags.status_bus_reset = 0;
755 sc->sc_flags.status_suspend = 0;
756 sc->sc_flags.change_suspend = 0;
757 sc->sc_flags.change_connect = 1;
759 /* complete root HUB interrupt endpoint */
760 at91dci_root_intr(sc);
763 USB_BUS_UNLOCK(&sc->sc_bus);
767 at91dci_interrupt(struct at91dci_softc *sc)
771 USB_BUS_LOCK(&sc->sc_bus);
773 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR);
774 status &= AT91_UDP_INT_DEFAULT;
777 USB_BUS_UNLOCK(&sc->sc_bus);
780 /* acknowledge interrupts */
782 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status);
784 /* check for any bus state change interrupts */
786 if (status & AT91_UDP_INT_BUS) {
788 DPRINTFN(5, "real bus interrupt 0x%08x\n", status);
790 if (status & AT91_UDP_INT_END_BR) {
792 /* set correct state */
793 sc->sc_flags.status_bus_reset = 1;
794 sc->sc_flags.status_suspend = 0;
795 sc->sc_flags.change_suspend = 0;
796 sc->sc_flags.change_connect = 1;
798 /* disable resume interrupt */
799 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
801 /* enable suspend interrupt */
802 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
803 AT91_UDP_INT_RXSUSP);
806 * If RXRSM and RXSUSP is set at the same time we interpret
807 * that like RESUME. Resume is set when there is at least 3
808 * milliseconds of inactivity on the USB BUS.
810 if (status & AT91_UDP_INT_RXRSM) {
811 if (sc->sc_flags.status_suspend) {
812 sc->sc_flags.status_suspend = 0;
813 sc->sc_flags.change_suspend = 1;
815 /* disable resume interrupt */
816 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
818 /* enable suspend interrupt */
819 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
820 AT91_UDP_INT_RXSUSP);
822 } else if (status & AT91_UDP_INT_RXSUSP) {
823 if (!sc->sc_flags.status_suspend) {
824 sc->sc_flags.status_suspend = 1;
825 sc->sc_flags.change_suspend = 1;
827 /* disable suspend interrupt */
828 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
829 AT91_UDP_INT_RXSUSP);
831 /* enable resume interrupt */
832 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
836 /* complete root HUB interrupt endpoint */
837 at91dci_root_intr(sc);
839 /* check for any endpoint interrupts */
841 if (status & AT91_UDP_INT_EPS) {
843 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status);
845 at91dci_interrupt_poll(sc);
847 USB_BUS_UNLOCK(&sc->sc_bus);
851 at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp)
853 struct at91dci_td *td;
855 /* get current Transfer Descriptor */
859 /* prepare for next TD */
860 temp->td_next = td->obj_next;
862 /* fill out the Transfer Descriptor */
863 td->func = temp->func;
865 td->offset = temp->offset;
866 td->remainder = temp->len;
869 td->did_stall = temp->did_stall;
870 td->short_pkt = temp->short_pkt;
871 td->alt_next = temp->setup_alt_next;
875 at91dci_setup_standard_chain(struct usb_xfer *xfer)
877 struct at91dci_std_temp temp;
878 struct at91dci_softc *sc;
879 struct at91dci_td *td;
884 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
885 xfer->address, UE_GET_ADDR(xfer->endpointno),
886 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
888 temp.max_frame_size = xfer->max_frame_size;
890 td = xfer->td_start[0];
891 xfer->td_transfer_first = td;
892 xfer->td_transfer_cache = td;
898 temp.td_next = xfer->td_start[0];
900 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
901 temp.did_stall = !xfer->flags_int.control_stall;
903 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
904 ep_no = (xfer->endpointno & UE_ADDR);
906 /* check if we should prepend a setup message */
908 if (xfer->flags_int.control_xfr) {
909 if (xfer->flags_int.control_hdr) {
911 temp.func = &at91dci_setup_rx;
912 temp.len = xfer->frlengths[0];
913 temp.pc = xfer->frbuffers + 0;
914 temp.short_pkt = temp.len ? 1 : 0;
915 /* check for last frame */
916 if (xfer->nframes == 1) {
917 /* no STATUS stage yet, SETUP is last */
918 if (xfer->flags_int.control_act)
919 temp.setup_alt_next = 0;
922 at91dci_setup_standard_chain_sub(&temp);
929 if (x != xfer->nframes) {
930 if (xfer->endpointno & UE_DIR_IN) {
931 temp.func = &at91dci_data_tx;
934 temp.func = &at91dci_data_rx;
938 /* setup "pc" pointer */
939 temp.pc = xfer->frbuffers + x;
943 while (x != xfer->nframes) {
945 /* DATA0 / DATA1 message */
947 temp.len = xfer->frlengths[x];
951 if (x == xfer->nframes) {
952 if (xfer->flags_int.control_xfr) {
953 if (xfer->flags_int.control_act) {
954 temp.setup_alt_next = 0;
957 temp.setup_alt_next = 0;
962 /* make sure that we send an USB packet */
968 /* regular data transfer */
970 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
973 at91dci_setup_standard_chain_sub(&temp);
975 if (xfer->flags_int.isochronous_xfr) {
976 temp.offset += temp.len;
978 /* get next Page Cache pointer */
979 temp.pc = xfer->frbuffers + x;
983 /* check for control transfer */
984 if (xfer->flags_int.control_xfr) {
986 /* always setup a valid "pc" pointer for status and sync */
987 temp.pc = xfer->frbuffers + 0;
990 temp.setup_alt_next = 0;
992 /* check if we need to sync */
994 /* we need a SYNC point after TX */
995 temp.func = &at91dci_data_tx_sync;
996 at91dci_setup_standard_chain_sub(&temp);
999 /* check if we should append a status stage */
1000 if (!xfer->flags_int.control_act) {
1003 * Send a DATA1 message and invert the current
1004 * endpoint direction.
1006 if (xfer->endpointno & UE_DIR_IN) {
1007 temp.func = &at91dci_data_rx;
1010 temp.func = &at91dci_data_tx;
1014 at91dci_setup_standard_chain_sub(&temp);
1016 /* we need a SYNC point after TX */
1017 temp.func = &at91dci_data_tx_sync;
1018 at91dci_setup_standard_chain_sub(&temp);
1023 /* must have at least one frame! */
1025 xfer->td_transfer_last = td;
1027 /* setup the correct fifo bank */
1028 if (sc->sc_ep_flags[ep_no].fifo_bank) {
1029 td = xfer->td_transfer_first;
1035 at91dci_timeout(void *arg)
1037 struct usb_xfer *xfer = arg;
1039 DPRINTF("xfer=%p\n", xfer);
1041 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1043 /* transfer is transferred */
1044 at91dci_device_done(xfer, USB_ERR_TIMEOUT);
1048 at91dci_start_standard_chain(struct usb_xfer *xfer)
1053 if (at91dci_xfer_do_fifo(xfer)) {
1055 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1056 uint8_t ep_no = xfer->endpointno & UE_ADDR;
1059 * Only enable the endpoint interrupt when we are actually
1060 * waiting for data, hence we are dealing with level
1061 * triggered interrupts !
1063 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no));
1065 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no);
1067 /* put transfer on interrupt queue */
1068 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1070 /* start timeout, if any */
1071 if (xfer->timeout != 0) {
1072 usbd_transfer_timeout_ms(xfer,
1073 &at91dci_timeout, xfer->timeout);
1079 at91dci_root_intr(struct at91dci_softc *sc)
1083 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1086 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
1088 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1089 sizeof(sc->sc_hub_idata));
1093 at91dci_standard_done_sub(struct usb_xfer *xfer)
1095 struct at91dci_td *td;
1101 td = xfer->td_transfer_cache;
1104 len = td->remainder;
1106 if (xfer->aframes != xfer->nframes) {
1108 * Verify the length and subtract
1109 * the remainder from "frlengths[]":
1111 if (len > xfer->frlengths[xfer->aframes]) {
1114 xfer->frlengths[xfer->aframes] -= len;
1117 /* Check for transfer error */
1119 /* the transfer is finished */
1124 /* Check for short transfer */
1126 if (xfer->flags_int.short_frames_ok) {
1127 /* follow alt next */
1134 /* the transfer is finished */
1142 /* this USB frame is complete */
1148 /* update transfer cache */
1150 xfer->td_transfer_cache = td;
1153 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1157 at91dci_standard_done(struct usb_xfer *xfer)
1159 usb_error_t err = 0;
1161 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1162 xfer, xfer->endpoint);
1166 xfer->td_transfer_cache = xfer->td_transfer_first;
1168 if (xfer->flags_int.control_xfr) {
1170 if (xfer->flags_int.control_hdr) {
1172 err = at91dci_standard_done_sub(xfer);
1176 if (xfer->td_transfer_cache == NULL) {
1180 while (xfer->aframes != xfer->nframes) {
1182 err = at91dci_standard_done_sub(xfer);
1185 if (xfer->td_transfer_cache == NULL) {
1190 if (xfer->flags_int.control_xfr &&
1191 !xfer->flags_int.control_act) {
1193 err = at91dci_standard_done_sub(xfer);
1196 at91dci_device_done(xfer, err);
1199 /*------------------------------------------------------------------------*
1200 * at91dci_device_done
1202 * NOTE: this function can be called more than one time on the
1203 * same USB transfer!
1204 *------------------------------------------------------------------------*/
1206 at91dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1208 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1211 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1213 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1214 xfer, xfer->endpoint, error);
1216 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1217 ep_no = (xfer->endpointno & UE_ADDR);
1219 /* disable endpoint interrupt */
1220 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no));
1222 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no);
1224 /* dequeue transfer and start next transfer */
1225 usbd_transfer_done(xfer, error);
1229 at91dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1230 struct usb_endpoint *ep, uint8_t *did_stall)
1232 struct at91dci_softc *sc;
1236 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1238 DPRINTFN(5, "endpoint=%p\n", ep);
1241 /* cancel any ongoing transfers */
1242 at91dci_device_done(xfer, USB_ERR_STALLED);
1244 /* set FORCESTALL */
1245 sc = AT9100_DCI_BUS2SC(udev->bus);
1246 csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR);
1247 csr_reg = AT91_UDP_CSR(csr_reg);
1248 csr_val = AT91_UDP_READ_4(sc, csr_reg);
1249 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL);
1250 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1254 at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no,
1255 uint8_t ep_type, uint8_t ep_dir)
1257 const struct usb_hw_ep_profile *pf;
1263 if (ep_type == UE_CONTROL) {
1264 /* clearing stall is not needed */
1267 /* compute CSR register offset */
1268 csr_reg = AT91_UDP_CSR(ep_no);
1270 /* compute default CSR value */
1272 AT91_CSR_ACK(csr_val, 0);
1274 /* disable endpoint */
1275 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1277 /* get endpoint profile */
1278 at91dci_get_hw_ep_profile(NULL, &pf, ep_no);
1281 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no));
1282 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0);
1285 * NOTE: One would assume that a FIFO reset would release the
1286 * FIFO banks aswell, but it doesn't! We have to do this
1290 /* release FIFO banks, if any */
1291 for (to = 0; to != 2; to++) {
1294 csr_val = AT91_UDP_READ_4(sc, csr_reg);
1296 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 |
1297 AT91_UDP_CSR_RX_DATA_BK1)) {
1298 /* clear status bits */
1299 if (pf->support_multi_buffer) {
1300 if (sc->sc_ep_flags[ep_no].fifo_bank) {
1301 sc->sc_ep_flags[ep_no].fifo_bank = 0;
1302 temp = AT91_UDP_CSR_RX_DATA_BK1;
1304 sc->sc_ep_flags[ep_no].fifo_bank = 1;
1305 temp = AT91_UDP_CSR_RX_DATA_BK0;
1308 temp = (AT91_UDP_CSR_RX_DATA_BK0 |
1309 AT91_UDP_CSR_RX_DATA_BK1);
1315 /* clear FORCESTALL */
1316 temp |= AT91_UDP_CSR_STALLSENT;
1318 AT91_CSR_ACK(csr_val, temp);
1319 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1322 /* compute default CSR value */
1324 AT91_CSR_ACK(csr_val, 0);
1326 /* enable endpoint */
1327 csr_val &= ~AT91_UDP_CSR_ET_MASK;
1328 csr_val |= AT91_UDP_CSR_EPEDS;
1330 if (ep_type == UE_CONTROL) {
1331 csr_val |= AT91_UDP_CSR_ET_CTRL;
1333 if (ep_type == UE_BULK) {
1334 csr_val |= AT91_UDP_CSR_ET_BULK;
1335 } else if (ep_type == UE_INTERRUPT) {
1336 csr_val |= AT91_UDP_CSR_ET_INT;
1338 csr_val |= AT91_UDP_CSR_ET_ISO;
1340 if (ep_dir & UE_DIR_IN) {
1341 csr_val |= AT91_UDP_CSR_ET_DIR_IN;
1345 /* enable endpoint */
1346 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val);
1350 at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1352 struct at91dci_softc *sc;
1353 struct usb_endpoint_descriptor *ed;
1355 DPRINTFN(5, "endpoint=%p\n", ep);
1357 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1360 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1365 sc = AT9100_DCI_BUS2SC(udev->bus);
1367 /* get endpoint descriptor */
1370 /* reset endpoint */
1371 at91dci_clear_stall_sub(sc,
1372 (ed->bEndpointAddress & UE_ADDR),
1373 (ed->bmAttributes & UE_XFERTYPE),
1374 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1378 at91dci_init(struct at91dci_softc *sc)
1385 /* set up the bus structure */
1386 sc->sc_bus.usbrev = USB_REV_1_1;
1387 sc->sc_bus.methods = &at91dci_bus_methods;
1389 USB_BUS_LOCK(&sc->sc_bus);
1391 /* turn on clocks */
1393 if (sc->sc_clocks_on) {
1394 (sc->sc_clocks_on) (sc->sc_clocks_arg);
1396 /* wait a little for things to stabilise */
1397 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
1399 /* disable and clear all interrupts */
1401 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1402 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1404 /* compute default CSR value */
1407 AT91_CSR_ACK(csr_val, 0);
1409 /* disable all endpoints */
1411 for (n = 0; n != AT91_UDP_EP_MAX; n++) {
1413 /* disable endpoint */
1414 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val);
1417 /* enable the control endpoint */
1419 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL |
1420 AT91_UDP_CSR_EPEDS);
1422 /* write to FIFO control register */
1424 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val);
1426 /* enable the interrupts we want */
1428 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS);
1430 /* turn off clocks */
1432 at91dci_clocks_off(sc);
1434 USB_BUS_UNLOCK(&sc->sc_bus);
1436 /* catch any lost interrupts */
1438 at91dci_do_poll(&sc->sc_bus);
1440 return (0); /* success */
1444 at91dci_uninit(struct at91dci_softc *sc)
1446 USB_BUS_LOCK(&sc->sc_bus);
1448 /* disable and clear all interrupts */
1449 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1450 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1452 sc->sc_flags.port_powered = 0;
1453 sc->sc_flags.status_vbus = 0;
1454 sc->sc_flags.status_bus_reset = 0;
1455 sc->sc_flags.status_suspend = 0;
1456 sc->sc_flags.change_suspend = 0;
1457 sc->sc_flags.change_connect = 1;
1459 at91dci_pull_down(sc);
1460 at91dci_clocks_off(sc);
1461 USB_BUS_UNLOCK(&sc->sc_bus);
1465 at91dci_suspend(struct at91dci_softc *sc)
1471 at91dci_resume(struct at91dci_softc *sc)
1477 at91dci_do_poll(struct usb_bus *bus)
1479 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
1481 USB_BUS_LOCK(&sc->sc_bus);
1482 at91dci_interrupt_poll(sc);
1483 USB_BUS_UNLOCK(&sc->sc_bus);
1486 /*------------------------------------------------------------------------*
1487 * at91dci bulk support
1488 *------------------------------------------------------------------------*/
1490 at91dci_device_bulk_open(struct usb_xfer *xfer)
1496 at91dci_device_bulk_close(struct usb_xfer *xfer)
1498 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1502 at91dci_device_bulk_enter(struct usb_xfer *xfer)
1508 at91dci_device_bulk_start(struct usb_xfer *xfer)
1511 at91dci_setup_standard_chain(xfer);
1512 at91dci_start_standard_chain(xfer);
1515 struct usb_pipe_methods at91dci_device_bulk_methods =
1517 .open = at91dci_device_bulk_open,
1518 .close = at91dci_device_bulk_close,
1519 .enter = at91dci_device_bulk_enter,
1520 .start = at91dci_device_bulk_start,
1523 /*------------------------------------------------------------------------*
1524 * at91dci control support
1525 *------------------------------------------------------------------------*/
1527 at91dci_device_ctrl_open(struct usb_xfer *xfer)
1533 at91dci_device_ctrl_close(struct usb_xfer *xfer)
1535 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1539 at91dci_device_ctrl_enter(struct usb_xfer *xfer)
1545 at91dci_device_ctrl_start(struct usb_xfer *xfer)
1548 at91dci_setup_standard_chain(xfer);
1549 at91dci_start_standard_chain(xfer);
1552 struct usb_pipe_methods at91dci_device_ctrl_methods =
1554 .open = at91dci_device_ctrl_open,
1555 .close = at91dci_device_ctrl_close,
1556 .enter = at91dci_device_ctrl_enter,
1557 .start = at91dci_device_ctrl_start,
1560 /*------------------------------------------------------------------------*
1561 * at91dci interrupt support
1562 *------------------------------------------------------------------------*/
1564 at91dci_device_intr_open(struct usb_xfer *xfer)
1570 at91dci_device_intr_close(struct usb_xfer *xfer)
1572 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1576 at91dci_device_intr_enter(struct usb_xfer *xfer)
1582 at91dci_device_intr_start(struct usb_xfer *xfer)
1585 at91dci_setup_standard_chain(xfer);
1586 at91dci_start_standard_chain(xfer);
1589 struct usb_pipe_methods at91dci_device_intr_methods =
1591 .open = at91dci_device_intr_open,
1592 .close = at91dci_device_intr_close,
1593 .enter = at91dci_device_intr_enter,
1594 .start = at91dci_device_intr_start,
1597 /*------------------------------------------------------------------------*
1598 * at91dci full speed isochronous support
1599 *------------------------------------------------------------------------*/
1601 at91dci_device_isoc_fs_open(struct usb_xfer *xfer)
1607 at91dci_device_isoc_fs_close(struct usb_xfer *xfer)
1609 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1613 at91dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1615 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1619 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1620 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1622 /* get the current frame index */
1624 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM);
1627 * check if the frame index is within the window where the frames
1630 temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK;
1632 if ((xfer->endpoint->is_synced == 0) ||
1633 (temp < xfer->nframes)) {
1635 * If there is data underflow or the endpoint queue is
1636 * empty we schedule the transfer a few frames ahead
1637 * of the current frame position. Else two isochronous
1638 * transfers might overlap.
1640 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK;
1641 xfer->endpoint->is_synced = 1;
1642 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1645 * compute how many milliseconds the insertion is ahead of the
1646 * current frame position:
1648 temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK;
1651 * pre-compute when the isochronous transfer will be finished:
1653 xfer->isoc_time_complete =
1654 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1657 /* compute frame number for next insertion */
1658 xfer->endpoint->isoc_next += xfer->nframes;
1661 at91dci_setup_standard_chain(xfer);
1665 at91dci_device_isoc_fs_start(struct usb_xfer *xfer)
1667 /* start TD chain */
1668 at91dci_start_standard_chain(xfer);
1671 struct usb_pipe_methods at91dci_device_isoc_fs_methods =
1673 .open = at91dci_device_isoc_fs_open,
1674 .close = at91dci_device_isoc_fs_close,
1675 .enter = at91dci_device_isoc_fs_enter,
1676 .start = at91dci_device_isoc_fs_start,
1679 /*------------------------------------------------------------------------*
1680 * at91dci root control support
1681 *------------------------------------------------------------------------*
1682 * Simulate a hardware HUB by handling all the necessary requests.
1683 *------------------------------------------------------------------------*/
1685 static const struct usb_device_descriptor at91dci_devd = {
1686 .bLength = sizeof(struct usb_device_descriptor),
1687 .bDescriptorType = UDESC_DEVICE,
1688 .bcdUSB = {0x00, 0x02},
1689 .bDeviceClass = UDCLASS_HUB,
1690 .bDeviceSubClass = UDSUBCLASS_HUB,
1691 .bDeviceProtocol = UDPROTO_FSHUB,
1692 .bMaxPacketSize = 64,
1693 .bcdDevice = {0x00, 0x01},
1696 .bNumConfigurations = 1,
1699 static const struct at91dci_config_desc at91dci_confd = {
1701 .bLength = sizeof(struct usb_config_descriptor),
1702 .bDescriptorType = UDESC_CONFIG,
1703 .wTotalLength[0] = sizeof(at91dci_confd),
1705 .bConfigurationValue = 1,
1706 .iConfiguration = 0,
1707 .bmAttributes = UC_SELF_POWERED,
1711 .bLength = sizeof(struct usb_interface_descriptor),
1712 .bDescriptorType = UDESC_INTERFACE,
1714 .bInterfaceClass = UICLASS_HUB,
1715 .bInterfaceSubClass = UISUBCLASS_HUB,
1716 .bInterfaceProtocol = 0,
1719 .bLength = sizeof(struct usb_endpoint_descriptor),
1720 .bDescriptorType = UDESC_ENDPOINT,
1721 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT),
1722 .bmAttributes = UE_INTERRUPT,
1723 .wMaxPacketSize[0] = 8,
1728 static const struct usb_hub_descriptor_min at91dci_hubd = {
1729 .bDescLength = sizeof(at91dci_hubd),
1730 .bDescriptorType = UDESC_HUB,
1732 .wHubCharacteristics[0] =
1733 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1734 .wHubCharacteristics[1] =
1735 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1736 .bPwrOn2PwrGood = 50,
1737 .bHubContrCurrent = 0,
1738 .DeviceRemovable = {0}, /* port is removable */
1741 #define STRING_LANG \
1742 0x09, 0x04, /* American English */
1744 #define STRING_VENDOR \
1745 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0
1747 #define STRING_PRODUCT \
1748 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1749 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1752 USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab);
1753 USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor);
1754 USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product);
1757 at91dci_roothub_exec(struct usb_device *udev,
1758 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1760 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
1767 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1770 ptr = (const void *)&sc->sc_hub_temp;
1774 value = UGETW(req->wValue);
1775 index = UGETW(req->wIndex);
1777 /* demultiplex the control request */
1779 switch (req->bmRequestType) {
1780 case UT_READ_DEVICE:
1781 switch (req->bRequest) {
1782 case UR_GET_DESCRIPTOR:
1783 goto tr_handle_get_descriptor;
1785 goto tr_handle_get_config;
1787 goto tr_handle_get_status;
1793 case UT_WRITE_DEVICE:
1794 switch (req->bRequest) {
1795 case UR_SET_ADDRESS:
1796 goto tr_handle_set_address;
1798 goto tr_handle_set_config;
1799 case UR_CLEAR_FEATURE:
1800 goto tr_valid; /* nop */
1801 case UR_SET_DESCRIPTOR:
1802 goto tr_valid; /* nop */
1803 case UR_SET_FEATURE:
1809 case UT_WRITE_ENDPOINT:
1810 switch (req->bRequest) {
1811 case UR_CLEAR_FEATURE:
1812 switch (UGETW(req->wValue)) {
1813 case UF_ENDPOINT_HALT:
1814 goto tr_handle_clear_halt;
1815 case UF_DEVICE_REMOTE_WAKEUP:
1816 goto tr_handle_clear_wakeup;
1821 case UR_SET_FEATURE:
1822 switch (UGETW(req->wValue)) {
1823 case UF_ENDPOINT_HALT:
1824 goto tr_handle_set_halt;
1825 case UF_DEVICE_REMOTE_WAKEUP:
1826 goto tr_handle_set_wakeup;
1831 case UR_SYNCH_FRAME:
1832 goto tr_valid; /* nop */
1838 case UT_READ_ENDPOINT:
1839 switch (req->bRequest) {
1841 goto tr_handle_get_ep_status;
1847 case UT_WRITE_INTERFACE:
1848 switch (req->bRequest) {
1849 case UR_SET_INTERFACE:
1850 goto tr_handle_set_interface;
1851 case UR_CLEAR_FEATURE:
1852 goto tr_valid; /* nop */
1853 case UR_SET_FEATURE:
1859 case UT_READ_INTERFACE:
1860 switch (req->bRequest) {
1861 case UR_GET_INTERFACE:
1862 goto tr_handle_get_interface;
1864 goto tr_handle_get_iface_status;
1870 case UT_WRITE_CLASS_INTERFACE:
1871 case UT_WRITE_VENDOR_INTERFACE:
1875 case UT_READ_CLASS_INTERFACE:
1876 case UT_READ_VENDOR_INTERFACE:
1880 case UT_WRITE_CLASS_DEVICE:
1881 switch (req->bRequest) {
1882 case UR_CLEAR_FEATURE:
1884 case UR_SET_DESCRIPTOR:
1885 case UR_SET_FEATURE:
1892 case UT_WRITE_CLASS_OTHER:
1893 switch (req->bRequest) {
1894 case UR_CLEAR_FEATURE:
1895 goto tr_handle_clear_port_feature;
1896 case UR_SET_FEATURE:
1897 goto tr_handle_set_port_feature;
1898 case UR_CLEAR_TT_BUFFER:
1908 case UT_READ_CLASS_OTHER:
1909 switch (req->bRequest) {
1910 case UR_GET_TT_STATE:
1911 goto tr_handle_get_tt_state;
1913 goto tr_handle_get_port_status;
1919 case UT_READ_CLASS_DEVICE:
1920 switch (req->bRequest) {
1921 case UR_GET_DESCRIPTOR:
1922 goto tr_handle_get_class_descriptor;
1924 goto tr_handle_get_class_status;
1935 tr_handle_get_descriptor:
1936 switch (value >> 8) {
1941 len = sizeof(at91dci_devd);
1942 ptr = (const void *)&at91dci_devd;
1948 len = sizeof(at91dci_confd);
1949 ptr = (const void *)&at91dci_confd;
1952 switch (value & 0xff) {
1953 case 0: /* Language table */
1954 len = sizeof(at91dci_langtab);
1955 ptr = (const void *)&at91dci_langtab;
1958 case 1: /* Vendor */
1959 len = sizeof(at91dci_vendor);
1960 ptr = (const void *)&at91dci_vendor;
1963 case 2: /* Product */
1964 len = sizeof(at91dci_product);
1965 ptr = (const void *)&at91dci_product;
1976 tr_handle_get_config:
1978 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1981 tr_handle_get_status:
1983 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1986 tr_handle_set_address:
1987 if (value & 0xFF00) {
1990 sc->sc_rt_addr = value;
1993 tr_handle_set_config:
1997 sc->sc_conf = value;
2000 tr_handle_get_interface:
2002 sc->sc_hub_temp.wValue[0] = 0;
2005 tr_handle_get_tt_state:
2006 tr_handle_get_class_status:
2007 tr_handle_get_iface_status:
2008 tr_handle_get_ep_status:
2010 USETW(sc->sc_hub_temp.wValue, 0);
2014 tr_handle_set_interface:
2015 tr_handle_set_wakeup:
2016 tr_handle_clear_wakeup:
2017 tr_handle_clear_halt:
2020 tr_handle_clear_port_feature:
2024 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2027 case UHF_PORT_SUSPEND:
2028 at91dci_wakeup_peer(sc);
2031 case UHF_PORT_ENABLE:
2032 sc->sc_flags.port_enabled = 0;
2036 case UHF_PORT_INDICATOR:
2037 case UHF_C_PORT_ENABLE:
2038 case UHF_C_PORT_OVER_CURRENT:
2039 case UHF_C_PORT_RESET:
2042 case UHF_PORT_POWER:
2043 sc->sc_flags.port_powered = 0;
2044 at91dci_pull_down(sc);
2045 at91dci_clocks_off(sc);
2047 case UHF_C_PORT_CONNECTION:
2048 sc->sc_flags.change_connect = 0;
2050 case UHF_C_PORT_SUSPEND:
2051 sc->sc_flags.change_suspend = 0;
2054 err = USB_ERR_IOERROR;
2059 tr_handle_set_port_feature:
2063 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
2066 case UHF_PORT_ENABLE:
2067 sc->sc_flags.port_enabled = 1;
2069 case UHF_PORT_SUSPEND:
2070 case UHF_PORT_RESET:
2072 case UHF_PORT_INDICATOR:
2075 case UHF_PORT_POWER:
2076 sc->sc_flags.port_powered = 1;
2079 err = USB_ERR_IOERROR;
2084 tr_handle_get_port_status:
2086 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
2091 if (sc->sc_flags.status_vbus) {
2092 at91dci_clocks_on(sc);
2093 at91dci_pull_up(sc);
2095 at91dci_pull_down(sc);
2096 at91dci_clocks_off(sc);
2099 /* Select FULL-speed and Device Side Mode */
2101 value = UPS_PORT_MODE_DEVICE;
2103 if (sc->sc_flags.port_powered) {
2104 value |= UPS_PORT_POWER;
2106 if (sc->sc_flags.port_enabled) {
2107 value |= UPS_PORT_ENABLED;
2109 if (sc->sc_flags.status_vbus &&
2110 sc->sc_flags.status_bus_reset) {
2111 value |= UPS_CURRENT_CONNECT_STATUS;
2113 if (sc->sc_flags.status_suspend) {
2114 value |= UPS_SUSPEND;
2116 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2120 if (sc->sc_flags.change_connect) {
2121 value |= UPS_C_CONNECT_STATUS;
2123 if (sc->sc_flags.status_vbus &&
2124 sc->sc_flags.status_bus_reset) {
2125 /* reset endpoint flags */
2126 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags));
2129 if (sc->sc_flags.change_suspend) {
2130 value |= UPS_C_SUSPEND;
2132 USETW(sc->sc_hub_temp.ps.wPortChange, value);
2133 len = sizeof(sc->sc_hub_temp.ps);
2136 tr_handle_get_class_descriptor:
2140 ptr = (const void *)&at91dci_hubd;
2141 len = sizeof(at91dci_hubd);
2145 err = USB_ERR_STALLED;
2154 at91dci_xfer_setup(struct usb_setup_params *parm)
2156 const struct usb_hw_ep_profile *pf;
2157 struct at91dci_softc *sc;
2158 struct usb_xfer *xfer;
2164 sc = AT9100_DCI_BUS2SC(parm->udev->bus);
2165 xfer = parm->curr_xfer;
2168 * NOTE: This driver does not use any of the parameters that
2169 * are computed from the following values. Just set some
2170 * reasonable dummies:
2172 parm->hc_max_packet_size = 0x500;
2173 parm->hc_max_packet_count = 1;
2174 parm->hc_max_frame_size = 0x500;
2176 usbd_transfer_setup_sub(parm);
2179 * compute maximum number of TDs
2181 if (parm->methods == &at91dci_device_ctrl_methods) {
2183 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2186 } else if (parm->methods == &at91dci_device_bulk_methods) {
2188 ntd = xfer->nframes + 1 /* SYNC */ ;
2190 } else if (parm->methods == &at91dci_device_intr_methods) {
2192 ntd = xfer->nframes + 1 /* SYNC */ ;
2194 } else if (parm->methods == &at91dci_device_isoc_fs_methods) {
2196 ntd = xfer->nframes + 1 /* SYNC */ ;
2204 * check if "usbd_transfer_setup_sub" set an error
2210 * allocate transfer descriptors
2219 ep_no = xfer->endpointno & UE_ADDR;
2220 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2223 /* should not happen */
2224 parm->err = USB_ERR_INVAL;
2233 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2235 for (n = 0; n != ntd; n++) {
2237 struct at91dci_td *td;
2241 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2244 td->io_tag = sc->sc_io_tag;
2245 td->io_hdl = sc->sc_io_hdl;
2246 td->max_packet_size = xfer->max_packet_size;
2247 td->status_reg = AT91_UDP_CSR(ep_no);
2248 td->fifo_reg = AT91_UDP_FDR(ep_no);
2249 if (pf->support_multi_buffer) {
2250 td->support_multi_buffer = 1;
2252 td->obj_next = last_obj;
2256 parm->size[0] += sizeof(*td);
2259 xfer->td_start[0] = last_obj;
2263 at91dci_xfer_unsetup(struct usb_xfer *xfer)
2269 at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2270 struct usb_endpoint *ep)
2272 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
2274 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2276 edesc->bEndpointAddress, udev->flags.usb_mode,
2279 if (udev->device_index != sc->sc_rt_addr) {
2281 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2285 if (udev->speed != USB_SPEED_FULL) {
2289 switch (edesc->bmAttributes & UE_XFERTYPE) {
2291 ep->methods = &at91dci_device_ctrl_methods;
2294 ep->methods = &at91dci_device_intr_methods;
2296 case UE_ISOCHRONOUS:
2297 ep->methods = &at91dci_device_isoc_fs_methods;
2300 ep->methods = &at91dci_device_bulk_methods;
2309 struct usb_bus_methods at91dci_bus_methods =
2311 .endpoint_init = &at91dci_ep_init,
2312 .xfer_setup = &at91dci_xfer_setup,
2313 .xfer_unsetup = &at91dci_xfer_unsetup,
2314 .get_hw_ep_profile = &at91dci_get_hw_ep_profile,
2315 .set_stall = &at91dci_set_stall,
2316 .clear_stall = &at91dci_clear_stall,
2317 .roothub_exec = &at91dci_roothub_exec,
2318 .xfer_poll = &at91dci_do_poll,