2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43 #include <linux/workqueue.h>
45 #include <linux/mlx4/device.h>
46 #include <linux/mlx4/driver.h>
47 #include <linux/mlx4/doorbell.h>
49 #define DRV_NAME "mlx4_core"
50 #define PFX DRV_NAME ": "
51 #define DRV_VERSION "1.0-ofed1.5.2"
52 #define DRV_RELDATE "August 4, 2010"
55 MLX4_HCR_BASE = 0x80680,
56 MLX4_HCR_SIZE = 0x0001c,
57 MLX4_CLR_INT_SIZE = 0x00008
61 MLX4_MGM_ENTRY_SIZE = 0x100,
62 MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
63 MLX4_MTT_ENTRY_PER_SEG = 8
67 MLX4_NUM_PDS = 1 << 15
71 MLX4_CMPT_TYPE_QP = 0,
72 MLX4_CMPT_TYPE_SRQ = 1,
73 MLX4_CMPT_TYPE_CQ = 2,
74 MLX4_CMPT_TYPE_EQ = 3,
80 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
83 #ifdef CONFIG_MLX4_DEBUG
84 extern int mlx4_debug_level;
85 #else /* CONFIG_MLX4_DEBUG */
86 #define mlx4_debug_level (0)
87 #endif /* CONFIG_MLX4_DEBUG */
89 #define mlx4_dbg(mdev, format, arg...) \
91 if (mlx4_debug_level) \
92 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
95 #define mlx4_err(mdev, format, arg...) \
96 dev_err(&mdev->pdev->dev, format, ## arg)
97 #define mlx4_info(mdev, format, arg...) \
98 dev_info(&mdev->pdev->dev, format, ## arg)
99 #define mlx4_warn(mdev, format, arg...) \
100 dev_warn(&mdev->pdev->dev, format, ## arg)
102 extern int mlx4_blck_lb;
112 unsigned long *table;
116 unsigned long **bits;
117 unsigned int *num_free;
124 struct mlx4_icm_table {
132 struct mlx4_icm **icm;
136 struct mlx4_dev *dev;
137 void __iomem *doorbell;
144 struct mlx4_buf_list *page_list;
148 struct mlx4_profile {
161 struct mlx4_icm *fw_icm;
162 struct mlx4_icm *aux_icm;
170 struct pci_pool *pool;
172 struct mutex hcr_mutex;
173 struct semaphore poll_sem;
174 struct semaphore event_sem;
176 spinlock_t context_lock;
178 struct mlx4_cmd_context *context;
184 struct mlx4_uar_table {
185 struct mlx4_bitmap bitmap;
188 struct mlx4_mr_table {
189 struct mlx4_bitmap mpt_bitmap;
190 struct mlx4_buddy mtt_buddy;
193 struct mlx4_icm_table mtt_table;
194 struct mlx4_icm_table dmpt_table;
197 struct mlx4_cq_table {
198 struct mlx4_bitmap bitmap;
200 struct radix_tree_root tree;
201 struct mlx4_icm_table table;
202 struct mlx4_icm_table cmpt_table;
205 struct mlx4_eq_table {
206 struct mlx4_bitmap bitmap;
208 void __iomem *clr_int;
209 void __iomem **uar_map;
212 struct mlx4_icm_table table;
213 struct mlx4_icm_table cmpt_table;
218 struct mlx4_srq_table {
219 struct mlx4_bitmap bitmap;
221 struct mlx4_icm_table table;
222 struct mlx4_icm_table cmpt_table;
225 struct mlx4_qp_table {
226 struct mlx4_bitmap bitmap;
230 struct mlx4_icm_table qp_table;
231 struct mlx4_icm_table auxc_table;
232 struct mlx4_icm_table altc_table;
233 struct mlx4_icm_table rdmarc_table;
234 struct mlx4_icm_table cmpt_table;
237 struct mlx4_mcg_table {
239 struct mlx4_bitmap bitmap;
240 struct mlx4_icm_table table;
243 struct mlx4_catas_err {
245 struct timer_list timer;
246 struct list_head list;
249 #define MLX4_MAX_MAC_NUM 128
250 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
252 struct mlx4_mac_table {
253 __be64 entries[MLX4_MAX_MAC_NUM];
254 int refs[MLX4_MAX_MAC_NUM];
260 #define MLX4_MAX_VLAN_NUM 128
261 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
263 struct mlx4_vlan_table {
264 __be32 entries[MLX4_MAX_VLAN_NUM];
265 int refs[MLX4_MAX_VLAN_NUM];
271 struct mlx4_port_info {
272 struct mlx4_dev *dev;
275 struct device_attribute port_attr;
276 enum mlx4_port_type tmp_type;
277 struct mlx4_mac_table mac_table;
278 struct mlx4_vlan_table vlan_table;
282 struct mlx4_dev *dev;
283 u8 do_sense_port[MLX4_MAX_PORTS + 1];
284 u8 sense_allowed[MLX4_MAX_PORTS + 1];
285 struct delayed_work sense_poll;
286 struct workqueue_struct *sense_wq;
290 extern struct mutex drv_mutex;
295 struct list_head dev_list;
296 struct list_head ctx_list;
299 struct list_head pgdir_list;
300 struct mutex pgdir_mutex;
305 struct mlx4_bitmap pd_bitmap;
306 struct mlx4_bitmap xrcd_bitmap;
307 struct mlx4_uar_table uar_table;
308 struct mlx4_mr_table mr_table;
309 struct mlx4_cq_table cq_table;
310 struct mlx4_eq_table eq_table;
311 struct mlx4_srq_table srq_table;
312 struct mlx4_qp_table qp_table;
313 struct mlx4_mcg_table mcg_table;
314 struct mlx4_bitmap counters_bitmap;
315 struct list_head bf_list;
316 struct mutex bf_mutex;
318 struct mlx4_catas_err catas_err;
320 void __iomem *clr_base;
322 struct mlx4_uar driver_uar;
324 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
325 struct device_attribute trigger_attr;
328 struct mlx4_sense sense;
329 struct mutex port_mutex;
330 int iboe_counter_index[MLX4_MAX_PORTS];
331 struct io_mapping *bf_mapping;
334 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
336 return container_of(dev, struct mlx4_priv, dev);
339 #define MLX4_SENSE_RANGE (HZ * 3)
341 extern struct workqueue_struct *mlx4_wq;
343 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
344 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
345 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
346 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
347 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
348 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
349 u32 reserved_bot, u32 resetrved_top);
350 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
352 int mlx4_reset(struct mlx4_dev *dev);
354 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
355 void mlx4_free_eq_table(struct mlx4_dev *dev);
357 int mlx4_init_pd_table(struct mlx4_dev *dev);
358 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
359 int mlx4_init_uar_table(struct mlx4_dev *dev);
360 int mlx4_init_mr_table(struct mlx4_dev *dev);
361 int mlx4_init_eq_table(struct mlx4_dev *dev);
362 int mlx4_init_cq_table(struct mlx4_dev *dev);
363 int mlx4_init_qp_table(struct mlx4_dev *dev);
364 int mlx4_init_srq_table(struct mlx4_dev *dev);
365 int mlx4_init_mcg_table(struct mlx4_dev *dev);
367 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
368 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
369 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
370 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
371 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
372 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
373 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
374 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
375 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
377 void mlx4_start_catas_poll(struct mlx4_dev *dev);
378 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
379 void mlx4_catas_init(void);
380 int mlx4_restart_one(struct pci_dev *pdev);
381 int mlx4_register_device(struct mlx4_dev *dev);
382 void mlx4_unregister_device(struct mlx4_dev *dev);
383 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
384 void *mlx4_find_get_prot_dev(struct mlx4_dev *dev, enum mlx4_prot proto, int port);
387 struct mlx4_init_hca_param;
389 u64 mlx4_make_profile(struct mlx4_dev *dev,
390 struct mlx4_profile *request,
391 struct mlx4_dev_cap *dev_cap,
392 struct mlx4_init_hca_param *init_hca);
394 int mlx4_cmd_init(struct mlx4_dev *dev);
395 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
396 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
397 int mlx4_cmd_use_events(struct mlx4_dev *dev);
398 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
400 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
401 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
403 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
405 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
407 void mlx4_handle_catas_err(struct mlx4_dev *dev);
409 void mlx4_do_sense_ports(struct mlx4_dev *dev,
410 enum mlx4_port_type *stype,
411 enum mlx4_port_type *defaults);
412 void mlx4_start_sense(struct mlx4_dev *dev);
413 void mlx4_stop_sense(struct mlx4_dev *dev);
414 int mlx4_sense_init(struct mlx4_dev *dev);
415 void mlx4_sense_cleanup(struct mlx4_dev *dev);
416 int mlx4_check_port_params(struct mlx4_dev *dev,
417 enum mlx4_port_type *port_type);
418 int mlx4_change_port_types(struct mlx4_dev *dev,
419 enum mlx4_port_type *port_types);
421 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
422 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
424 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
425 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);