2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
121 #include <sys/queue.h>
122 #include <sys/cpuset.h>
124 #include <sys/lock.h>
125 #include <sys/msgbuf.h>
126 #include <sys/mutex.h>
127 #include <sys/proc.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
130 #include <sys/systm.h>
131 #include <sys/vmmeter.h>
133 #include <dev/ofw/openfirm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
143 #include <vm/vm_pager.h>
146 #include <machine/cpu.h>
147 #include <machine/platform.h>
148 #include <machine/bat.h>
149 #include <machine/frame.h>
150 #include <machine/md_var.h>
151 #include <machine/psl.h>
152 #include <machine/pte.h>
153 #include <machine/smp.h>
154 #include <machine/sr.h>
155 #include <machine/mmuvar.h>
161 #define TODO panic("%s: not implemented", __func__);
163 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
164 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
165 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
175 * Map of physical memory regions.
177 static struct mem_region *regions;
178 static struct mem_region *pregions;
179 static u_int phys_avail_count;
180 static int regions_sz, pregions_sz;
181 static struct ofw_map *translations;
184 * Lock for the pteg and pvo tables.
186 struct mtx moea_table_mutex;
187 struct mtx moea_vsid_mutex;
189 /* tlbie instruction synchronization */
190 static struct mtx tlbie_mtx;
195 static struct pteg *moea_pteg_table;
196 u_int moea_pteg_count;
197 u_int moea_pteg_mask;
202 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
203 struct pvo_head moea_pvo_kunmanaged =
204 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
206 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
207 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
209 #define BPVO_POOL_SIZE 32768
210 static struct pvo_entry *moea_bpvo_pool;
211 static int moea_bpvo_pool_index = 0;
213 #define VSID_NBPW (sizeof(u_int32_t) * 8)
214 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
216 static boolean_t moea_initialized = FALSE;
221 u_int moea_pte_valid = 0;
222 u_int moea_pte_overflow = 0;
223 u_int moea_pte_replacements = 0;
224 u_int moea_pvo_entries = 0;
225 u_int moea_pvo_enter_calls = 0;
226 u_int moea_pvo_remove_calls = 0;
227 u_int moea_pte_spills = 0;
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
231 &moea_pte_overflow, 0, "");
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
233 &moea_pte_replacements, 0, "");
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
237 &moea_pvo_enter_calls, 0, "");
238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
239 &moea_pvo_remove_calls, 0, "");
240 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
241 &moea_pte_spills, 0, "");
244 * Allocate physical memory for use in moea_bootstrap.
246 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
251 static int moea_pte_insert(u_int, struct pte *);
256 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
257 vm_offset_t, vm_offset_t, u_int, int);
258 static void moea_pvo_remove(struct pvo_entry *, int);
259 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
260 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
265 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
266 vm_prot_t, boolean_t);
267 static void moea_syncicache(vm_offset_t, vm_size_t);
268 static boolean_t moea_query_bit(vm_page_t, int);
269 static u_int moea_clear_bit(vm_page_t, int);
270 static void moea_kremove(mmu_t, vm_offset_t);
271 int moea_pte_spill(vm_offset_t);
274 * Kernel MMU interface
276 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
277 void moea_clear_modify(mmu_t, vm_page_t);
278 void moea_clear_reference(mmu_t, vm_page_t);
279 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
280 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
281 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
283 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
284 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
285 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
286 void moea_init(mmu_t);
287 boolean_t moea_is_modified(mmu_t, vm_page_t);
288 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
289 boolean_t moea_is_referenced(mmu_t, vm_page_t);
290 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
291 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
292 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
293 int moea_page_wired_mappings(mmu_t, vm_page_t);
294 void moea_pinit(mmu_t, pmap_t);
295 void moea_pinit0(mmu_t, pmap_t);
296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
298 void moea_qremove(mmu_t, vm_offset_t, int);
299 void moea_release(mmu_t, pmap_t);
300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
301 void moea_remove_all(mmu_t, vm_page_t);
302 void moea_remove_write(mmu_t, vm_page_t);
303 void moea_zero_page(mmu_t, vm_page_t);
304 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
305 void moea_zero_page_idle(mmu_t, vm_page_t);
306 void moea_activate(mmu_t, struct thread *);
307 void moea_deactivate(mmu_t, struct thread *);
308 void moea_cpu_bootstrap(mmu_t, int);
309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
310 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
311 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
313 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
315 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
317 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
320 static mmu_method_t moea_methods[] = {
321 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
322 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
323 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
324 MMUMETHOD(mmu_copy_page, moea_copy_page),
325 MMUMETHOD(mmu_enter, moea_enter),
326 MMUMETHOD(mmu_enter_object, moea_enter_object),
327 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
328 MMUMETHOD(mmu_extract, moea_extract),
329 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
330 MMUMETHOD(mmu_init, moea_init),
331 MMUMETHOD(mmu_is_modified, moea_is_modified),
332 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
333 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
334 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
335 MMUMETHOD(mmu_map, moea_map),
336 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
337 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
338 MMUMETHOD(mmu_pinit, moea_pinit),
339 MMUMETHOD(mmu_pinit0, moea_pinit0),
340 MMUMETHOD(mmu_protect, moea_protect),
341 MMUMETHOD(mmu_qenter, moea_qenter),
342 MMUMETHOD(mmu_qremove, moea_qremove),
343 MMUMETHOD(mmu_release, moea_release),
344 MMUMETHOD(mmu_remove, moea_remove),
345 MMUMETHOD(mmu_remove_all, moea_remove_all),
346 MMUMETHOD(mmu_remove_write, moea_remove_write),
347 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
348 MMUMETHOD(mmu_zero_page, moea_zero_page),
349 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
350 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
351 MMUMETHOD(mmu_activate, moea_activate),
352 MMUMETHOD(mmu_deactivate, moea_deactivate),
353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
355 /* Internal interfaces */
356 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
357 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
358 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
359 MMUMETHOD(mmu_mapdev, moea_mapdev),
360 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
361 MMUMETHOD(mmu_kextract, moea_kextract),
362 MMUMETHOD(mmu_kenter, moea_kenter),
363 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
364 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
369 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
371 static __inline uint32_t
372 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
377 if (ma != VM_MEMATTR_DEFAULT) {
379 case VM_MEMATTR_UNCACHEABLE:
380 return (PTE_I | PTE_G);
381 case VM_MEMATTR_WRITE_COMBINING:
382 case VM_MEMATTR_WRITE_BACK:
383 case VM_MEMATTR_PREFETCHABLE:
385 case VM_MEMATTR_WRITE_THROUGH:
386 return (PTE_W | PTE_M);
391 * Assume the page is cache inhibited and access is guarded unless
392 * it's in our available memory array.
394 pte_lo = PTE_I | PTE_G;
395 for (i = 0; i < pregions_sz; i++) {
396 if ((pa >= pregions[i].mr_start) &&
397 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
407 tlbie(vm_offset_t va)
410 mtx_lock_spin(&tlbie_mtx);
411 __asm __volatile("ptesync");
412 __asm __volatile("tlbie %0" :: "r"(va));
413 __asm __volatile("eieio; tlbsync; ptesync");
414 mtx_unlock_spin(&tlbie_mtx);
422 for (va = 0; va < 0x00040000; va += 0x00001000) {
423 __asm __volatile("tlbie %0" :: "r"(va));
426 __asm __volatile("tlbsync");
431 va_to_sr(u_int *sr, vm_offset_t va)
433 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
436 static __inline u_int
437 va_to_pteg(u_int sr, vm_offset_t addr)
441 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
443 return (hash & moea_pteg_mask);
446 static __inline struct pvo_head *
447 vm_page_to_pvoh(vm_page_t m)
450 return (&m->md.mdpg_pvoh);
454 moea_attr_clear(vm_page_t m, int ptebit)
457 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
458 m->md.mdpg_attrs &= ~ptebit;
462 moea_attr_fetch(vm_page_t m)
465 return (m->md.mdpg_attrs);
469 moea_attr_save(vm_page_t m, int ptebit)
472 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
473 m->md.mdpg_attrs |= ptebit;
477 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
479 if (pt->pte_hi == pvo_pt->pte_hi)
486 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
488 return (pt->pte_hi & ~PTE_VALID) ==
489 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
490 ((va >> ADDR_API_SHFT) & PTE_API) | which);
494 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
497 mtx_assert(&moea_table_mutex, MA_OWNED);
500 * Construct a PTE. Default to IMB initially. Valid bit only gets
501 * set when the real pte is set in memory.
503 * Note: Don't set the valid bit for correct operation of tlb update.
505 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
506 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
511 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
514 mtx_assert(&moea_table_mutex, MA_OWNED);
515 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
519 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
522 mtx_assert(&moea_table_mutex, MA_OWNED);
525 * As shown in Section 7.6.3.2.3
527 pt->pte_lo &= ~ptebit;
532 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
535 mtx_assert(&moea_table_mutex, MA_OWNED);
536 pvo_pt->pte_hi |= PTE_VALID;
539 * Update the PTE as defined in section 7.6.3.1.
540 * Note that the REF/CHG bits are from pvo_pt and thus should havce
541 * been saved so this routine can restore them (if desired).
543 pt->pte_lo = pvo_pt->pte_lo;
545 pt->pte_hi = pvo_pt->pte_hi;
551 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
554 mtx_assert(&moea_table_mutex, MA_OWNED);
555 pvo_pt->pte_hi &= ~PTE_VALID;
558 * Force the reg & chg bits back into the PTEs.
563 * Invalidate the pte.
565 pt->pte_hi &= ~PTE_VALID;
570 * Save the reg & chg bits.
572 moea_pte_synch(pt, pvo_pt);
577 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
583 moea_pte_unset(pt, pvo_pt, va);
584 moea_pte_set(pt, pvo_pt);
588 * Quick sort callout for comparing memory regions.
590 static int om_cmp(const void *a, const void *b);
593 om_cmp(const void *a, const void *b)
595 const struct ofw_map *mapa;
596 const struct ofw_map *mapb;
600 if (mapa->om_pa < mapb->om_pa)
602 else if (mapa->om_pa > mapb->om_pa)
609 moea_cpu_bootstrap(mmu_t mmup, int ap)
616 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
617 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
619 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
620 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
624 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
625 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
628 __asm __volatile("mtibatu 1,%0" :: "r"(0));
629 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
630 __asm __volatile("mtibatu 2,%0" :: "r"(0));
631 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
632 __asm __volatile("mtibatu 3,%0" :: "r"(0));
635 for (i = 0; i < 16; i++)
636 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
639 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
640 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
647 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
650 phandle_t chosen, mmu;
653 vm_size_t size, physsz, hwphyssz;
654 vm_offset_t pa, va, off;
659 * Set up BAT0 to map the lowest 256 MB area
661 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
662 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
665 * Map PCI memory space.
667 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
668 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
670 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
671 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
673 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
674 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
676 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
677 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
682 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
683 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
686 * Use an IBAT and a DBAT to map the bottom segment of memory
687 * where we are. Turn off instruction relocation temporarily
688 * to prevent faults while reprogramming the IBAT.
691 mtmsr(msr & ~PSL_IR);
692 __asm (".balign 32; \n"
693 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
694 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
695 :: "r"(battable[0].batu), "r"(battable[0].batl));
699 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
700 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
703 /* set global direct map flag */
706 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
707 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
709 for (i = 0; i < pregions_sz; i++) {
713 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
714 pregions[i].mr_start,
715 pregions[i].mr_start + pregions[i].mr_size,
716 pregions[i].mr_size);
718 * Install entries into the BAT table to allow all
719 * of physmem to be convered by on-demand BAT entries.
720 * The loop will sometimes set the same battable element
721 * twice, but that's fine since they won't be used for
724 pa = pregions[i].mr_start & 0xf0000000;
725 end = pregions[i].mr_start + pregions[i].mr_size;
727 u_int n = pa >> ADDR_SR_SHFT;
729 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
730 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
731 pa += SEGMENT_LENGTH;
735 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
736 panic("moea_bootstrap: phys_avail too small");
738 phys_avail_count = 0;
741 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
742 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
743 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
744 regions[i].mr_start + regions[i].mr_size,
747 (physsz + regions[i].mr_size) >= hwphyssz) {
748 if (physsz < hwphyssz) {
749 phys_avail[j] = regions[i].mr_start;
750 phys_avail[j + 1] = regions[i].mr_start +
757 phys_avail[j] = regions[i].mr_start;
758 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
760 physsz += regions[i].mr_size;
762 physmem = btoc(physsz);
765 * Allocate PTEG table.
768 moea_pteg_count = PTEGCOUNT;
770 moea_pteg_count = 0x1000;
772 while (moea_pteg_count < physmem)
773 moea_pteg_count <<= 1;
775 moea_pteg_count >>= 1;
776 #endif /* PTEGCOUNT */
778 size = moea_pteg_count * sizeof(struct pteg);
779 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
781 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
782 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
783 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
784 moea_pteg_mask = moea_pteg_count - 1;
787 * Allocate pv/overflow lists.
789 size = sizeof(struct pvo_head) * moea_pteg_count;
790 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
792 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
793 for (i = 0; i < moea_pteg_count; i++)
794 LIST_INIT(&moea_pvo_table[i]);
797 * Initialize the lock that synchronizes access to the pteg and pvo
800 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
802 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
804 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
807 * Initialise the unmanaged pvo pool.
809 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
810 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
811 moea_bpvo_pool_index = 0;
814 * Make sure kernel vsid is allocated as well as VSID 0.
816 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
817 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
818 moea_vsid_bitmap[0] |= 1;
821 * Initialize the kernel pmap (which is statically allocated).
823 PMAP_LOCK_INIT(kernel_pmap);
824 for (i = 0; i < 16; i++)
825 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
826 CPU_FILL(&kernel_pmap->pm_active);
829 * Set up the Open Firmware mappings
831 if ((chosen = OF_finddevice("/chosen")) == -1)
832 panic("moea_bootstrap: can't find /chosen");
833 OF_getprop(chosen, "mmu", &mmui, 4);
834 if ((mmu = OF_instance_to_package(mmui)) == -1)
835 panic("moea_bootstrap: can't get mmu package");
836 if ((sz = OF_getproplen(mmu, "translations")) == -1)
837 panic("moea_bootstrap: can't get ofw translation count");
839 for (i = 0; phys_avail[i] != 0; i += 2) {
840 if (phys_avail[i + 1] >= sz) {
841 translations = (struct ofw_map *)phys_avail[i];
845 if (translations == NULL)
846 panic("moea_bootstrap: no space to copy translations");
847 bzero(translations, sz);
848 if (OF_getprop(mmu, "translations", translations, sz) == -1)
849 panic("moea_bootstrap: can't get ofw translations");
850 CTR0(KTR_PMAP, "moea_bootstrap: translations");
851 sz /= sizeof(*translations);
852 qsort(translations, sz, sizeof (*translations), om_cmp);
853 for (i = 0; i < sz; i++) {
854 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
855 translations[i].om_pa, translations[i].om_va,
856 translations[i].om_len);
859 * If the mapping is 1:1, let the RAM and device on-demand
860 * BAT tables take care of the translation.
862 if (translations[i].om_va == translations[i].om_pa)
865 /* Enter the pages */
866 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE)
867 moea_kenter(mmup, translations[i].om_va + off,
868 translations[i].om_pa + off);
872 * Calculate the last available physical address.
874 for (i = 0; phys_avail[i + 2] != 0; i += 2)
876 Maxmem = powerpc_btop(phys_avail[i + 1]);
878 moea_cpu_bootstrap(mmup,0);
883 * Set the start and end of kva.
885 virtual_avail = VM_MIN_KERNEL_ADDRESS;
886 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
889 * Allocate a kernel stack with a guard page for thread0 and map it
890 * into the kernel page map.
892 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
893 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
894 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
895 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
896 thread0.td_kstack = va;
897 thread0.td_kstack_pages = KSTACK_PAGES;
898 for (i = 0; i < KSTACK_PAGES; i++) {
899 moea_kenter(mmup, va, pa);
905 * Allocate virtual address space for the message buffer.
907 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
908 msgbufp = (struct msgbuf *)virtual_avail;
910 virtual_avail += round_page(msgbufsize);
911 while (va < virtual_avail) {
912 moea_kenter(mmup, va, pa);
918 * Allocate virtual address space for the dynamic percpu area.
920 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
921 dpcpu = (void *)virtual_avail;
923 virtual_avail += DPCPU_SIZE;
924 while (va < virtual_avail) {
925 moea_kenter(mmup, va, pa);
929 dpcpu_init(dpcpu, 0);
933 * Activate a user pmap. The pmap must be activated before it's address
934 * space can be accessed in any way.
937 moea_activate(mmu_t mmu, struct thread *td)
942 * Load all the data we need up front to encourage the compiler to
943 * not issue any loads while we have interrupts disabled below.
945 pm = &td->td_proc->p_vmspace->vm_pmap;
948 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
949 PCPU_SET(curpmap, pmr);
953 moea_deactivate(mmu_t mmu, struct thread *td)
957 pm = &td->td_proc->p_vmspace->vm_pmap;
958 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
959 PCPU_SET(curpmap, NULL);
963 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
965 struct pvo_entry *pvo;
968 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
972 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
973 pm->pm_stats.wired_count++;
974 pvo->pvo_vaddr |= PVO_WIRED;
976 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
977 pm->pm_stats.wired_count--;
978 pvo->pvo_vaddr &= ~PVO_WIRED;
985 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
990 dst = VM_PAGE_TO_PHYS(mdst);
991 src = VM_PAGE_TO_PHYS(msrc);
993 kcopy((void *)src, (void *)dst, PAGE_SIZE);
997 * Zero a page of physical memory by temporarily mapping it into the tlb.
1000 moea_zero_page(mmu_t mmu, vm_page_t m)
1002 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1003 void *va = (void *)pa;
1005 bzero(va, PAGE_SIZE);
1009 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1011 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1012 void *va = (void *)(pa + off);
1018 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1020 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1021 void *va = (void *)pa;
1023 bzero(va, PAGE_SIZE);
1027 * Map the given physical page at the specified virtual address in the
1028 * target pmap with the protection requested. If specified the page
1029 * will be wired down.
1032 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1036 vm_page_lock_queues();
1038 moea_enter_locked(pmap, va, m, prot, wired);
1039 vm_page_unlock_queues();
1044 * Map the given physical page at the specified virtual address in the
1045 * target pmap with the protection requested. If specified the page
1046 * will be wired down.
1048 * The page queues and pmap must be locked.
1051 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1054 struct pvo_head *pvo_head;
1057 u_int pte_lo, pvo_flags, was_exec;
1060 if (!moea_initialized) {
1061 pvo_head = &moea_pvo_kunmanaged;
1062 zone = moea_upvo_zone;
1065 was_exec = PTE_EXEC;
1067 pvo_head = vm_page_to_pvoh(m);
1069 zone = moea_mpvo_zone;
1070 pvo_flags = PVO_MANAGED;
1073 if (pmap_bootstrapped)
1074 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1075 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1076 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1077 VM_OBJECT_LOCKED(m->object),
1078 ("moea_enter_locked: page %p is not busy", m));
1080 /* XXX change the pvo head for fake pages */
1081 if ((m->oflags & VPO_UNMANAGED) != 0) {
1082 pvo_flags &= ~PVO_MANAGED;
1083 pvo_head = &moea_pvo_kunmanaged;
1084 zone = moea_upvo_zone;
1088 * If this is a managed page, and it's the first reference to the page,
1089 * clear the execness of the page. Otherwise fetch the execness.
1091 if ((pg != NULL) && ((m->oflags & VPO_UNMANAGED) == 0)) {
1092 if (LIST_EMPTY(pvo_head)) {
1093 moea_attr_clear(pg, PTE_EXEC);
1095 was_exec = moea_attr_fetch(pg) & PTE_EXEC;
1099 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1101 if (prot & VM_PROT_WRITE) {
1103 if (pmap_bootstrapped &&
1104 (m->oflags & VPO_UNMANAGED) == 0)
1105 vm_page_aflag_set(m, PGA_WRITEABLE);
1109 if (prot & VM_PROT_EXECUTE)
1110 pvo_flags |= PVO_EXECUTABLE;
1113 pvo_flags |= PVO_WIRED;
1115 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1119 * Flush the real page from the instruction cache if this page is
1120 * mapped executable and cacheable and was not previously mapped (or
1121 * was not mapped executable).
1123 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) &&
1124 (pte_lo & PTE_I) == 0 && was_exec == 0) {
1126 * Flush the real memory from the cache.
1128 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1130 moea_attr_save(pg, PTE_EXEC);
1133 /* XXX syncicache always until problems are sorted */
1134 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1138 * Maps a sequence of resident pages belonging to the same object.
1139 * The sequence begins with the given page m_start. This page is
1140 * mapped at the given virtual address start. Each subsequent page is
1141 * mapped at a virtual address that is offset from start by the same
1142 * amount as the page is offset from m_start within the object. The
1143 * last page in the sequence is the page with the largest offset from
1144 * m_start that can be mapped at a virtual address less than the given
1145 * virtual address end. Not every virtual page between start and end
1146 * is mapped; only those for which a resident page exists with the
1147 * corresponding offset from m_start are mapped.
1150 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1151 vm_page_t m_start, vm_prot_t prot)
1154 vm_pindex_t diff, psize;
1156 psize = atop(end - start);
1158 vm_page_lock_queues();
1160 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1161 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1162 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1163 m = TAILQ_NEXT(m, listq);
1165 vm_page_unlock_queues();
1170 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1174 vm_page_lock_queues();
1176 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1178 vm_page_unlock_queues();
1183 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1185 struct pvo_entry *pvo;
1189 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1193 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1199 * Atomically extract and hold the physical page with the given
1200 * pmap and virtual address pair if that mapping permits the given
1204 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1206 struct pvo_entry *pvo;
1214 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1215 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1216 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1217 (prot & VM_PROT_WRITE) == 0)) {
1218 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1220 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1229 moea_init(mmu_t mmu)
1232 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1233 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1234 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1235 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1236 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1237 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1238 moea_initialized = TRUE;
1242 moea_is_referenced(mmu_t mmu, vm_page_t m)
1245 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1246 ("moea_is_referenced: page %p is not managed", m));
1247 return (moea_query_bit(m, PTE_REF));
1251 moea_is_modified(mmu_t mmu, vm_page_t m)
1254 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1255 ("moea_is_modified: page %p is not managed", m));
1258 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1259 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1260 * is clear, no PTEs can have PTE_CHG set.
1262 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1263 if ((m->oflags & VPO_BUSY) == 0 &&
1264 (m->aflags & PGA_WRITEABLE) == 0)
1266 return (moea_query_bit(m, PTE_CHG));
1270 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1272 struct pvo_entry *pvo;
1276 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1277 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1283 moea_clear_reference(mmu_t mmu, vm_page_t m)
1286 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1287 ("moea_clear_reference: page %p is not managed", m));
1288 moea_clear_bit(m, PTE_REF);
1292 moea_clear_modify(mmu_t mmu, vm_page_t m)
1295 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1296 ("moea_clear_modify: page %p is not managed", m));
1297 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1298 KASSERT((m->oflags & VPO_BUSY) == 0,
1299 ("moea_clear_modify: page %p is busy", m));
1302 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1303 * set. If the object containing the page is locked and the page is
1304 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1306 if ((m->aflags & PGA_WRITEABLE) == 0)
1308 moea_clear_bit(m, PTE_CHG);
1312 * Clear the write and modified bits in each of the given page's mappings.
1315 moea_remove_write(mmu_t mmu, vm_page_t m)
1317 struct pvo_entry *pvo;
1322 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1323 ("moea_remove_write: page %p is not managed", m));
1326 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1327 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1328 * is clear, no page table entries need updating.
1330 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1331 if ((m->oflags & VPO_BUSY) == 0 &&
1332 (m->aflags & PGA_WRITEABLE) == 0)
1334 vm_page_lock_queues();
1335 lo = moea_attr_fetch(m);
1337 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1338 pmap = pvo->pvo_pmap;
1340 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1341 pt = moea_pvo_to_pte(pvo, -1);
1342 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1343 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1345 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1346 lo |= pvo->pvo_pte.pte.pte_lo;
1347 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1348 moea_pte_change(pt, &pvo->pvo_pte.pte,
1350 mtx_unlock(&moea_table_mutex);
1355 if ((lo & PTE_CHG) != 0) {
1356 moea_attr_clear(m, PTE_CHG);
1359 vm_page_aflag_clear(m, PGA_WRITEABLE);
1360 vm_page_unlock_queues();
1364 * moea_ts_referenced:
1366 * Return a count of reference bits for a page, clearing those bits.
1367 * It is not necessary for every reference bit to be cleared, but it
1368 * is necessary that 0 only be returned when there are truly no
1369 * reference bits set.
1371 * XXX: The exact number of bits to check and clear is a matter that
1372 * should be tested and standardized at some point in the future for
1373 * optimal aging of shared pages.
1376 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1379 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1380 ("moea_ts_referenced: page %p is not managed", m));
1381 return (moea_clear_bit(m, PTE_REF));
1385 * Modify the WIMG settings of all mappings for a page.
1388 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1390 struct pvo_entry *pvo;
1391 struct pvo_head *pvo_head;
1396 if ((m->oflags & VPO_UNMANAGED) != 0) {
1397 m->md.mdpg_cache_attrs = ma;
1401 vm_page_lock_queues();
1402 pvo_head = vm_page_to_pvoh(m);
1403 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1405 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1406 pmap = pvo->pvo_pmap;
1408 pt = moea_pvo_to_pte(pvo, -1);
1409 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1410 pvo->pvo_pte.pte.pte_lo |= lo;
1412 moea_pte_change(pt, &pvo->pvo_pte.pte,
1414 if (pvo->pvo_pmap == kernel_pmap)
1417 mtx_unlock(&moea_table_mutex);
1420 m->md.mdpg_cache_attrs = ma;
1421 vm_page_unlock_queues();
1425 * Map a wired page into kernel virtual address space.
1428 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1431 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1435 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1441 if (va < VM_MIN_KERNEL_ADDRESS)
1442 panic("moea_kenter: attempt to enter non-kernel address %#x",
1446 pte_lo = moea_calc_wimg(pa, ma);
1448 PMAP_LOCK(kernel_pmap);
1449 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1450 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1452 if (error != 0 && error != ENOENT)
1453 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1457 * Flush the real memory from the instruction cache.
1459 if ((pte_lo & (PTE_I | PTE_G)) == 0) {
1460 moea_syncicache(pa, PAGE_SIZE);
1462 PMAP_UNLOCK(kernel_pmap);
1466 * Extract the physical page address associated with the given kernel virtual
1470 moea_kextract(mmu_t mmu, vm_offset_t va)
1472 struct pvo_entry *pvo;
1476 * Allow direct mappings on 32-bit OEA
1478 if (va < VM_MIN_KERNEL_ADDRESS) {
1482 PMAP_LOCK(kernel_pmap);
1483 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1484 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1485 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1486 PMAP_UNLOCK(kernel_pmap);
1491 * Remove a wired page from kernel virtual address space.
1494 moea_kremove(mmu_t mmu, vm_offset_t va)
1497 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1501 * Map a range of physical addresses into kernel virtual address space.
1503 * The value passed in *virt is a suggested virtual address for the mapping.
1504 * Architectures which can support a direct-mapped physical to virtual region
1505 * can return the appropriate address within that region, leaving '*virt'
1506 * unchanged. We cannot and therefore do not; *virt is updated with the
1507 * first usable address after the mapped region.
1510 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1511 vm_offset_t pa_end, int prot)
1513 vm_offset_t sva, va;
1517 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1518 moea_kenter(mmu, va, pa_start);
1524 * Returns true if the pmap's pv is one of the first
1525 * 16 pvs linked to from this page. This count may
1526 * be changed upwards or downwards in the future; it
1527 * is only necessary that true be returned for a small
1528 * subset of pmaps for proper page aging.
1531 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1534 struct pvo_entry *pvo;
1537 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1538 ("moea_page_exists_quick: page %p is not managed", m));
1541 vm_page_lock_queues();
1542 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1543 if (pvo->pvo_pmap == pmap) {
1550 vm_page_unlock_queues();
1555 * Return the number of managed mappings to the given physical page
1559 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1561 struct pvo_entry *pvo;
1565 if ((m->oflags & VPO_UNMANAGED) != 0)
1567 vm_page_lock_queues();
1568 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1569 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1571 vm_page_unlock_queues();
1575 static u_int moea_vsidcontext;
1578 moea_pinit(mmu_t mmu, pmap_t pmap)
1583 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1584 PMAP_LOCK_INIT(pmap);
1587 __asm __volatile("mftb %0" : "=r"(entropy));
1589 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1591 pmap->pmap_phys = pmap;
1595 mtx_lock(&moea_vsid_mutex);
1597 * Allocate some segment registers for this pmap.
1599 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1603 * Create a new value by mutiplying by a prime and adding in
1604 * entropy from the timebase register. This is to make the
1605 * VSID more random so that the PT hash function collides
1606 * less often. (Note that the prime casues gcc to do shifts
1607 * instead of a multiply.)
1609 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1610 hash = moea_vsidcontext & (NPMAPS - 1);
1611 if (hash == 0) /* 0 is special, avoid it */
1614 mask = 1 << (hash & (VSID_NBPW - 1));
1615 hash = (moea_vsidcontext & 0xfffff);
1616 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1617 /* anything free in this bucket? */
1618 if (moea_vsid_bitmap[n] == 0xffffffff) {
1619 entropy = (moea_vsidcontext >> 20);
1622 i = ffs(~moea_vsid_bitmap[n]) - 1;
1624 hash &= 0xfffff & ~(VSID_NBPW - 1);
1627 moea_vsid_bitmap[n] |= mask;
1628 for (i = 0; i < 16; i++)
1629 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1630 mtx_unlock(&moea_vsid_mutex);
1634 mtx_unlock(&moea_vsid_mutex);
1635 panic("moea_pinit: out of segments");
1639 * Initialize the pmap associated with process 0.
1642 moea_pinit0(mmu_t mmu, pmap_t pm)
1645 moea_pinit(mmu, pm);
1646 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1650 * Set the physical protection on the specified range of this map as requested.
1653 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1656 struct pvo_entry *pvo;
1660 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1661 ("moea_protect: non current pmap"));
1663 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1664 moea_remove(mmu, pm, sva, eva);
1668 vm_page_lock_queues();
1670 for (; sva < eva; sva += PAGE_SIZE) {
1671 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1675 if ((prot & VM_PROT_EXECUTE) == 0)
1676 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1679 * Grab the PTE pointer before we diddle with the cached PTE
1682 pt = moea_pvo_to_pte(pvo, pteidx);
1684 * Change the protection of the page.
1686 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1687 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1690 * If the PVO is in the page table, update that pte as well.
1693 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1694 mtx_unlock(&moea_table_mutex);
1697 vm_page_unlock_queues();
1702 * Map a list of wired pages into kernel virtual address space. This is
1703 * intended for temporary mappings which do not need page modification or
1704 * references recorded. Existing mappings in the region are overwritten.
1707 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1712 while (count-- > 0) {
1713 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1720 * Remove page mappings from kernel virtual address space. Intended for
1721 * temporary mappings entered by moea_qenter.
1724 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1729 while (count-- > 0) {
1730 moea_kremove(mmu, va);
1736 moea_release(mmu_t mmu, pmap_t pmap)
1741 * Free segment register's VSID
1743 if (pmap->pm_sr[0] == 0)
1744 panic("moea_release");
1746 mtx_lock(&moea_vsid_mutex);
1747 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1748 mask = 1 << (idx % VSID_NBPW);
1750 moea_vsid_bitmap[idx] &= ~mask;
1751 mtx_unlock(&moea_vsid_mutex);
1752 PMAP_LOCK_DESTROY(pmap);
1756 * Remove the given range of addresses from the specified map.
1759 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1761 struct pvo_entry *pvo;
1764 vm_page_lock_queues();
1766 for (; sva < eva; sva += PAGE_SIZE) {
1767 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1769 moea_pvo_remove(pvo, pteidx);
1773 vm_page_unlock_queues();
1777 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1778 * will reflect changes in pte's back to the vm_page.
1781 moea_remove_all(mmu_t mmu, vm_page_t m)
1783 struct pvo_head *pvo_head;
1784 struct pvo_entry *pvo, *next_pvo;
1787 vm_page_lock_queues();
1788 pvo_head = vm_page_to_pvoh(m);
1789 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1790 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1792 pmap = pvo->pvo_pmap;
1794 moea_pvo_remove(pvo, -1);
1797 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) {
1798 moea_attr_clear(m, PTE_CHG);
1801 vm_page_aflag_clear(m, PGA_WRITEABLE);
1802 vm_page_unlock_queues();
1806 * Allocate a physical page of memory directly from the phys_avail map.
1807 * Can only be called from moea_bootstrap before avail start and end are
1811 moea_bootstrap_alloc(vm_size_t size, u_int align)
1816 size = round_page(size);
1817 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1819 s = (phys_avail[i] + align - 1) & ~(align - 1);
1824 if (s < phys_avail[i] || e > phys_avail[i + 1])
1827 if (s == phys_avail[i]) {
1828 phys_avail[i] += size;
1829 } else if (e == phys_avail[i + 1]) {
1830 phys_avail[i + 1] -= size;
1832 for (j = phys_avail_count * 2; j > i; j -= 2) {
1833 phys_avail[j] = phys_avail[j - 2];
1834 phys_avail[j + 1] = phys_avail[j - 1];
1837 phys_avail[i + 3] = phys_avail[i + 1];
1838 phys_avail[i + 1] = s;
1839 phys_avail[i + 2] = e;
1845 panic("moea_bootstrap_alloc: could not allocate memory");
1849 moea_syncicache(vm_offset_t pa, vm_size_t len)
1851 __syncicache((void *)pa, len);
1855 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1856 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1858 struct pvo_entry *pvo;
1865 moea_pvo_enter_calls++;
1870 * Compute the PTE Group index.
1873 sr = va_to_sr(pm->pm_sr, va);
1874 ptegidx = va_to_pteg(sr, va);
1877 * Remove any existing mapping for this page. Reuse the pvo entry if
1878 * there is a mapping.
1880 mtx_lock(&moea_table_mutex);
1881 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1882 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1883 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1884 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1885 (pte_lo & PTE_PP)) {
1886 mtx_unlock(&moea_table_mutex);
1889 moea_pvo_remove(pvo, -1);
1895 * If we aren't overwriting a mapping, try to allocate.
1897 if (moea_initialized) {
1898 pvo = uma_zalloc(zone, M_NOWAIT);
1900 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1901 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1902 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1903 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1905 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1906 moea_bpvo_pool_index++;
1911 mtx_unlock(&moea_table_mutex);
1916 pvo->pvo_vaddr = va;
1918 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1919 pvo->pvo_vaddr &= ~ADDR_POFF;
1920 if (flags & VM_PROT_EXECUTE)
1921 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1922 if (flags & PVO_WIRED)
1923 pvo->pvo_vaddr |= PVO_WIRED;
1924 if (pvo_head != &moea_pvo_kunmanaged)
1925 pvo->pvo_vaddr |= PVO_MANAGED;
1927 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1929 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1932 * Remember if the list was empty and therefore will be the first
1935 if (LIST_FIRST(pvo_head) == NULL)
1937 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1939 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1940 pm->pm_stats.wired_count++;
1941 pm->pm_stats.resident_count++;
1944 * We hope this succeeds but it isn't required.
1946 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
1948 PVO_PTEGIDX_SET(pvo, i);
1950 panic("moea_pvo_enter: overflow");
1951 moea_pte_overflow++;
1953 mtx_unlock(&moea_table_mutex);
1955 return (first ? ENOENT : 0);
1959 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1964 * If there is an active pte entry, we need to deactivate it (and
1965 * save the ref & cfg bits).
1967 pt = moea_pvo_to_pte(pvo, pteidx);
1969 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1970 mtx_unlock(&moea_table_mutex);
1971 PVO_PTEGIDX_CLR(pvo);
1973 moea_pte_overflow--;
1977 * Update our statistics.
1979 pvo->pvo_pmap->pm_stats.resident_count--;
1980 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1981 pvo->pvo_pmap->pm_stats.wired_count--;
1984 * Save the REF/CHG bits into their cache if the page is managed.
1986 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
1989 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1991 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
1992 (PTE_REF | PTE_CHG));
1997 * Remove this PVO from the PV list.
1999 LIST_REMOVE(pvo, pvo_vlink);
2002 * Remove this from the overflow list and return it to the pool
2003 * if we aren't going to reuse it.
2005 LIST_REMOVE(pvo, pvo_olink);
2006 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2007 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2008 moea_upvo_zone, pvo);
2010 moea_pvo_remove_calls++;
2014 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2019 * We can find the actual pte entry without searching by grabbing
2020 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2021 * noticing the HID bit.
2023 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2024 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2025 pteidx ^= moea_pteg_mask * 8;
2030 static struct pvo_entry *
2031 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2033 struct pvo_entry *pvo;
2038 sr = va_to_sr(pm->pm_sr, va);
2039 ptegidx = va_to_pteg(sr, va);
2041 mtx_lock(&moea_table_mutex);
2042 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2043 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2045 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2049 mtx_unlock(&moea_table_mutex);
2055 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2060 * If we haven't been supplied the ptegidx, calculate it.
2066 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2067 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2068 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2071 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2072 mtx_lock(&moea_table_mutex);
2074 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2075 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2076 "valid pte index", pvo);
2079 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2080 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2081 "pvo but no valid pte", pvo);
2084 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2085 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2086 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2087 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2090 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2092 panic("moea_pvo_to_pte: pvo %p pte does not match "
2093 "pte %p in moea_pteg_table", pvo, pt);
2096 mtx_assert(&moea_table_mutex, MA_OWNED);
2100 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2101 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2102 "moea_pteg_table but valid in pvo", pvo, pt);
2105 mtx_unlock(&moea_table_mutex);
2110 * XXX: THIS STUFF SHOULD BE IN pte.c?
2113 moea_pte_spill(vm_offset_t addr)
2115 struct pvo_entry *source_pvo, *victim_pvo;
2116 struct pvo_entry *pvo;
2125 ptegidx = va_to_pteg(sr, addr);
2128 * Have to substitute some entry. Use the primary hash for this.
2129 * Use low bits of timebase as random generator.
2131 pteg = &moea_pteg_table[ptegidx];
2132 mtx_lock(&moea_table_mutex);
2133 __asm __volatile("mftb %0" : "=r"(i));
2139 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2141 * We need to find a pvo entry for this address.
2143 if (source_pvo == NULL &&
2144 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2145 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2147 * Now found an entry to be spilled into the pteg.
2148 * The PTE is now valid, so we know it's active.
2150 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2153 PVO_PTEGIDX_SET(pvo, j);
2154 moea_pte_overflow--;
2155 mtx_unlock(&moea_table_mutex);
2161 if (victim_pvo != NULL)
2166 * We also need the pvo entry of the victim we are replacing
2167 * so save the R & C bits of the PTE.
2169 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2170 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2172 if (source_pvo != NULL)
2177 if (source_pvo == NULL) {
2178 mtx_unlock(&moea_table_mutex);
2182 if (victim_pvo == NULL) {
2183 if ((pt->pte_hi & PTE_HID) == 0)
2184 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2188 * If this is a secondary PTE, we need to search it's primary
2189 * pvo bucket for the matching PVO.
2191 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2194 * We also need the pvo entry of the victim we are
2195 * replacing so save the R & C bits of the PTE.
2197 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2203 if (victim_pvo == NULL)
2204 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2209 * We are invalidating the TLB entry for the EA we are replacing even
2210 * though it's valid. If we don't, we lose any ref/chg bit changes
2211 * contained in the TLB entry.
2213 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2215 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2216 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2218 PVO_PTEGIDX_CLR(victim_pvo);
2219 PVO_PTEGIDX_SET(source_pvo, i);
2220 moea_pte_replacements++;
2222 mtx_unlock(&moea_table_mutex);
2227 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2232 mtx_assert(&moea_table_mutex, MA_OWNED);
2235 * First try primary hash.
2237 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2238 if ((pt->pte_hi & PTE_VALID) == 0) {
2239 pvo_pt->pte_hi &= ~PTE_HID;
2240 moea_pte_set(pt, pvo_pt);
2246 * Now try secondary hash.
2248 ptegidx ^= moea_pteg_mask;
2250 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2251 if ((pt->pte_hi & PTE_VALID) == 0) {
2252 pvo_pt->pte_hi |= PTE_HID;
2253 moea_pte_set(pt, pvo_pt);
2258 panic("moea_pte_insert: overflow");
2263 moea_query_bit(vm_page_t m, int ptebit)
2265 struct pvo_entry *pvo;
2268 if (moea_attr_fetch(m) & ptebit)
2271 vm_page_lock_queues();
2272 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2275 * See if we saved the bit off. If so, cache it and return
2278 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2279 moea_attr_save(m, ptebit);
2280 vm_page_unlock_queues();
2286 * No luck, now go through the hard part of looking at the PTEs
2287 * themselves. Sync so that any pending REF/CHG bits are flushed to
2291 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2294 * See if this pvo has a valid PTE. if so, fetch the
2295 * REF/CHG bits from the valid PTE. If the appropriate
2296 * ptebit is set, cache it and return success.
2298 pt = moea_pvo_to_pte(pvo, -1);
2300 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2301 mtx_unlock(&moea_table_mutex);
2302 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2303 moea_attr_save(m, ptebit);
2304 vm_page_unlock_queues();
2310 vm_page_unlock_queues();
2315 moea_clear_bit(vm_page_t m, int ptebit)
2318 struct pvo_entry *pvo;
2321 vm_page_lock_queues();
2324 * Clear the cached value.
2326 moea_attr_clear(m, ptebit);
2329 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2330 * we can reset the right ones). note that since the pvo entries and
2331 * list heads are accessed via BAT0 and are never placed in the page
2332 * table, we don't have to worry about further accesses setting the
2338 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2339 * valid pte clear the ptebit from the valid pte.
2342 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2343 pt = moea_pvo_to_pte(pvo, -1);
2345 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2346 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2348 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2350 mtx_unlock(&moea_table_mutex);
2352 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2355 vm_page_unlock_queues();
2360 * Return true if the physical range is encompassed by the battable[idx]
2363 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2371 * Return immediately if not a valid mapping
2373 if (!(battable[idx].batu & BAT_Vs))
2377 * The BAT entry must be cache-inhibited, guarded, and r/w
2378 * so it can function as an i/o page
2380 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2381 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2385 * The address should be within the BAT range. Assume that the
2386 * start address in the BAT has the correct alignment (thus
2387 * not requiring masking)
2389 start = battable[idx].batl & BAT_PBS;
2390 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2391 end = start | (bat_ble << 15) | 0x7fff;
2393 if ((pa < start) || ((pa + size) > end))
2400 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2405 * This currently does not work for entries that
2406 * overlap 256M BAT segments.
2409 for(i = 0; i < 16; i++)
2410 if (moea_bat_mapped(i, pa, size) == 0)
2417 * Map a set of physical memory pages into the kernel virtual
2418 * address space. Return a pointer to where it is mapped. This
2419 * routine is intended to be used for mapping device memory,
2423 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2426 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2430 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2432 vm_offset_t va, tmpva, ppa, offset;
2435 ppa = trunc_page(pa);
2436 offset = pa & PAGE_MASK;
2437 size = roundup(offset + size, PAGE_SIZE);
2440 * If the physical address lies within a valid BAT table entry,
2441 * return the 1:1 mapping. This currently doesn't work
2442 * for regions that overlap 256M BAT segments.
2444 for (i = 0; i < 16; i++) {
2445 if (moea_bat_mapped(i, pa, size) == 0)
2446 return ((void *) pa);
2449 va = kmem_alloc_nofault(kernel_map, size);
2451 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2453 for (tmpva = va; size > 0;) {
2454 moea_kenter_attr(mmu, tmpva, ppa, ma);
2461 return ((void *)(va + offset));
2465 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2467 vm_offset_t base, offset;
2470 * If this is outside kernel virtual space, then it's a
2471 * battable entry and doesn't require unmapping
2473 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2474 base = trunc_page(va);
2475 offset = va & PAGE_MASK;
2476 size = roundup(offset + size, PAGE_SIZE);
2477 kmem_free(kernel_map, base, size);
2482 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2484 struct pvo_entry *pvo;
2491 lim = round_page(va);
2492 len = MIN(lim - va, sz);
2493 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2495 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2497 moea_syncicache(pa, len);