2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
6 * Adapted and extended for Marvell SoCs by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/interrupt.h>
40 #include <sys/module.h>
41 #include <sys/malloc.h>
42 #include <sys/mutex.h>
44 #include <sys/queue.h>
45 #include <sys/timetc.h>
46 #include <machine/bus.h>
47 #include <machine/fdt.h>
48 #include <machine/intr.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <arm/mv/mvvar.h>
55 #include <arm/mv/mvreg.h>
57 #define GPIO_MAX_INTR_COUNT 8
58 #define GPIO_PINS_PER_REG 32
60 struct mv_gpio_softc {
61 struct resource * res[GPIO_MAX_INTR_COUNT + 1];
62 void *ih_cookie[GPIO_MAX_INTR_COUNT];
64 bus_space_handle_t bsh;
65 uint8_t pin_num; /* number of GPIO pins */
66 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
69 extern struct resource_spec mv_gpio_res[];
71 static struct mv_gpio_softc *mv_gpio_softc = NULL;
72 static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
74 static int mv_gpio_probe(device_t);
75 static int mv_gpio_attach(device_t);
76 static int mv_gpio_intr(void *);
78 static void mv_gpio_intr_handler(int pin);
79 static uint32_t mv_gpio_reg_read(uint32_t reg);
80 static void mv_gpio_reg_write(uint32_t reg, uint32_t val);
81 static void mv_gpio_reg_set(uint32_t reg, uint32_t val);
82 static void mv_gpio_reg_clear(uint32_t reg, uint32_t val);
84 static void mv_gpio_blink(uint32_t pin, uint8_t enable);
85 static void mv_gpio_polarity(uint32_t pin, uint8_t enable);
86 static void mv_gpio_level(uint32_t pin, uint8_t enable);
87 static void mv_gpio_edge(uint32_t pin, uint8_t enable);
88 static void mv_gpio_out_en(uint32_t pin, uint8_t enable);
89 static void mv_gpio_int_ack(uint32_t pin);
90 static void mv_gpio_value_set(uint32_t pin, uint8_t val);
91 static uint32_t mv_gpio_value_get(uint32_t pin);
93 static device_method_t mv_gpio_methods[] = {
94 DEVMETHOD(device_probe, mv_gpio_probe),
95 DEVMETHOD(device_attach, mv_gpio_attach),
99 static driver_t mv_gpio_driver = {
102 sizeof(struct mv_gpio_softc),
105 static devclass_t mv_gpio_devclass;
107 DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0);
109 typedef int (*gpios_phandler_t)(phandle_t, pcell_t *, int);
111 struct gpio_ctrl_entry {
113 gpios_phandler_t handler;
116 int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len);
117 int gpio_get_config_from_dt(void);
119 struct gpio_ctrl_entry gpio_controllers[] = {
120 { "mrvl,gpio", &mv_handle_gpios_prop },
125 mv_gpio_probe(device_t dev)
128 if (!ofw_bus_is_compatible(dev, "mrvl,gpio"))
131 device_set_desc(dev, "Marvell Integrated GPIO Controller");
136 mv_gpio_attach(device_t dev)
139 struct mv_gpio_softc *sc;
140 uint32_t dev_id, rev_id;
142 sc = (struct mv_gpio_softc *)device_get_softc(dev);
148 /* Get chip id and revision */
149 soc_id(&dev_id, &rev_id);
151 if (dev_id == MV_DEV_88F5182 ||
152 dev_id == MV_DEV_88F5281 ||
153 dev_id == MV_DEV_MV78100 ||
154 dev_id == MV_DEV_MV78100_Z0 ) {
158 } else if (dev_id == MV_DEV_88F6281) {
163 device_printf(dev, "unknown chip id=0x%x\n", dev_id);
167 error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
169 device_printf(dev, "could not allocate resources\n");
173 sc->bst = rman_get_bustag(sc->res[0]);
174 sc->bsh = rman_get_bushandle(sc->res[0]);
176 /* Disable and clear all interrupts */
177 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0);
178 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0);
179 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0);
181 if (sc->pin_num > GPIO_PINS_PER_REG) {
182 bus_space_write_4(sc->bst, sc->bsh,
183 GPIO_HI_INT_EDGE_MASK, 0);
184 bus_space_write_4(sc->bst, sc->bsh,
185 GPIO_HI_INT_LEV_MASK, 0);
186 bus_space_write_4(sc->bst, sc->bsh,
187 GPIO_HI_INT_CAUSE, 0);
190 for (i = 0; i < sc->irq_num; i++) {
191 if (bus_setup_intr(dev, sc->res[1 + i],
192 INTR_TYPE_MISC, mv_gpio_intr, NULL,
193 sc, &sc->ih_cookie[i]) != 0) {
194 bus_release_resources(dev, mv_gpio_res, sc->res);
195 device_printf(dev, "could not set up intr %d\n", i);
200 return (platform_gpio_init());
204 mv_gpio_intr(void *arg)
206 uint32_t int_cause, gpio_val;
207 uint32_t int_cause_hi, gpio_val_hi = 0;
210 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
211 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
212 gpio_val &= int_cause;
213 if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
214 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
215 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
216 gpio_val_hi &= int_cause_hi;
220 while (gpio_val != 0) {
222 mv_gpio_intr_handler(i);
227 if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
229 while (gpio_val_hi != 0) {
231 mv_gpio_intr_handler(i + GPIO_PINS_PER_REG);
237 return (FILTER_HANDLED);
241 * GPIO interrupt handling
244 static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS];
247 mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
248 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
250 struct intr_event *event;
253 if (pin < 0 || pin >= mv_gpio_softc->pin_num)
255 event = gpio_events[pin];
257 error = intr_event_create(&event, (void *)pin, 0, pin,
258 (void (*)(void *))mv_gpio_intr_mask,
259 (void (*)(void *))mv_gpio_intr_unmask,
260 (void (*)(void *))mv_gpio_int_ack,
265 gpio_events[pin] = event;
268 intr_event_add_handler(event, name, filt, hand, arg,
269 intr_priority(flags), flags, cookiep);
274 mv_gpio_intr_mask(int pin)
277 if (pin >= mv_gpio_softc->pin_num)
280 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
281 mv_gpio_edge(pin, 0);
283 mv_gpio_level(pin, 0);
287 mv_gpio_intr_unmask(int pin)
290 if (pin >= mv_gpio_softc->pin_num)
293 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
294 mv_gpio_edge(pin, 1);
296 mv_gpio_level(pin, 1);
300 mv_gpio_intr_handler(int pin)
302 struct intr_event *event;
304 event = gpio_events[pin];
305 if (event == NULL || TAILQ_EMPTY(&event->ie_handlers))
308 intr_event_handle(event, NULL);
312 mv_gpio_configure(uint32_t pin, uint32_t flags)
315 if (pin >= mv_gpio_softc->pin_num)
318 if (flags & MV_GPIO_OUT_BLINK)
319 mv_gpio_blink(pin, 1);
320 if (flags & MV_GPIO_IN_POL_LOW)
321 mv_gpio_polarity(pin, 1);
322 if (flags & MV_GPIO_IN_IRQ_EDGE)
323 mv_gpio_edge(pin, 1);
324 if (flags & MV_GPIO_IN_IRQ_LEVEL)
325 mv_gpio_level(pin, 1);
327 gpio_setup[pin] = flags;
333 mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable)
336 mv_gpio_value_set(pin, val);
337 mv_gpio_out_en(pin, enable);
341 mv_gpio_in(uint32_t pin)
344 return (mv_gpio_value_get(pin) ? 1 : 0);
348 mv_gpio_reg_read(uint32_t reg)
351 return (bus_space_read_4(mv_gpio_softc->bst,
352 mv_gpio_softc->bsh, reg));
356 mv_gpio_reg_write(uint32_t reg, uint32_t val)
359 bus_space_write_4(mv_gpio_softc->bst,
360 mv_gpio_softc->bsh, reg, val);
364 mv_gpio_reg_set(uint32_t reg, uint32_t pin)
368 reg_val = mv_gpio_reg_read(reg);
369 reg_val |= GPIO(pin);
370 mv_gpio_reg_write(reg, reg_val);
374 mv_gpio_reg_clear(uint32_t reg, uint32_t pin)
378 reg_val = mv_gpio_reg_read(reg);
379 reg_val &= ~(GPIO(pin));
380 mv_gpio_reg_write(reg, reg_val);
384 mv_gpio_out_en(uint32_t pin, uint8_t enable)
388 if (pin >= mv_gpio_softc->pin_num)
391 if (pin >= GPIO_PINS_PER_REG) {
392 reg = GPIO_HI_DATA_OUT_EN_CTRL;
393 pin -= GPIO_PINS_PER_REG;
395 reg = GPIO_DATA_OUT_EN_CTRL;
398 mv_gpio_reg_clear(reg, pin);
400 mv_gpio_reg_set(reg, pin);
404 mv_gpio_blink(uint32_t pin, uint8_t enable)
408 if (pin >= mv_gpio_softc->pin_num)
411 if (pin >= GPIO_PINS_PER_REG) {
412 reg = GPIO_HI_BLINK_EN;
413 pin -= GPIO_PINS_PER_REG;
418 mv_gpio_reg_set(reg, pin);
420 mv_gpio_reg_clear(reg, pin);
424 mv_gpio_polarity(uint32_t pin, uint8_t enable)
428 if (pin >= mv_gpio_softc->pin_num)
431 if (pin >= GPIO_PINS_PER_REG) {
432 reg = GPIO_HI_DATA_IN_POLAR;
433 pin -= GPIO_PINS_PER_REG;
435 reg = GPIO_DATA_IN_POLAR;
438 mv_gpio_reg_set(reg, pin);
440 mv_gpio_reg_clear(reg, pin);
444 mv_gpio_level(uint32_t pin, uint8_t enable)
448 if (pin >= mv_gpio_softc->pin_num)
451 if (pin >= GPIO_PINS_PER_REG) {
452 reg = GPIO_HI_INT_LEV_MASK;
453 pin -= GPIO_PINS_PER_REG;
455 reg = GPIO_INT_LEV_MASK;
458 mv_gpio_reg_set(reg, pin);
460 mv_gpio_reg_clear(reg, pin);
464 mv_gpio_edge(uint32_t pin, uint8_t enable)
468 if (pin >= mv_gpio_softc->pin_num)
471 if (pin >= GPIO_PINS_PER_REG) {
472 reg = GPIO_HI_INT_EDGE_MASK;
473 pin -= GPIO_PINS_PER_REG;
475 reg = GPIO_INT_EDGE_MASK;
478 mv_gpio_reg_set(reg, pin);
480 mv_gpio_reg_clear(reg, pin);
484 mv_gpio_int_ack(uint32_t pin)
488 if (pin >= mv_gpio_softc->pin_num)
491 if (pin >= GPIO_PINS_PER_REG) {
492 reg = GPIO_HI_INT_CAUSE;
493 pin -= GPIO_PINS_PER_REG;
495 reg = GPIO_INT_CAUSE;
497 mv_gpio_reg_clear(reg, pin);
501 mv_gpio_value_get(uint32_t pin)
503 uint32_t reg, reg_val;
505 if (pin >= mv_gpio_softc->pin_num)
508 if (pin >= GPIO_PINS_PER_REG) {
509 reg = GPIO_HI_DATA_IN;
510 pin -= GPIO_PINS_PER_REG;
514 reg_val = mv_gpio_reg_read(reg);
516 return (reg_val & GPIO(pin));
520 mv_gpio_value_set(uint32_t pin, uint8_t val)
524 if (pin >= mv_gpio_softc->pin_num)
527 if (pin >= GPIO_PINS_PER_REG) {
528 reg = GPIO_HI_DATA_OUT;
529 pin -= GPIO_PINS_PER_REG;
534 mv_gpio_reg_set(reg, pin);
536 mv_gpio_reg_clear(reg, pin);
540 mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len)
542 pcell_t gpio_cells, pincnt;
543 int inc, t, tuples, tuple_size;
545 u_long gpio_ctrl, size;
546 struct mv_gpio_softc sc;
549 if (OF_getproplen(ctrl, "gpio-controller") <= 0)
550 /* Node is not a GPIO controller. */
553 if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0)
556 gpio_cells = fdt32_to_cpu(gpio_cells);
560 tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t);
561 tuples = len / tuple_size;
563 if (fdt_regsize(ctrl, &gpio_ctrl, &size))
566 if (OF_getprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0)
568 sc.pin_num = fdt32_to_cpu(pincnt);
571 * Skip controller reference, since controller's phandle is given
572 * explicitly (in a function argument).
574 inc = sizeof(ihandle_t) / sizeof(pcell_t);
577 for (t = 0; t < tuples; t++) {
578 pin = fdt32_to_cpu(gpios[0]);
579 dir = fdt32_to_cpu(gpios[1]);
580 flags = fdt32_to_cpu(gpios[2]);
582 mv_gpio_configure(pin, flags);
586 mv_gpio_out_en(pin, 0);
589 if (flags & MV_GPIO_OUT_OPEN_DRAIN)
590 mv_gpio_out(pin, 0, 1);
592 if (flags & MV_GPIO_OUT_OPEN_SRC)
593 mv_gpio_out(pin, 1, 1);
595 gpios += gpio_cells + inc;
601 #define MAX_PINS_PER_NODE 5
602 #define GPIOS_PROP_CELLS 4
604 platform_gpio_init(void)
606 phandle_t child, parent, root, ctrl;
607 ihandle_t ctrl_ihandle;
608 pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS];
609 struct gpio_ctrl_entry *e;
612 root = OF_finddevice("/");
616 /* Traverse through entire tree to find nodes with 'gpios' prop */
617 for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
619 /* Find a 'leaf'. Start the search from this node. */
620 while (OF_child(child)) {
622 child = OF_child(child);
624 if ((len = OF_getproplen(child, "gpios")) > 0) {
626 if (len > sizeof(gpios))
629 /* Get 'gpios' property. */
630 OF_getprop(child, "gpios", &gpios, len);
632 e = (struct gpio_ctrl_entry *)&gpio_controllers;
634 /* Find and call a handler. */
635 for (; e->compat; e++) {
637 * First cell of 'gpios' property should
638 * contain a ref. to a node defining GPIO
641 ctrl_ihandle = (ihandle_t)gpios[0];
642 ctrl_ihandle = fdt32_to_cpu(ctrl_ihandle);
643 ctrl = OF_instance_to_package(ctrl_ihandle);
645 if (fdt_is_compatible(ctrl, e->compat))
646 /* Call a handler. */
647 if ((rv = e->handler(ctrl,
648 (pcell_t *)&gpios, len)))
653 if (OF_peer(child) == 0) {
654 /* No more siblings. */
656 parent = OF_parent(child);