2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
3 * Copyright (c) 2010 The FreeBSD Foundation
6 * Developed by Semihalf.
8 * Portions of this software were developed by Semihalf
9 * under sponsorship from the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of MARVELL nor the names of contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * Marvell integrated PCI/PCI-Express controller driver.
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
50 #include <sys/queue.h>
53 #include <sys/endian.h>
58 #include <dev/fdt/fdt_common.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcib_private.h>
65 #include "ofw_bus_if.h"
68 #include <machine/resource.h>
69 #include <machine/bus.h>
71 #include <arm/mv/mvreg.h>
72 #include <arm/mv/mvvar.h>
73 #include <arm/mv/mvwin.h>
75 #define PCI_CFG_ENA (1 << 31)
76 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
77 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
78 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
79 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
81 #define PCI_REG_CFG_ADDR 0x0C78
82 #define PCI_REG_CFG_DATA 0x0C7C
83 #define PCI_REG_P2P_CONF 0x1D14
85 #define PCIE_REG_CFG_ADDR 0x18F8
86 #define PCIE_REG_CFG_DATA 0x18FC
87 #define PCIE_REG_CONTROL 0x1A00
88 #define PCIE_CTRL_LINK1X 0x00000001
89 #define PCIE_REG_STATUS 0x1A04
90 #define PCIE_REG_IRQ_MASK 0x1910
92 #define STATUS_LINK_DOWN 1
93 #define STATUS_BUS_OFFS 8
94 #define STATUS_BUS_MASK (0xFF << STATUS_BUS_OFFS)
95 #define STATUS_DEV_OFFS 16
96 #define STATUS_DEV_MASK (0x1F << STATUS_DEV_OFFS)
98 #define P2P_CONF_BUS_OFFS 16
99 #define P2P_CONF_BUS_MASK (0xFF << P2P_CONF_BUS_OFFS)
100 #define P2P_CONF_DEV_OFFS 24
101 #define P2P_CONF_DEV_MASK (0x1F << P2P_CONF_DEV_OFFS)
103 #define PCI_VENDORID_MRVL 0x11AB
105 struct mv_pcib_softc {
108 struct rman sc_mem_rman;
109 bus_addr_t sc_mem_base;
110 bus_addr_t sc_mem_size;
111 bus_addr_t sc_mem_alloc; /* Next allocation. */
112 int sc_mem_win_target;
115 struct rman sc_io_rman;
116 bus_addr_t sc_io_base;
117 bus_addr_t sc_io_size;
118 bus_addr_t sc_io_alloc; /* Next allocation. */
119 int sc_io_win_target;
122 struct resource *sc_res;
123 bus_space_handle_t sc_bsh;
124 bus_space_tag_t sc_bst;
127 int sc_busnr; /* Host bridge bus number */
128 int sc_devnr; /* Host bridge device number */
131 struct fdt_pci_intr sc_intr_info;
134 /* Local forward prototypes */
135 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
136 static void mv_pcib_hw_cfginit(void);
137 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
139 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
140 u_int, u_int, uint32_t, int);
141 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
142 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
143 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
144 static int mv_pcib_intr_info(phandle_t, struct mv_pcib_softc *);
145 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
148 /* Forward prototypes */
149 static int mv_pcib_probe(device_t);
150 static int mv_pcib_attach(device_t);
152 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
153 u_long, u_long, u_long, u_int);
154 static int mv_pcib_release_resource(device_t, device_t, int, int,
156 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
157 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
159 static int mv_pcib_maxslots(device_t);
160 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
161 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
163 static int mv_pcib_route_interrupt(device_t, device_t, int);
166 * Bus interface definitions.
168 static device_method_t mv_pcib_methods[] = {
169 /* Device interface */
170 DEVMETHOD(device_probe, mv_pcib_probe),
171 DEVMETHOD(device_attach, mv_pcib_attach),
174 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar),
175 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar),
176 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource),
177 DEVMETHOD(bus_release_resource, mv_pcib_release_resource),
178 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
179 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
180 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
181 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
184 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
185 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
186 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
187 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
189 /* OFW bus interface */
190 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
191 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
192 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
193 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
194 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
199 static driver_t mv_pcib_driver = {
202 sizeof(struct mv_pcib_softc),
205 devclass_t pcib_devclass;
207 DRIVER_MODULE(pcib, fdtbus, mv_pcib_driver, pcib_devclass, 0, 0);
209 static struct mtx pcicfg_mtx;
212 mv_pcib_probe(device_t self)
216 node = ofw_bus_get_node(self);
217 if (!fdt_is_type(node, "pci"))
220 if (!(fdt_is_compatible(node, "mrvl,pcie") ||
221 fdt_is_compatible(node, "mrvl,pci")))
224 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
225 return (BUS_PROBE_DEFAULT);
229 mv_pcib_attach(device_t self)
231 struct mv_pcib_softc *sc;
232 phandle_t node, parnode;
236 sc = device_get_softc(self);
239 node = ofw_bus_get_node(self);
240 parnode = OF_parent(node);
241 if (fdt_is_compatible(node, "mrvl,pcie")) {
242 sc->sc_type = MV_TYPE_PCIE;
243 sc->sc_mem_win_target = MV_WIN_PCIE_MEM_TARGET;
244 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR;
245 sc->sc_io_win_target = MV_WIN_PCIE_IO_TARGET;
246 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR;
248 } else if (fdt_is_compatible(node, "mrvl,pci")) {
249 sc->sc_type = MV_TYPE_PCI;
250 sc->sc_mem_win_target = MV_WIN_PCI_MEM_TARGET;
251 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
252 sc->sc_io_win_target = MV_WIN_PCI_IO_TARGET;
253 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
259 * Get PCI interrupt info.
261 if (mv_pcib_intr_info(node, sc) != 0) {
262 device_printf(self, "could not retrieve interrupt info\n");
267 * Retrieve our mem-mapped registers range.
270 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
272 if (sc->sc_res == NULL) {
273 device_printf(self, "could not map memory\n");
276 sc->sc_bst = rman_get_bustag(sc->sc_res);
277 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
280 * Configure decode windows for PCI(E) access.
282 if (mv_pcib_decode_win(node, sc) != 0)
285 mv_pcib_hw_cfginit();
290 val = mv_pcib_hw_cfgread(sc, sc->sc_busnr, sc->sc_devnr, 0,
292 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
294 mv_pcib_hw_cfgwrite(sc, sc->sc_busnr, sc->sc_devnr, 0,
295 PCIR_COMMAND, val, 2);
297 sc->sc_mem_alloc = sc->sc_mem_base;
298 sc->sc_io_alloc = sc->sc_io_base;
300 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
301 err = rman_init(&sc->sc_mem_rman);
305 sc->sc_io_rman.rm_type = RMAN_ARRAY;
306 err = rman_init(&sc->sc_io_rman);
308 rman_fini(&sc->sc_mem_rman);
312 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
313 sc->sc_mem_base + sc->sc_mem_size - 1);
317 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
318 sc->sc_io_base + sc->sc_io_size - 1);
322 err = mv_pcib_init(sc, sc->sc_busnr, mv_pcib_maxslots(sc->sc_dev));
326 device_add_child(self, "pci", -1);
327 return (bus_generic_attach(self));
330 /* XXX SYS_RES_ should be released here */
331 rman_fini(&sc->sc_mem_rman);
332 rman_fini(&sc->sc_io_rman);
337 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
340 bus_addr_t *allocp, limit;
341 uint32_t addr, bar, mask, size;
344 reg = PCIR_BAR(barno);
345 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
349 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
350 width = ((bar & 7) == 4) ? 2 : 1;
352 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
353 size = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
355 /* Get BAR type and size */
358 allocp = &sc->sc_io_alloc;
359 limit = sc->sc_io_base + sc->sc_io_size;
361 if ((size & 0xffff0000) == 0)
365 allocp = &sc->sc_mem_alloc;
366 limit = sc->sc_mem_base + sc->sc_mem_size;
372 /* Sanity check (must be a power of 2) */
376 addr = (*allocp + mask) & ~mask;
377 if ((*allocp = addr + size) > limit)
381 printf("PCI %u:%u:%u: reg %x: size=%08x: addr=%08x\n",
382 bus, slot, func, reg, size, addr);
384 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
386 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
393 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
395 bus_addr_t io_base, mem_base;
396 uint32_t io_limit, mem_limit;
399 io_base = sc->sc_io_base;
400 io_limit = io_base + sc->sc_io_size - 1;
401 mem_base = sc->sc_mem_base;
402 mem_limit = mem_base + sc->sc_mem_size - 1;
404 /* Configure I/O decode registers */
405 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
407 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
409 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
411 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
414 /* Configure memory decode registers */
415 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
417 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
420 /* Disable memory prefetch decode */
421 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
423 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
425 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
427 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
430 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
433 /* Configure buses behind the bridge */
434 mv_pcib_init(sc, secbus, PCI_SLOTMAX);
438 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
440 int slot, func, maxfunc, error;
441 uint8_t hdrtype, command, class, subclass;
443 for (slot = 0; slot <= maxslot; slot++) {
445 for (func = 0; func <= maxfunc; func++) {
446 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
447 func, PCIR_HDRTYPE, 1);
449 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
452 if (func == 0 && (hdrtype & PCIM_MFDEV))
453 maxfunc = PCI_FUNCMAX;
455 command = mv_pcib_read_config(sc->sc_dev, bus, slot,
456 func, PCIR_COMMAND, 1);
457 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
458 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
459 PCIR_COMMAND, command, 1);
461 error = mv_pcib_init_all_bars(sc, bus, slot, func,
467 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
469 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
470 PCIR_COMMAND, command, 1);
472 /* Handle PCI-PCI bridges */
473 class = mv_pcib_read_config(sc->sc_dev, bus, slot,
474 func, PCIR_CLASS, 1);
475 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
476 func, PCIR_SUBCLASS, 1);
478 if (class != PCIC_BRIDGE ||
479 subclass != PCIS_BRIDGE_PCI)
482 mv_pcib_init_bridge(sc, bus, slot, func);
486 /* Enable all ABCD interrupts */
487 pcib_write_irq_mask(sc, (0xF << 24));
493 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
494 int func, int hdrtype)
498 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
501 /* Program the base address registers */
502 while (bar < maxbar) {
503 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
506 device_printf(sc->sc_dev,
507 "PCI IO/Memory space exhausted\n");
515 static struct resource *
516 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
517 u_long start, u_long end, u_long count, u_int flags)
519 struct mv_pcib_softc *sc = device_get_softc(dev);
520 struct rman *rm = NULL;
521 struct resource *res;
525 rm = &sc->sc_io_rman;
528 rm = &sc->sc_mem_rman;
531 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
532 type, rid, start, end, count, flags));
535 res = rman_reserve_resource(rm, start, end, count, flags, child);
539 rman_set_rid(res, *rid);
540 rman_set_bustag(res, fdtbus_bs_tag);
541 rman_set_bushandle(res, start);
543 if (flags & RF_ACTIVE)
544 if (bus_activate_resource(child, type, *rid, res)) {
545 rman_release_resource(res);
553 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
554 struct resource *res)
557 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
558 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
561 return (rman_release_resource(res));
565 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
567 struct mv_pcib_softc *sc = device_get_softc(dev);
571 *result = sc->sc_busnr;
573 case PCIB_IVAR_DOMAIN:
574 *result = device_get_unit(dev);
582 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
584 struct mv_pcib_softc *sc = device_get_softc(dev);
588 sc->sc_busnr = value;
596 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
599 if (!sc->sc_type != MV_TYPE_PCI)
602 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
606 mv_pcib_hw_cfginit(void)
608 static int opened = 0;
613 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
618 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
619 u_int func, u_int reg, int bytes)
621 uint32_t addr, data, ca, cd;
623 ca = (sc->sc_type != MV_TYPE_PCI) ?
624 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
625 cd = (sc->sc_type != MV_TYPE_PCI) ?
626 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
627 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
628 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
630 mtx_lock_spin(&pcicfg_mtx);
631 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
636 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
640 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
644 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
648 mtx_unlock_spin(&pcicfg_mtx);
653 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
654 u_int func, u_int reg, uint32_t data, int bytes)
656 uint32_t addr, ca, cd;
658 ca = (sc->sc_type != MV_TYPE_PCI) ?
659 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
660 cd = (sc->sc_type != MV_TYPE_PCI) ?
661 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
662 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
663 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
665 mtx_lock_spin(&pcicfg_mtx);
666 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
670 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
671 cd + (reg & 3), data);
674 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
675 cd + (reg & 2), htole16(data));
678 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
682 mtx_unlock_spin(&pcicfg_mtx);
686 mv_pcib_maxslots(device_t dev)
688 struct mv_pcib_softc *sc = device_get_softc(dev);
690 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
694 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
695 u_int reg, int bytes)
697 struct mv_pcib_softc *sc = device_get_softc(dev);
700 if (bus == sc->sc_busnr && slot == sc->sc_devnr)
703 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
707 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
708 u_int reg, uint32_t val, int bytes)
710 struct mv_pcib_softc *sc = device_get_softc(dev);
713 if (bus == sc->sc_busnr && slot == sc->sc_devnr)
716 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
720 mv_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
722 struct mv_pcib_softc *sc;
725 sc = device_get_softc(pcib);
727 err = fdt_pci_route_intr(pci_get_bus(dev), pci_get_slot(dev),
728 pci_get_function(dev), pin, &sc->sc_intr_info, &interrupt);
732 device_printf(pcib, "could not route pin %d for device %d.%d\n",
733 pin, pci_get_slot(dev), pci_get_function(dev));
734 return (PCI_INVALID_IRQ);
738 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
740 struct fdt_pci_range io_space, mem_space;
746 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) {
747 device_printf(dev, "could not retrieve 'ranges' data\n");
751 /* Configure CPU decoding windows */
752 error = decode_win_cpu_set(sc->sc_io_win_target,
753 sc->sc_io_win_attr, io_space.base_parent, io_space.len, -1);
755 device_printf(dev, "could not set up CPU decode "
756 "window for PCI IO\n");
759 error = decode_win_cpu_set(sc->sc_mem_win_target,
760 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, -1);
762 device_printf(dev, "could not set up CPU decode "
763 "windows for PCI MEM\n");
767 sc->sc_io_base = io_space.base_parent;
768 sc->sc_io_size = io_space.len;
770 sc->sc_mem_base = mem_space.base_parent;
771 sc->sc_mem_size = mem_space.len;
777 mv_pcib_intr_info(phandle_t node, struct mv_pcib_softc *sc)
781 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
788 control = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
792 * If this PCI-E port (controller) is configured (by the
793 * underlying firmware) with lane width other than 1x, there
794 * are auxiliary resources defined for aggregating more width
795 * on our lane. Skip all such entries as they are not
796 * standalone ports and must not have a device object
799 if ((control & PCIE_CTRL_LINK1X) == 0)
800 while (info->op_base &&
801 info->op_type == MV_TYPE_PCIE_AGGR_LANE)
804 mv_pcib_add_child(driver, parent, sc);