2 * Copyright (C) 2008-2009 Semihalf
5 * Initial version developed by Ilya Bakulin. Full functionality and bringup
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
36 #include <sys/resource.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/endian.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
60 #define EDMA_TIMEOUT 100000 /* 100 ms */
61 #define SATA_INL(sc, reg) ATA_INL((sc)->sc_mem_res, reg)
62 #define SATA_OUTL(sc, reg, val) ATA_OUTL((sc)->sc_mem_res, reg, val)
64 /* HW-related data structures */
65 struct sata_prdentry {
69 uint32_t prd_reserved;
77 uint16_t crqb_reserved1[2];
78 uint8_t crqb_ata_command;
79 uint8_t crqb_ata_feature;
80 uint8_t crqb_ata_lba_low;
81 uint8_t crqb_ata_lba_mid;
82 uint8_t crqb_ata_lba_high;
83 uint8_t crqb_ata_device;
84 uint8_t crqb_ata_lba_low_p;
85 uint8_t crqb_ata_lba_mid_p;
86 uint8_t crqb_ata_lba_high_p;
87 uint8_t crqb_ata_feature_p;
88 uint8_t crqb_ata_count;
89 uint8_t crqb_ata_count_p;
90 uint16_t crqb_reserved2;
95 uint8_t crpb_reserved;
96 uint8_t crpb_edma_status;
97 uint8_t crpb_dev_status;
98 uint32_t crpb_timestamp;
101 /* Identification section. */
104 unsigned int sc_version;
105 unsigned int sc_edma_qlen;
106 uint32_t sc_edma_reqis_mask;
107 uint32_t sc_edma_resos_mask;
108 struct resource *sc_mem_res;
109 bus_space_tag_t sc_mem_res_bustag;
110 bus_space_handle_t sc_mem_res_bushdl;
111 struct resource *sc_irq_res;
112 void *sc_irq_cookiep;
114 void (*function)(void *);
116 } sc_interrupt[SATA_CHAN_NUM];
119 /* Controller functions */
120 static int sata_probe(device_t dev);
121 static int sata_attach(device_t dev);
122 static int sata_detach(device_t dev);
123 static void sata_intr(void*);
124 static struct resource * sata_alloc_resource(device_t dev, device_t child,
125 int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
126 static int sata_release_resource(device_t dev, device_t child, int type,
127 int rid, struct resource *r);
128 static int sata_setup_intr(device_t dev, device_t child,
129 struct resource *irq, int flags, driver_filter_t *filt,
130 driver_intr_t *function, void *argument, void **cookiep);
131 static int sata_teardown_intr(device_t dev, device_t child,
132 struct resource *irq, void *cookie);
134 /* Channel functions */
135 static int sata_channel_probe(device_t dev);
136 static int sata_channel_attach(device_t dev);
137 static int sata_channel_detach(device_t dev);
138 static int sata_channel_begin_transaction(struct ata_request *request);
139 static int sata_channel_end_transaction(struct ata_request *request);
140 static int sata_channel_status(device_t dev);
141 static int sata_channel_setmode(device_t dev, int target, int mode);
142 static int sata_channel_getrev(device_t dev, int target);
143 static void sata_channel_reset(device_t dev);
144 static void sata_channel_dmasetprd(void *xsc, bus_dma_segment_t *segs,
145 int nsegs, int error);
148 static int sata_edma_ctrl(device_t dev, int on);
149 static int sata_edma_is_running(device_t);
151 static device_method_t sata_methods[] = {
153 DEVMETHOD(device_probe, sata_probe),
154 DEVMETHOD(device_attach, sata_attach),
155 DEVMETHOD(device_detach, sata_detach),
156 DEVMETHOD(device_shutdown, bus_generic_shutdown),
157 DEVMETHOD(device_suspend, bus_generic_suspend),
158 DEVMETHOD(device_resume, bus_generic_resume),
160 /* ATA bus methods. */
161 DEVMETHOD(bus_alloc_resource, sata_alloc_resource),
162 DEVMETHOD(bus_release_resource, sata_release_resource),
163 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
164 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
165 DEVMETHOD(bus_setup_intr, sata_setup_intr),
166 DEVMETHOD(bus_teardown_intr, sata_teardown_intr),
170 static driver_t sata_driver = {
173 sizeof(struct sata_softc),
176 devclass_t sata_devclass;
178 DRIVER_MODULE(sata, simplebus, sata_driver, sata_devclass, 0, 0);
179 MODULE_VERSION(sata, 1);
180 MODULE_DEPEND(sata, ata, 1, 1, 1);
183 sata_probe(device_t dev)
185 struct sata_softc *sc;
188 if (!ofw_bus_is_compatible(dev, "mrvl,sata"))
192 sc = device_get_softc(dev);
197 sc->sc_edma_qlen = 128;
201 case MV_DEV_MV78100_Z0:
203 sc->sc_edma_qlen = 32;
206 device_printf(dev, "unsupported SoC (ID: 0x%08X)!\n", d);
210 sc->sc_edma_reqis_mask = (sc->sc_edma_qlen - 1) << SATA_EDMA_REQIS_OFS;
211 sc->sc_edma_resos_mask = (sc->sc_edma_qlen - 1) << SATA_EDMA_RESOS_OFS;
213 device_set_desc(dev, "Marvell Integrated SATA Controller");
218 sata_attach(device_t dev)
220 struct sata_softc *sc;
221 int mem_id, irq_id, error, i;
225 sc = device_get_softc(dev);
230 /* Allocate resources */
231 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
233 if (sc->sc_mem_res == NULL) {
234 device_printf(dev, "could not allocate memory.\n");
238 sc->sc_mem_res_bustag = rman_get_bustag(sc->sc_mem_res);
239 sc->sc_mem_res_bushdl = rman_get_bushandle(sc->sc_mem_res);
240 KASSERT(sc->sc_mem_res_bustag && sc->sc_mem_res_bushdl,
241 ("cannot get bus handle or tag."));
243 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq_id,
245 if (sc->sc_irq_res == NULL) {
246 device_printf(dev, "could not allocate IRQ.\n");
251 error = bus_setup_intr(dev, sc->sc_irq_res,
252 INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
253 NULL, sata_intr, sc, &sc->sc_irq_cookiep);
255 device_printf(dev, "could not setup interrupt.\n");
259 /* Attach channels */
260 for (i = 0; i < SATA_CHAN_NUM; i++) {
261 ata_chan = device_add_child(dev, "ata",
262 devclass_find_free_unit(ata_devclass, 0));
265 device_printf(dev, "cannot add channel %d.\n", i);
271 /* Disable interrupt coalescing */
272 reg = SATA_INL(sc, SATA_CR);
273 for (i = 0; i < SATA_CHAN_NUM; i++)
274 reg |= SATA_CR_COALDIS(i);
276 /* Disable DMA byte swapping */
277 if (sc->sc_version == 2)
278 reg |= SATA_CR_NODMABS | SATA_CR_NOEDMABS |
281 SATA_OUTL(sc, SATA_CR, reg);
283 /* Clear and mask all interrupts */
284 SATA_OUTL(sc, SATA_ICR, 0);
285 SATA_OUTL(sc, SATA_MIMR, 0);
287 return(bus_generic_attach(dev));
295 sata_detach(device_t dev)
297 struct sata_softc *sc;
299 sc = device_get_softc(dev);
301 if (device_is_attached(dev))
302 bus_generic_detach(dev);
304 if (sc->sc_mem_res != NULL) {
305 bus_release_resource(dev, SYS_RES_MEMORY,
306 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
307 sc->sc_mem_res = NULL;
310 if (sc->sc_irq_res != NULL) {
311 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_cookiep);
312 bus_release_resource(dev, SYS_RES_IRQ,
313 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
314 sc->sc_irq_res = NULL;
320 static struct resource *
321 sata_alloc_resource(device_t dev, device_t child, int type, int *rid,
322 u_long start, u_long end, u_long count, u_int flags)
324 struct sata_softc *sc;
326 sc = device_get_softc(dev);
328 KASSERT(type == SYS_RES_IRQ && *rid == ATA_IRQ_RID,
329 ("illegal resource request (type %u, rid %u).",
332 return (sc->sc_irq_res);
336 sata_release_resource(device_t dev, device_t child, int type, int rid,
340 KASSERT(type == SYS_RES_IRQ && rid == ATA_IRQ_RID,
341 ("strange type %u and/or rid %u while releasing resource.", type,
348 sata_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
349 driver_filter_t *filt, driver_intr_t *function, void *argument,
352 struct sata_softc *sc;
353 struct ata_channel *ch;
355 sc = device_get_softc(dev);
356 ch = device_get_softc(child);
359 device_printf(dev, "filter interrupts are not supported.\n");
363 sc->sc_interrupt[ch->unit].function = function;
364 sc->sc_interrupt[ch->unit].argument = argument;
371 sata_teardown_intr(device_t dev, device_t child, struct resource *irq,
374 struct sata_softc *sc;
375 struct ata_channel *ch;
377 sc = device_get_softc(dev);
378 ch = device_get_softc(child);
380 sc->sc_interrupt[ch->unit].function = NULL;
381 sc->sc_interrupt[ch->unit].argument = NULL;
389 struct sata_softc *sc;
395 * Behave like ata_generic_intr() for PCI controllers.
396 * Simply invoke ISRs on all channels.
398 for (unit = 0; unit < SATA_CHAN_NUM; unit++)
399 if (sc->sc_interrupt[unit].function != NULL)
400 sc->sc_interrupt[unit].function(
401 sc->sc_interrupt[unit].argument);
405 sata_channel_probe(device_t dev)
408 device_set_desc(dev, "Marvell Integrated SATA Channel");
409 return (ata_probe(dev));
413 sata_channel_attach(device_t dev)
415 struct sata_softc *sc;
416 struct ata_channel *ch;
420 sc = device_get_softc(device_get_parent(dev));
421 ch = device_get_softc(dev);
427 ch->unit = device_get_unit(dev);
428 ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE | ATA_SATA;
430 /* Set legacy ATA resources. */
431 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
432 ch->r_io[i].res = sc->sc_mem_res;
433 ch->r_io[i].offset = SATA_SHADOWR_BASE(ch->unit) + (i << 2);
436 ch->r_io[ATA_CONTROL].res = sc->sc_mem_res;
437 ch->r_io[ATA_CONTROL].offset = SATA_SHADOWR_CONTROL(ch->unit);
439 ch->r_io[ATA_IDX_ADDR].res = sc->sc_mem_res;
440 ata_default_registers(dev);
442 /* Set SATA resources. */
443 ch->r_io[ATA_SSTATUS].res = sc->sc_mem_res;
444 ch->r_io[ATA_SSTATUS].offset = SATA_SATA_SSTATUS(ch->unit);
445 ch->r_io[ATA_SERROR].res = sc->sc_mem_res;
446 ch->r_io[ATA_SERROR].offset = SATA_SATA_SERROR(ch->unit);
447 ch->r_io[ATA_SCONTROL].res = sc->sc_mem_res;
448 ch->r_io[ATA_SCONTROL].offset = SATA_SATA_SCONTROL(ch->unit);
451 ch->hw.begin_transaction = sata_channel_begin_transaction;
452 ch->hw.end_transaction = sata_channel_end_transaction;
453 ch->hw.status = sata_channel_status;
455 /* Set DMA resources */
457 ch->dma.setprd = sata_channel_dmasetprd;
459 /* Clear work area */
460 KASSERT(sc->sc_edma_qlen * (sizeof(struct sata_crqb) +
461 sizeof(struct sata_crpb)) <= ch->dma.max_iosize,
462 ("insufficient DMA memory for request/response queues.\n"));
463 bzero(ch->dma.work, sc->sc_edma_qlen * (sizeof(struct sata_crqb) +
464 sizeof(struct sata_crpb)));
465 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
466 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
468 /* Turn off EDMA engine */
469 error = sata_edma_ctrl(dev, 0);
476 * Initialize EDMA engine:
477 * - Native Command Queuing off,
478 * - Non-Queued operation,
479 * - Host Queue Cache enabled.
481 SATA_OUTL(sc, SATA_EDMA_CFG(ch->unit), SATA_EDMA_CFG_HQCACHE |
482 (sc->sc_version == 1) ? SATA_EDMA_CFG_QL128 : 0);
484 /* Set request queue pointers */
485 work = ch->dma.work_bus;
486 SATA_OUTL(sc, SATA_EDMA_REQBAHR(ch->unit), work >> 32);
487 SATA_OUTL(sc, SATA_EDMA_REQIPR(ch->unit), work & 0xFFFFFFFF);
488 SATA_OUTL(sc, SATA_EDMA_REQOPR(ch->unit), work & 0xFFFFFFFF);
490 /* Set response queue pointers */
491 work += sc->sc_edma_qlen * sizeof(struct sata_crqb);
492 SATA_OUTL(sc, SATA_EDMA_RESBAHR(ch->unit), work >> 32);
493 SATA_OUTL(sc, SATA_EDMA_RESIPR(ch->unit), work & 0xFFFFFFFF);
494 SATA_OUTL(sc, SATA_EDMA_RESOPR(ch->unit), work & 0xFFFFFFFF);
496 /* Clear any outstanding interrupts */
497 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
498 SATA_OUTL(sc, SATA_SATA_FISICR(ch->unit), 0);
499 SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
500 SATA_OUTL(sc, SATA_ICR,
501 ~(SATA_ICR_DEV(ch->unit) | SATA_ICR_DMADONE(ch->unit)));
503 /* Umask channel interrupts */
504 SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0xFFFFFFFF);
505 SATA_OUTL(sc, SATA_MIMR, SATA_INL(sc, SATA_MIMR) |
506 SATA_MICR_DONE(ch->unit) | SATA_MICR_DMADONE(ch->unit) |
507 SATA_MICR_ERR(ch->unit));
511 return (ata_attach(dev));
515 sata_channel_detach(device_t dev)
517 struct sata_softc *sc;
518 struct ata_channel *ch;
521 sc = device_get_softc(device_get_parent(dev));
522 ch = device_get_softc(dev);
527 /* Turn off EDMA engine */
528 sata_edma_ctrl(dev, 0);
530 /* Mask chanel interrupts */
531 SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0);
532 SATA_OUTL(sc, SATA_MIMR, SATA_INL(sc, SATA_MIMR) & ~(
533 SATA_MICR_DONE(ch->unit) | SATA_MICR_DMADONE(ch->unit) |
534 SATA_MICR_ERR(ch->unit)));
536 error = ata_detach(dev);
545 sata_channel_begin_transaction(struct ata_request *request)
547 struct sata_softc *sc;
548 struct ata_channel *ch;
549 struct sata_crqb *crqb;
553 sc = device_get_softc(device_get_parent(request->parent));
554 ch = device_get_softc(request->parent);
556 mtx_assert(&ch->state_mtx, MA_OWNED);
558 /* Only DMA R/W goes through the EDMA machine. */
559 if (request->u.ata.command != ATA_READ_DMA &&
560 request->u.ata.command != ATA_WRITE_DMA &&
561 request->u.ata.command != ATA_READ_DMA48 &&
562 request->u.ata.command != ATA_WRITE_DMA48) {
564 /* Disable EDMA before accessing legacy registers */
565 if (sata_edma_is_running(request->parent)) {
566 error = sata_edma_ctrl(request->parent, 0);
568 request->result = error;
569 return (ATA_OP_FINISHED);
573 return (ata_begin_transaction(request));
576 /* Prepare data for DMA */
577 if ((error = ch->dma.load(request, NULL, NULL))) {
578 device_printf(request->parent, "setting up DMA failed!\n");
579 request->result = error;
580 return ATA_OP_FINISHED;
583 /* Get next free queue slot */
584 req_in = SATA_INL(sc, SATA_EDMA_REQIPR(ch->unit));
585 slot = (req_in & sc->sc_edma_reqis_mask) >> SATA_EDMA_REQIS_OFS;
586 crqb = (struct sata_crqb *)(ch->dma.work +
587 (slot << SATA_EDMA_REQIS_OFS));
589 /* Fill in request */
590 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
591 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
593 crqb->crqb_prdlo = htole32((uint64_t)request->dma->sg_bus & 0xFFFFFFFF);
594 crqb->crqb_prdhi = htole32((uint64_t)request->dma->sg_bus >> 32);
595 crqb->crqb_flags = htole32((request->flags & ATA_R_READ ? 0x01 : 0x00) |
596 (request->tag << 1));
598 crqb->crqb_ata_command = request->u.ata.command;
599 crqb->crqb_ata_feature = request->u.ata.feature;
600 crqb->crqb_ata_lba_low = request->u.ata.lba;
601 crqb->crqb_ata_lba_mid = request->u.ata.lba >> 8;
602 crqb->crqb_ata_lba_high = request->u.ata.lba >> 16;
603 crqb->crqb_ata_device = ((request->u.ata.lba >> 24) & 0x0F) | (1 << 6);
604 crqb->crqb_ata_lba_low_p = request->u.ata.lba >> 24;
605 crqb->crqb_ata_lba_mid_p = request->u.ata.lba >> 32;
606 crqb->crqb_ata_lba_high_p = request->u.ata.lba >> 40;
607 crqb->crqb_ata_feature_p = request->u.ata.feature >> 8;
608 crqb->crqb_ata_count = request->u.ata.count;
609 crqb->crqb_ata_count_p = request->u.ata.count >> 8;
611 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
612 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
614 /* Enable EDMA if disabled */
615 if (!sata_edma_is_running(request->parent)) {
616 error = sata_edma_ctrl(request->parent, 1);
618 ch->dma.unload(request);
619 request->result = error;
620 return (ATA_OP_FINISHED);
624 /* Tell EDMA about new request */
625 req_in = (req_in & ~sc->sc_edma_reqis_mask) | (((slot + 1) <<
626 SATA_EDMA_REQIS_OFS) & sc->sc_edma_reqis_mask);
628 SATA_OUTL(sc, SATA_EDMA_REQIPR(ch->unit), req_in);
630 return (ATA_OP_CONTINUES);
634 sata_channel_end_transaction(struct ata_request *request)
636 struct sata_softc *sc;
637 struct ata_channel *ch;
638 struct sata_crpb *crpb;
639 uint32_t res_in, res_out, icr;
642 sc = device_get_softc(device_get_parent(request->parent));
643 ch = device_get_softc(request->parent);
645 mtx_assert(&ch->state_mtx, MA_OWNED);
647 icr = SATA_INL(sc, SATA_ICR);
648 if (icr & SATA_ICR_DMADONE(ch->unit)) {
649 /* Get current response slot */
650 res_out = SATA_INL(sc, SATA_EDMA_RESOPR(ch->unit));
651 slot = (res_out & sc->sc_edma_resos_mask) >>
653 crpb = (struct sata_crpb *)(ch->dma.work +
654 (sc->sc_edma_qlen * sizeof(struct sata_crqb)) +
655 (slot << SATA_EDMA_RESOS_OFS));
657 /* Record this request status */
658 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
659 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
661 request->status = crpb->crpb_dev_status;
664 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
667 /* Update response queue pointer */
668 res_out = (res_out & ~sc->sc_edma_resos_mask) | (((slot + 1) <<
669 SATA_EDMA_RESOS_OFS) & sc->sc_edma_resos_mask);
671 SATA_OUTL(sc, SATA_EDMA_RESOPR(ch->unit), res_out);
673 /* Ack DMA interrupt if there is nothing more to do */
674 res_in = SATA_INL(sc, SATA_EDMA_RESIPR(ch->unit));
675 res_in &= sc->sc_edma_resos_mask;
676 res_out &= sc->sc_edma_resos_mask;
678 if (res_in == res_out)
679 SATA_OUTL(sc, SATA_ICR,
680 ~SATA_ICR_DMADONE(ch->unit));
682 /* Update progress */
683 if (!(request->status & ATA_S_ERROR) &&
684 !(request->flags & ATA_R_TIMEOUT))
685 request->donecount = request->bytecount;
687 /* Unload DMA data */
688 ch->dma.unload(request);
690 return(ATA_OP_FINISHED);
693 /* Legacy ATA interrupt */
694 return (ata_end_transaction(request));
698 sata_channel_status(device_t dev)
700 struct sata_softc *sc;
701 struct ata_channel *ch;
704 sc = device_get_softc(device_get_parent(dev));
705 ch = device_get_softc(dev);
707 icr = SATA_INL(sc, SATA_ICR);
708 iecr = SATA_INL(sc, SATA_EDMA_IECR(ch->unit));
710 if ((icr & SATA_ICR_DEV(ch->unit)) || iecr) {
711 /* Disable EDMA before accessing SATA registers */
712 sata_edma_ctrl(dev, 0);
713 ata_sata_phy_check_events(dev, -1);
715 /* Ack device and error interrupt */
716 SATA_OUTL(sc, SATA_ICR, ~SATA_ICR_DEV(ch->unit));
717 SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
720 icr &= SATA_ICR_DEV(ch->unit) | SATA_ICR_DMADONE(ch->unit);
725 sata_channel_reset(device_t dev)
727 struct sata_softc *sc;
728 struct ata_channel *ch;
730 sc = device_get_softc(device_get_parent(dev));
731 ch = device_get_softc(dev);
733 /* Disable EDMA before using legacy registers */
734 sata_edma_ctrl(dev, 0);
736 /* Mask all EDMA interrups */
737 SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0);
740 SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), SATA_EDMA_CMD_RESET);
742 SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), 0);
744 /* Reset PHY and device */
745 if (ata_sata_phy_reset(dev, -1, 1))
746 ata_generic_reset(dev);
750 /* Clear EDMA errors */
751 SATA_OUTL(sc, SATA_SATA_FISICR(ch->unit), 0);
752 SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
754 /* Unmask all EDMA interrups */
755 SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0xFFFFFFFF);
759 sata_channel_setmode(device_t parent, int target, int mode)
762 /* Disable EDMA before using legacy registers */
763 sata_edma_ctrl(parent, 0);
764 return (ata_sata_setmode(parent, target, mode));
768 sata_channel_getrev(device_t parent, int target)
771 /* Disable EDMA before using legacy registers */
772 sata_edma_ctrl(parent, 0);
773 return (ata_sata_getrev(parent, target));
777 sata_channel_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
780 struct ata_dmasetprd_args *args;
781 struct sata_prdentry *prd;
787 if ((args->error = error))
790 for (i = 0; i < nsegs; i++) {
791 prd[i].prd_addrlo = htole32(segs[i].ds_addr);
792 prd[i].prd_addrhi = htole32((uint64_t)segs[i].ds_addr >> 32);
793 prd[i].prd_count = htole32(segs[i].ds_len);
796 prd[i - 1].prd_count |= htole32(ATA_DMA_EOT);
797 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries.\n"));
802 sata_edma_ctrl(device_t dev, int on)
804 struct sata_softc *sc;
805 struct ata_channel *ch;
809 sc = device_get_softc(device_get_parent(dev));
810 ch = device_get_softc(dev);
811 bit = on ? SATA_EDMA_CMD_ENABLE : SATA_EDMA_CMD_DISABLE;
812 timeout = EDMA_TIMEOUT;
814 SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), bit);
819 reg = SATA_INL(sc, SATA_EDMA_CMD(ch->unit));
821 /* Enable bit will be 1 after disable command completion */
822 if (on && (reg & SATA_EDMA_CMD_ENABLE))
825 /* Disable bit will be 0 after disable command completion */
826 if (!on && !(reg & SATA_EDMA_CMD_DISABLE))
829 if (timeout-- <= 0) {
830 device_printf(dev, "EDMA command timeout!\n");
839 sata_edma_is_running(device_t dev)
841 struct sata_softc *sc;
842 struct ata_channel *ch;
844 sc = device_get_softc(device_get_parent(dev));
845 ch = device_get_softc(dev);
847 return (SATA_INL(sc, SATA_EDMA_CMD(ch->unit)) & SATA_EDMA_CMD_ENABLE);
850 static device_method_t sata_channel_methods[] = {
851 /* Device interface. */
852 DEVMETHOD(device_probe, sata_channel_probe),
853 DEVMETHOD(device_attach, sata_channel_attach),
854 DEVMETHOD(device_detach, sata_channel_detach),
855 DEVMETHOD(device_shutdown, bus_generic_shutdown),
856 DEVMETHOD(device_suspend, ata_suspend),
857 DEVMETHOD(device_resume, ata_resume),
859 /* ATA channel interface */
860 DEVMETHOD(ata_reset, sata_channel_reset),
861 DEVMETHOD(ata_setmode, sata_channel_setmode),
862 DEVMETHOD(ata_getrev, sata_channel_getrev),
866 driver_t sata_channel_driver = {
868 sata_channel_methods,
869 sizeof(struct ata_channel),
872 DRIVER_MODULE(ata, sata, sata_channel_driver, ata_devclass, 0, 0);