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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_SRXX_TYPEDEFS_H__
53 #define __CVMX_SRXX_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
61 cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
62 return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
73 cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id);
74 return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
79 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80 static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
83 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
85 cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
86 return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
89 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
91 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
92 static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
95 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
96 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
97 cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
98 return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
103 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104 static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
107 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
109 cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
121 cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id);
122 return CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull;
125 #define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
131 * SRX_COM_CTL - Spi receive common control
136 * Both the calendar table and the LEN and M parameters must be completely
137 * setup before writing the Interface enable (INF_EN) and Status channel
138 * enabled (ST_EN) asserted.
140 union cvmx_srxx_com_ctl
143 struct cvmx_srxx_com_ctl_s
145 #if __BYTE_ORDER == __BIG_ENDIAN
146 uint64_t reserved_8_63 : 56;
147 uint64_t prts : 4; /**< Number of ports in the receiver (write: ports - 1)
153 uint64_t st_en : 1; /**< Status channel enabled
154 This is to allow configs without a status channel.
155 This bit should not be modified once the
156 interface is enabled. */
157 uint64_t reserved_1_2 : 2;
158 uint64_t inf_en : 1; /**< Interface enable
159 The master switch that enables the entire
160 interface. SRX will not validiate any data until
161 this bit is set. This bit should not be modified
162 once the interface is enabled. */
165 uint64_t reserved_1_2 : 2;
168 uint64_t reserved_8_63 : 56;
171 struct cvmx_srxx_com_ctl_s cn38xx;
172 struct cvmx_srxx_com_ctl_s cn38xxp2;
173 struct cvmx_srxx_com_ctl_s cn58xx;
174 struct cvmx_srxx_com_ctl_s cn58xxp1;
176 typedef union cvmx_srxx_com_ctl cvmx_srxx_com_ctl_t;
179 * cvmx_srx#_ign_rx_full
181 * SRX_IGN_RX_FULL - Ignore RX FIFO backpressure
186 * If a device can not or should not assert backpressure, then setting DROP
187 * will force STARVING status on the status channel for all ports. This
188 * eliminates any back pressure from N2.
190 * This implies that it's ok drop packets when the FIFOS fill up.
192 * A side effect of this mode is that the TPA Watcher will effectively be
193 * disabled. Since the DROP mode forces all TPA lines asserted, the TPA
194 * Watcher will never find a cycle where the TPA for the selected port is
195 * deasserted in order to increment its count.
197 union cvmx_srxx_ign_rx_full
200 struct cvmx_srxx_ign_rx_full_s
202 #if __BYTE_ORDER == __BIG_ENDIAN
203 uint64_t reserved_16_63 : 48;
204 uint64_t ignore : 16; /**< This port should ignore backpressure hints from
205 GMX when the RX FIFO fills up
206 - 0: Use GMX backpressure
207 - 1: Ignore GMX backpressure */
209 uint64_t ignore : 16;
210 uint64_t reserved_16_63 : 48;
213 struct cvmx_srxx_ign_rx_full_s cn38xx;
214 struct cvmx_srxx_ign_rx_full_s cn38xxp2;
215 struct cvmx_srxx_ign_rx_full_s cn58xx;
216 struct cvmx_srxx_ign_rx_full_s cn58xxp1;
218 typedef union cvmx_srxx_ign_rx_full cvmx_srxx_ign_rx_full_t;
221 * cvmx_srx#_spi4_cal#
223 * specify the RSL base addresses for the block
224 * SRX_SPI4_CAL - Spi4 Calender table
225 * direct_calendar_write / direct_calendar_read
228 * There are 32 calendar table CSR's, each containing 4 entries for a
229 * total of 128 entries. In the above definition...
231 * n = calendar table offset * 4
233 * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
234 * (with n == 0). Offset 0x10 is the 16th entry in the calendar table
235 * and would contain entries (16*4) = 64, 65, 66, and 67.
238 * Calendar table entry accesses (read or write) can only occur
239 * if the interface is disabled. All other accesses will be
242 * Both the calendar table and the LEN and M parameters must be
243 * completely setup before writing the Interface enable (INF_EN) and
244 * Status channel enabled (ST_EN) asserted.
246 union cvmx_srxx_spi4_calx
249 struct cvmx_srxx_spi4_calx_s
251 #if __BYTE_ORDER == __BIG_ENDIAN
252 uint64_t reserved_17_63 : 47;
253 uint64_t oddpar : 1; /**< Odd parity over SRX_SPI4_CAL[15:0]
254 (^SRX_SPI4_CAL[16:0] === 1'b1) | $NS NS */
255 uint64_t prt3 : 4; /**< Status for port n+3 */
256 uint64_t prt2 : 4; /**< Status for port n+2 */
257 uint64_t prt1 : 4; /**< Status for port n+1 */
258 uint64_t prt0 : 4; /**< Status for port n+0 */
265 uint64_t reserved_17_63 : 47;
268 struct cvmx_srxx_spi4_calx_s cn38xx;
269 struct cvmx_srxx_spi4_calx_s cn38xxp2;
270 struct cvmx_srxx_spi4_calx_s cn58xx;
271 struct cvmx_srxx_spi4_calx_s cn58xxp1;
273 typedef union cvmx_srxx_spi4_calx cvmx_srxx_spi4_calx_t;
276 * cvmx_srx#_spi4_stat
278 * SRX_SPI4_STAT - Spi4 status channel control
283 * Both the calendar table and the LEN and M parameters must be
284 * completely setup before writing the Interface enable (INF_EN) and
285 * Status channel enabled (ST_EN) asserted.
287 * Current rev only supports LVTTL status IO
289 union cvmx_srxx_spi4_stat
292 struct cvmx_srxx_spi4_stat_s
294 #if __BYTE_ORDER == __BIG_ENDIAN
295 uint64_t reserved_16_63 : 48;
296 uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */
297 uint64_t reserved_7_7 : 1;
298 uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */
301 uint64_t reserved_7_7 : 1;
303 uint64_t reserved_16_63 : 48;
306 struct cvmx_srxx_spi4_stat_s cn38xx;
307 struct cvmx_srxx_spi4_stat_s cn38xxp2;
308 struct cvmx_srxx_spi4_stat_s cn58xx;
309 struct cvmx_srxx_spi4_stat_s cn58xxp1;
311 typedef union cvmx_srxx_spi4_stat cvmx_srxx_spi4_stat_t;
314 * cvmx_srx#_sw_tick_ctl
316 * SRX_SW_TICK_CTL - Create a software tick of Spi4 data. A write to this register will create a data tick.
319 union cvmx_srxx_sw_tick_ctl
322 struct cvmx_srxx_sw_tick_ctl_s
324 #if __BYTE_ORDER == __BIG_ENDIAN
325 uint64_t reserved_14_63 : 50;
326 uint64_t eop : 1; /**< SW Tick EOP
328 uint64_t sop : 1; /**< SW Tick SOP
330 uint64_t mod : 4; /**< SW Tick MOD - valid byte count
332 uint64_t opc : 4; /**< SW Tick ERR - packet had an error
334 uint64_t adr : 4; /**< SW Tick port address
342 uint64_t reserved_14_63 : 50;
345 struct cvmx_srxx_sw_tick_ctl_s cn38xx;
346 struct cvmx_srxx_sw_tick_ctl_s cn58xx;
347 struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
349 typedef union cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_ctl_t;
352 * cvmx_srx#_sw_tick_dat
354 * SRX_SW_TICK_DAT - Create a software tick of Spi4 data
357 union cvmx_srxx_sw_tick_dat
360 struct cvmx_srxx_sw_tick_dat_s
362 #if __BYTE_ORDER == __BIG_ENDIAN
363 uint64_t dat : 64; /**< Data tick when SRX_SW_TICK_CTL is written
369 struct cvmx_srxx_sw_tick_dat_s cn38xx;
370 struct cvmx_srxx_sw_tick_dat_s cn58xx;
371 struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
373 typedef union cvmx_srxx_sw_tick_dat cvmx_srxx_sw_tick_dat_t;