2 * Product specific probe and attach routines for:
3 * aic7901 and aic7902 SCSI controllers
5 * Copyright (c) 1994-2001 Justin T. Gibbs.
6 * Copyright (c) 2000-2002 Adaptec Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * substantially similar to the "NO WARRANTY" disclaimer below
17 * ("Disclaimer") and any redistribution must be conditioned upon
18 * including a substantially similar Disclaimer requirement for further
19 * binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGES.
41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $
45 #include "aic79xx_osm.h"
46 #include "aic79xx_inline.h"
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD$");
50 #include <dev/aic7xxx/aic79xx_osm.h>
51 #include <dev/aic7xxx/aic79xx_inline.h>
54 static __inline uint64_t
55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
61 | ((uint64_t)vendor << 32)
62 | ((uint64_t)device << 48);
67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
68 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull
69 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
70 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
71 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull
73 #define ID_AIC7901 0x800F9005FFFF9005ull
74 #define ID_AHA_29320A 0x8000900500609005ull
75 #define ID_AHA_29320ALP 0x8017900500449005ull
77 #define ID_AIC7901A 0x801E9005FFFF9005ull
78 #define ID_AHA_29320LP 0x8014900500449005ull
80 #define ID_AIC7902 0x801F9005FFFF9005ull
81 #define ID_AIC7902_B 0x801D9005FFFF9005ull
82 #define ID_AHA_39320 0x8010900500409005ull
83 #define ID_AHA_29320 0x8012900500429005ull
84 #define ID_AHA_29320B 0x8013900500439005ull
85 #define ID_AHA_39320_B 0x8015900500409005ull
86 #define ID_AHA_39320_B_DELL 0x8015900501681028ull
87 #define ID_AHA_39320A 0x8016900500409005ull
88 #define ID_AHA_39320D 0x8011900500419005ull
89 #define ID_AHA_39320D_B 0x801C900500419005ull
90 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull
91 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
92 #define ID_AHA_39320LPE 0x8017900500459005ull
93 #define ID_AIC7902_PCI_REV_A4 0x3
94 #define ID_AIC7902_PCI_REV_B0 0x10
95 #define SUBID_HP 0x0E11
97 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
99 #define DEVID_9005_TYPE(id) ((id) & 0xF)
100 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
101 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
102 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
104 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
106 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
108 #define SUBID_9005_TYPE(id) ((id) & 0xF)
109 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
110 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
112 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
114 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
116 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
117 #define SUBID_9005_SEEPTYPE_NONE 0x0
118 #define SUBID_9005_SEEPTYPE_4K 0x1
120 static ahd_device_setup_t ahd_aic7901_setup;
121 static ahd_device_setup_t ahd_aic7901A_setup;
122 static ahd_device_setup_t ahd_aic7902_setup;
123 static ahd_device_setup_t ahd_aic790X_setup;
125 struct ahd_pci_identity ahd_pci_ident_table [] =
127 /* aic7901 based controllers */
131 "Adaptec 29320A Ultra320 SCSI adapter",
137 "Adaptec 29320ALP Ultra320 SCSI adapter",
140 /* aic7901A based controllers */
144 "Adaptec 29320LP Ultra320 SCSI adapter",
147 /* aic7902 based controllers */
151 "Adaptec 29320 Ultra320 SCSI adapter",
157 "Adaptec 29320B Ultra320 SCSI adapter",
163 "Adaptec 39320 Ultra320 SCSI adapter",
169 "Adaptec 39320 Ultra320 SCSI adapter",
175 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
181 "Adaptec 39320A Ultra320 SCSI adapter",
187 "Adaptec 39320D Ultra320 SCSI adapter",
193 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
199 "Adaptec 39320D Ultra320 SCSI adapter",
205 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
211 "Adaptec 39320LPE Ultra320 SCSI adapter",
214 /* Generic chip probes for devices we don't know 'exactly' */
216 ID_AIC7901 & ID_9005_GENERIC_MASK,
217 ID_9005_GENERIC_MASK,
218 "Adaptec AIC7901 Ultra320 SCSI adapter",
222 ID_AIC7901A & ID_DEV_VENDOR_MASK,
224 "Adaptec AIC7901A Ultra320 SCSI adapter",
228 ID_AIC7902 & ID_9005_GENERIC_MASK,
229 ID_9005_GENERIC_MASK,
230 "Adaptec AIC7902 Ultra320 SCSI adapter",
235 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
237 #define DEVCONFIG 0x40
238 #define PCIXINITPAT 0x0000E000ul
239 #define PCIXINIT_PCI33_66 0x0000E000ul
240 #define PCIXINIT_PCIX50_66 0x0000C000ul
241 #define PCIXINIT_PCIX66_100 0x0000A000ul
242 #define PCIXINIT_PCIX100_133 0x00008000ul
243 #define PCI_BUS_MODES_INDEX(devconfig) \
244 (((devconfig) & PCIXINITPAT) >> 13)
245 static const char *pci_bus_modes[] =
247 "PCI bus mode unknown",
248 "PCI bus mode unknown",
249 "PCI bus mode unknown",
250 "PCI bus mode unknown",
257 #define TESTMODE 0x00000800ul
258 #define IRDY_RST 0x00000200ul
259 #define FRAME_RST 0x00000100ul
260 #define PCI64BIT 0x00000080ul
261 #define MRDCEN 0x00000040ul
262 #define ENDIANSEL 0x00000020ul
263 #define MIXQWENDIANEN 0x00000008ul
264 #define DACEN 0x00000004ul
265 #define STPWLEVEL 0x00000002ul
266 #define QWENDIANSEL 0x00000001ul
268 #define DEVCONFIG1 0x44
271 #define CSIZE_LATTIME 0x0c
272 #define CACHESIZE 0x000000fful
273 #define LATTIME 0x0000ff00ul
275 static int ahd_check_extport(struct ahd_softc *ahd);
276 static void ahd_configure_termination(struct ahd_softc *ahd,
277 u_int adapter_control);
278 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
280 struct ahd_pci_identity *
281 ahd_find_pci_device(aic_dev_softc_t pci)
288 struct ahd_pci_identity *entry;
291 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
292 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
293 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
294 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
295 full_id = ahd_compose_id(device,
301 * If we are configured to attach to HostRAID
302 * controllers, mask out the IROC/HostRAID bit
305 if (ahd_attach_to_HostRAID_controllers)
306 full_id &= ID_ALL_IROC_MASK;
308 for (i = 0; i < ahd_num_pci_devs; i++) {
309 entry = &ahd_pci_ident_table[i];
310 if (entry->full_id == (full_id & entry->id_mask)) {
311 /* Honor exclusion entries. */
312 if (entry->name == NULL)
321 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
323 struct scb_data *shared_scb_data;
330 shared_scb_data = NULL;
331 ahd->description = entry->name;
333 * Record if this is a HostRAID board.
335 device = aic_pci_read_config(ahd->dev_softc,
336 PCIR_DEVICE, /*bytes*/2);
337 if (DEVID_9005_HOSTRAID(device))
338 ahd->flags |= AHD_HOSTRAID_BOARD;
341 * Record if this is an HP board.
343 subvendor = aic_pci_read_config(ahd->dev_softc,
344 PCIR_SUBVEND_0, /*bytes*/2);
345 if (subvendor == SUBID_HP)
346 ahd->flags |= AHD_HP_BOARD;
348 error = entry->setup(ahd);
353 * Find the PCI-X cap pointer. If we don't find it,
354 * pcix_ptr will be 0.
356 pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr);
357 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
358 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
359 ahd->chip |= AHD_PCI;
360 /* Disable PCIX workarounds when running in PCI mode. */
361 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
363 ahd->chip |= AHD_PCIX;
364 if (ahd->pcix_ptr == 0)
367 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
369 aic_power_state_change(ahd, AIC_POWER_STATE_D0);
371 error = ahd_pci_map_registers(ahd);
376 * If we need to support high memory, enable dual
377 * address cycles. This bit must be set to enable
378 * high address bit generation even if we are on a
379 * 64bit bus (PCI64BIT set in devconfig).
381 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
385 printf("%s: Enabling 39Bit Addressing\n",
387 devconfig = aic_pci_read_config(ahd->dev_softc,
388 DEVCONFIG, /*bytes*/4);
390 aic_pci_write_config(ahd->dev_softc, DEVCONFIG,
391 devconfig, /*bytes*/4);
394 /* Ensure busmastering is enabled */
395 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
396 command |= PCIM_CMD_BUSMASTEREN;
397 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
399 error = ahd_softc_init(ahd);
403 ahd->bus_intr = ahd_pci_intr;
405 error = ahd_reset(ahd, /*reinit*/FALSE);
410 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
411 /*bytes*/1) & CACHESIZE;
412 ahd->pci_cachesize *= 4;
414 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
415 /* See if we have a SEEPROM and perform auto-term */
416 error = ahd_check_extport(ahd);
420 /* Core initialization */
421 error = ahd_init(ahd);
426 * Allow interrupts now that we are completely setup.
428 error = ahd_pci_map_int(ahd);
434 * Link this softc in with all other ahd instances.
436 ahd_softc_insert(ahd);
442 * Perform some simple tests that should catch situations where
443 * our registers are invalidly mapped.
446 ahd_pci_test_register_access(struct ahd_softc *ahd)
457 * Enable PCI error interrupt status, but suppress NMIs
458 * generated by SERR raised due to target aborts.
460 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
461 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
462 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
465 * First a simple test to see if any
466 * registers can be read. Reading
467 * HCNTRL has no side effects and has
468 * at least one bit that is guaranteed to
469 * be zero so it is a good register to
472 hcntrl = ahd_inb(ahd, HCNTRL);
477 * Next create a situation where write combining
478 * or read prefetching could be initiated by the
479 * CPU or host bridge. Our device does not support
480 * either, so look for data corruption and/or flaged
481 * PCI errors. First pause without causing another
485 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
486 while (ahd_is_paused(ahd) == 0)
489 /* Clear any PCI errors that occurred before our driver attached. */
490 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
491 targpcistat = ahd_inb(ahd, TARGPCISTAT);
492 ahd_outb(ahd, TARGPCISTAT, targpcistat);
493 pci_status1 = aic_pci_read_config(ahd->dev_softc,
494 PCIR_STATUS + 1, /*bytes*/1);
495 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
496 pci_status1, /*bytes*/1);
497 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
498 ahd_outb(ahd, CLRINT, CLRPCIINT);
500 ahd_outb(ahd, SEQCTL0, PERRORDIS);
501 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
502 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
505 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
508 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
509 targpcistat = ahd_inb(ahd, TARGPCISTAT);
510 if ((targpcistat & STA) != 0)
517 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
519 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
520 targpcistat = ahd_inb(ahd, TARGPCISTAT);
522 /* Silently clear any latched errors. */
523 ahd_outb(ahd, TARGPCISTAT, targpcistat);
524 pci_status1 = aic_pci_read_config(ahd->dev_softc,
525 PCIR_STATUS + 1, /*bytes*/1);
526 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
527 pci_status1, /*bytes*/1);
528 ahd_outb(ahd, CLRINT, CLRPCIINT);
530 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
531 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
536 * Check the external port logic for a serial eeprom
537 * and termination/cable detection contrls.
540 ahd_check_extport(struct ahd_softc *ahd)
542 struct vpd_config vpd;
543 struct seeprom_config *sc;
544 u_int adapter_control;
548 sc = ahd->seep_config;
549 have_seeprom = ahd_acquire_seeprom(ahd);
554 * Fetch VPD for this function and parse it.
557 printf("%s: Reading VPD from SEEPROM...",
560 /* Address is always in units of 16bit words */
561 start_addr = ((2 * sizeof(*sc))
562 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
564 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
565 start_addr, sizeof(vpd)/2,
568 error = ahd_parse_vpddata(ahd, &vpd);
570 printf("%s: VPD parsing %s\n",
572 error == 0 ? "successful" : "failed");
575 printf("%s: Reading SEEPROM...", ahd_name(ahd));
577 /* Address is always in units of 16bit words */
578 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
580 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
581 start_addr, sizeof(*sc)/2,
582 /*bytestream*/FALSE);
585 printf("Unable to read SEEPROM\n");
588 have_seeprom = ahd_verify_cksum(sc);
591 if (have_seeprom == 0)
592 printf ("checksum error\n");
597 ahd_release_seeprom(ahd);
604 * Pull scratch ram settings and treat them as
605 * if they are the contents of an seeprom if
606 * the 'ADPT', 'BIOS', or 'ASPI' signature is found
607 * in SCB 0xFF. We manually compose the data as 16bit
608 * values to avoid endian issues.
610 ahd_set_scbptr(ahd, 0xFF);
611 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
612 if (nvram_scb != 0xFF
613 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
614 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
615 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
616 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
617 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
618 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
619 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
620 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
621 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
622 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
623 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
624 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
628 ahd_set_scbptr(ahd, nvram_scb);
629 sc_data = (uint16_t *)sc;
630 for (i = 0; i < 64; i += 2)
631 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
632 have_seeprom = ahd_verify_cksum(sc);
634 ahd->flags |= AHD_SCB_CONFIG_USED;
639 if (have_seeprom != 0
640 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
644 printf("%s: Seeprom Contents:", ahd_name(ahd));
645 sc_data = (uint16_t *)sc;
646 for (i = 0; i < (sizeof(*sc)); i += 2)
647 printf("\n\t0x%.4x", sc_data[i]);
654 printf("%s: No SEEPROM available.\n", ahd_name(ahd));
655 ahd->flags |= AHD_USEDEFAULTS;
656 error = ahd_default_config(ahd);
657 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
658 free(ahd->seep_config, M_DEVBUF);
659 ahd->seep_config = NULL;
661 error = ahd_parse_cfgdata(ahd, sc);
662 adapter_control = sc->adapter_control;
667 ahd_configure_termination(ahd, adapter_control);
673 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
680 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
681 devconfig &= ~STPWLEVEL;
682 if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
683 devconfig |= STPWLEVEL;
685 printf("%s: STPWLEVEL is %s\n",
686 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
687 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
689 /* Make sure current sensing is off. */
690 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
691 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
695 * Read to sense. Write to set.
697 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
698 if ((adapter_control & CFAUTOTERM) == 0) {
700 printf("%s: Manual Primary Termination\n",
702 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
703 if ((adapter_control & CFSTERM) != 0)
704 termctl |= FLX_TERMCTL_ENPRILOW;
705 if ((adapter_control & CFWSTERM) != 0)
706 termctl |= FLX_TERMCTL_ENPRIHIGH;
707 } else if (error != 0) {
708 printf("%s: Primary Auto-Term Sensing failed! "
709 "Using Defaults.\n", ahd_name(ahd));
710 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
713 if ((adapter_control & CFSEAUTOTERM) == 0) {
715 printf("%s: Manual Secondary Termination\n",
717 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
718 if ((adapter_control & CFSELOWTERM) != 0)
719 termctl |= FLX_TERMCTL_ENSECLOW;
720 if ((adapter_control & CFSEHIGHTERM) != 0)
721 termctl |= FLX_TERMCTL_ENSECHIGH;
722 } else if (error != 0) {
723 printf("%s: Secondary Auto-Term Sensing failed! "
724 "Using Defaults.\n", ahd_name(ahd));
725 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
729 * Now set the termination based on what we found.
731 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
732 ahd->flags &= ~AHD_TERM_ENB_A;
733 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
734 ahd->flags |= AHD_TERM_ENB_A;
737 /* Must set the latch once in order to be effective. */
738 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
739 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
741 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
743 printf("%s: Unable to set termination settings!\n",
745 } else if (bootverbose) {
746 printf("%s: Primary High byte termination %sabled\n",
748 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
750 printf("%s: Primary Low byte termination %sabled\n",
752 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
754 printf("%s: Secondary High byte termination %sabled\n",
756 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
758 printf("%s: Secondary Low byte termination %sabled\n",
760 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
772 static const char *split_status_source[] =
780 static const char *pci_status_source[] =
792 static const char *split_status_strings[] =
794 "%s: Received split response in %s.\n",
795 "%s: Received split completion error message in %s\n",
796 "%s: Receive overrun in %s\n",
797 "%s: Count not complete in %s\n",
798 "%s: Split completion data bucket in %s\n",
799 "%s: Split completion address error in %s\n",
800 "%s: Split completion byte count error in %s\n",
801 "%s: Signaled Target-abort to early terminate a split in %s\n"
804 static const char *pci_status_strings[] =
806 "%s: Data Parity Error has been reported via PERR# in %s\n",
807 "%s: Target initial wait state error in %s\n",
808 "%s: Split completion read data parity error in %s\n",
809 "%s: Split completion address attribute parity error in %s\n",
810 "%s: Received a Target Abort in %s\n",
811 "%s: Received a Master Abort in %s\n",
812 "%s: Signal System Error Detected in %s\n",
813 "%s: Address or Write Phase Parity Error Detected in %s.\n"
817 ahd_pci_intr(struct ahd_softc *ahd)
819 uint8_t pci_status[8];
820 ahd_mode_state saved_modes;
826 intstat = ahd_inb(ahd, INTSTAT);
828 if ((intstat & SPLTINT) != 0)
829 ahd_pci_split_intr(ahd, intstat);
831 if ((intstat & PCIINT) == 0)
834 printf("%s: PCI error Interrupt\n", ahd_name(ahd));
835 saved_modes = ahd_save_modes(ahd);
836 ahd_dump_card_state(ahd);
837 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
838 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
842 pci_status[i] = ahd_inb(ahd, reg);
843 /* Clear latched errors. So our interrupt deasserts. */
844 ahd_outb(ahd, reg, pci_status[i]);
847 for (i = 0; i < 8; i++) {
853 for (bit = 0; bit < 8; bit++) {
855 if ((pci_status[i] & (0x1 << bit)) != 0) {
856 static const char *s;
858 s = pci_status_strings[bit];
859 if (i == 7/*TARG*/ && bit == 3)
860 s = "%s: Signaled Target Abort\n";
861 printf(s, ahd_name(ahd), pci_status_source[i]);
865 pci_status1 = aic_pci_read_config(ahd->dev_softc,
866 PCIR_STATUS + 1, /*bytes*/1);
867 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
868 pci_status1, /*bytes*/1);
869 ahd_restore_modes(ahd, saved_modes);
870 ahd_outb(ahd, CLRINT, CLRPCIINT);
875 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
877 uint8_t split_status[4];
878 uint8_t split_status1[4];
879 uint8_t sg_split_status[2];
880 uint8_t sg_split_status1[2];
881 ahd_mode_state saved_modes;
883 uint32_t pcix_status;
886 * Check for splits in all modes. Modes 0 and 1
887 * additionally have SG engine splits to look at.
889 pcix_status = aic_pci_read_config(ahd->dev_softc,
890 ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4);
891 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
892 ahd_name(ahd), pcix_status >> 16);
893 saved_modes = ahd_save_modes(ahd);
894 for (i = 0; i < 4; i++) {
895 ahd_set_modes(ahd, i, i);
897 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
898 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
899 /* Clear latched errors. So our interrupt deasserts. */
900 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
901 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
904 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
905 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
906 /* Clear latched errors. So our interrupt deasserts. */
907 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
908 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
911 for (i = 0; i < 4; i++) {
914 for (bit = 0; bit < 8; bit++) {
916 if ((split_status[i] & (0x1 << bit)) != 0) {
917 static const char *s;
919 s = split_status_strings[bit];
920 printf(s, ahd_name(ahd),
921 split_status_source[i]);
927 if ((sg_split_status[i] & (0x1 << bit)) != 0) {
928 static const char *s;
930 s = split_status_strings[bit];
931 printf(s, ahd_name(ahd), "SG");
936 * Clear PCI-X status bits.
938 aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS,
939 pcix_status, /*bytes*/4);
940 ahd_outb(ahd, CLRINT, CLRSPLTINT);
941 ahd_restore_modes(ahd, saved_modes);
945 ahd_aic7901_setup(struct ahd_softc *ahd)
948 ahd->chip = AHD_AIC7901;
949 ahd->features = AHD_AIC7901_FE;
950 return (ahd_aic790X_setup(ahd));
954 ahd_aic7901A_setup(struct ahd_softc *ahd)
957 ahd->chip = AHD_AIC7901A;
958 ahd->features = AHD_AIC7901A_FE;
959 return (ahd_aic790X_setup(ahd));
963 ahd_aic7902_setup(struct ahd_softc *ahd)
965 ahd->chip = AHD_AIC7902;
966 ahd->features = AHD_AIC7902_FE;
967 return (ahd_aic790X_setup(ahd));
971 ahd_aic790X_setup(struct ahd_softc *ahd)
976 pci = ahd->dev_softc;
977 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
978 if (rev < ID_AIC7902_PCI_REV_A4) {
979 printf("%s: Unable to attach to unsupported chip revision %d\n",
981 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
984 ahd->channel = aic_get_pci_function(pci) + 'A';
985 if (rev < ID_AIC7902_PCI_REV_B0) {
987 * Enable A series workarounds.
989 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
990 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
991 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
992 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
993 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
994 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
995 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
996 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
997 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
998 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
1002 * IO Cell paramter setup.
1004 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1006 if ((ahd->flags & AHD_HP_BOARD) == 0)
1007 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
1011 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
1012 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY;
1013 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
1016 * Some issues have been resolved in the 7901B.
1018 if ((ahd->features & AHD_MULTI_FUNC) != 0)
1019 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG
1020 | AHD_BUSFREEREV_BUG;
1023 * IO Cell paramter setup.
1025 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1026 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
1027 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1030 * Set the PREQDIS bit for H2B which disables some workaround
1031 * that doesn't work on regular PCI busses.
1032 * XXX - Find out exactly what this does from the hardware
1035 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1036 aic_pci_write_config(pci, DEVCONFIG1,
1037 devconfig1|PREQDIS, /*bytes*/1);
1038 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);