2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ah_eeprom_v14.h"
26 #include "ar5416/ar5416.h"
27 #include "ar5416/ar5416reg.h"
28 #include "ar5416/ar5416phy.h"
30 #define N(a) (sizeof(a)/sizeof(a[0]))
33 RF_HAL_FUNCS base; /* public state, must be first */
34 uint16_t pcdacTable[1];
43 /* NB: Bank*Data storage follows */
45 #define AR2133(ah) ((struct ar2133State *) AH5212(ah)->ah_rfHal)
47 #define ar5416ModifyRfBuffer ar5212ModifyRfBuffer /*XXX*/
49 void ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
50 uint32_t numBits, uint32_t firstBit, uint32_t column);
53 ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
56 (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
61 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
67 * if synth_freq < 2412
69 * else if 2412 <= synth_freq <= 2422
71 * else // synth_freq > 2422
73 * else if forceBias > 0
74 * bias = forceBias & 7
76 * no change, use value from ini file
78 * no change, invalid band
81 * 2422 also uses value of 2
85 * Less than 2412 uses value of 0, 2412 and above uses value of 2
88 ar2133ForceBias(struct ath_hal *ah, uint16_t synth_freq)
92 uint32_t new_bias = 0;
93 struct ar2133State *priv = AR2133(ah);
95 /* XXX this is a bit of a silly check for 2.4ghz channels -adrian */
96 if (synth_freq >= 3000)
99 if (synth_freq < 2412)
101 else if (synth_freq < 2422)
106 /* pre-reverse this field */
107 tmp_reg = ath_hal_reverseBits(new_bias, 3);
109 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Force rf_pwd_icsyndiv to %1d on %4d\n",
110 __func__, new_bias, synth_freq);
112 /* swizzle rf_pwd_icsyndiv */
113 ar5416ModifyRfBuffer(priv->Bank6Data, tmp_reg, 3, 181, 3);
115 /* write Bank 6 with new params */
116 ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6, priv->Bank6Data, reg_writes);
120 * Take the MHz channel value and set the Channel value
122 * ASSUMES: Writes enabled to analog bus
125 ar2133SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
127 uint32_t channelSel = 0;
128 uint32_t bModeSynth = 0;
129 uint32_t aModeRefSel = 0;
132 CHAN_CENTERS centers;
134 OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
136 ar5416GetChannelCenters(ah, chan, ¢ers);
137 freq = centers.synth_center;
142 if (((freq - 2192) % 5) == 0) {
143 channelSel = ((freq - 672) * 2 - 3040)/10;
145 } else if (((freq - 2224) % 5) == 0) {
146 channelSel = ((freq - 704) * 2 - 3040) / 10;
149 HALDEBUG(ah, HAL_DEBUG_ANY,
150 "%s: invalid channel %u MHz\n", __func__, freq);
154 channelSel = (channelSel << 2) & 0xff;
155 channelSel = ath_hal_reverseBits(channelSel, 8);
157 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
159 /* Enable channel spreading for channel 14 */
160 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
161 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
163 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
164 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
166 } else if ((freq % 20) == 0 && freq >= 5120) {
167 channelSel = ath_hal_reverseBits(((freq - 4800) / 20 << 2), 8);
168 if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah))
169 aModeRefSel = ath_hal_reverseBits(3, 2);
171 aModeRefSel = ath_hal_reverseBits(1, 2);
172 } else if ((freq % 10) == 0) {
173 channelSel = ath_hal_reverseBits(((freq - 4800) / 10 << 1), 8);
174 if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah))
175 aModeRefSel = ath_hal_reverseBits(2, 2);
177 aModeRefSel = ath_hal_reverseBits(1, 2);
178 } else if ((freq % 5) == 0) {
179 channelSel = ath_hal_reverseBits((freq - 4800) / 5, 8);
180 aModeRefSel = ath_hal_reverseBits(1, 2);
182 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
187 /* Workaround for hw bug - AR5416 specific */
188 if (AR_SREV_OWL(ah) && ah->ah_config.ah_ar5416_biasadj)
189 ar2133ForceBias(ah, freq);
191 reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
194 OS_REG_WRITE(ah, AR_PHY(0x37), reg32);
196 AH_PRIVATE(ah)->ah_curchan = chan;
202 * Return a reference to the requested RF Bank.
205 ar2133GetRfBank(struct ath_hal *ah, int bank)
207 struct ar2133State *priv = AR2133(ah);
209 HALASSERT(priv != AH_NULL);
211 case 1: return priv->Bank1Data;
212 case 2: return priv->Bank2Data;
213 case 3: return priv->Bank3Data;
214 case 6: return priv->Bank6Data;
215 case 7: return priv->Bank7Data;
217 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
223 * Reads EEPROM header info from device structure and programs
226 * REQUIRES: Access to the analog rf device
229 ar2133SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
230 uint16_t modesIndex, uint16_t *rfXpdGain)
232 struct ar2133State *priv = AR2133(ah);
237 /* Setup Bank 0 Write */
238 ath_hal_ini_bank_setup(priv->Bank0Data, &AH5416(ah)->ah_ini_bank0, 1);
240 /* Setup Bank 1 Write */
241 ath_hal_ini_bank_setup(priv->Bank1Data, &AH5416(ah)->ah_ini_bank1, 1);
243 /* Setup Bank 2 Write */
244 ath_hal_ini_bank_setup(priv->Bank2Data, &AH5416(ah)->ah_ini_bank2, 1);
246 /* Setup Bank 3 Write */
247 ath_hal_ini_bank_setup(priv->Bank3Data, &AH5416(ah)->ah_ini_bank3, modesIndex);
249 /* Setup Bank 6 Write */
250 ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex);
252 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
253 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
254 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 2ghz: OB_2:%d, DB_2:%d\n",
256 ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL),
257 ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL));
258 ar5416ModifyRfBuffer(priv->Bank6Data,
259 ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0);
260 ar5416ModifyRfBuffer(priv->Bank6Data,
261 ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL), 3, 194, 0);
263 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 5ghz: OB_5:%d, DB_5:%d\n",
265 ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL),
266 ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL));
267 ar5416ModifyRfBuffer(priv->Bank6Data,
268 ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL), 3, 203, 0);
269 ar5416ModifyRfBuffer(priv->Bank6Data,
270 ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL), 3, 200, 0);
272 /* Setup Bank 7 Setup */
273 ath_hal_ini_bank_setup(priv->Bank7Data, &AH5416(ah)->ah_ini_bank7, 1);
275 /* Write Analog registers */
276 writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank0,
278 writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank1,
279 priv->Bank1Data, writes);
280 writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank2,
281 priv->Bank2Data, writes);
282 writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank3,
283 priv->Bank3Data, writes);
284 writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6,
285 priv->Bank6Data, writes);
286 (void) ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank7,
287 priv->Bank7Data, writes);
294 * Read the transmit power levels from the structures taken from EEPROM
295 * Interpolate read transmit power values for this channel
296 * Organize the transmit power values into a table for writing into the hardware
300 ar2133SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
301 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
308 ar2133GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
311 int16_t minGain,minPwr,minPcdac,retVal;
313 /* Assume NUM_POINTS_XPD0 > 0 */
314 minGain = data->pDataPerXPD[0].xpd_gain;
315 for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
316 if (data->pDataPerXPD[i].xpd_gain < minGain) {
318 minGain = data->pDataPerXPD[i].xpd_gain;
321 minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
322 minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
323 for (i=1; i<NUM_POINTS_XPD0; i++) {
324 if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
325 minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
326 minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
329 retVal = minPwr - (minPcdac*2);
335 ar2133GetChannelMaxMinPower(struct ath_hal *ah,
336 const struct ieee80211_channel *chan,
337 int16_t *maxPow, int16_t *minPow)
340 struct ath_hal_5212 *ahp = AH5212(ah);
341 int numChannels=0,i,last;
342 int totalD, totalF,totalMin;
343 EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
344 EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
347 if (IS_CHAN_A(chan)) {
348 powerArray = ahp->ah_modePowerArray5112;
349 data = powerArray[headerInfo11A].pDataPerChannel;
350 numChannels = powerArray[headerInfo11A].numChannels;
351 } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
352 /* XXX - is this correct? Should we also use the same power for turbo G? */
353 powerArray = ahp->ah_modePowerArray5112;
354 data = powerArray[headerInfo11G].pDataPerChannel;
355 numChannels = powerArray[headerInfo11G].numChannels;
356 } else if (IS_CHAN_B(chan)) {
357 powerArray = ahp->ah_modePowerArray5112;
358 data = powerArray[headerInfo11B].pDataPerChannel;
359 numChannels = powerArray[headerInfo11B].numChannels;
363 /* Make sure the channel is in the range of the TP values
366 if ((numChannels < 1) ||
367 (chan->channel < data[0].channelValue) ||
368 (chan->channel > data[numChannels-1].channelValue))
371 /* Linearly interpolate the power value now */
373 (i<numChannels) && (chan->channel > data[i].channelValue);
375 totalD = data[i].channelValue - data[last].channelValue;
377 totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
378 *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
380 totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]);
381 *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD);
384 if (chan->channel == data[i].channelValue) {
385 *maxPow = data[i].maxPower_t4;
386 *minPow = ar2133GetMinPower(ah, &data[i]);
392 *maxPow = *minPow = 0;
398 * The ordering of nfarray is thus:
400 * nfarray[0]: Chain 0 ctl
401 * nfarray[1]: Chain 1 ctl
402 * nfarray[2]: Chain 2 ctl
403 * nfarray[3]: Chain 0 ext
404 * nfarray[4]: Chain 1 ext
405 * nfarray[5]: Chain 2 ext
408 ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
410 struct ath_hal_5416 *ahp = AH5416(ah);
414 * Blank nf array - some chips may only
415 * have one or two RX chainmasks enabled.
417 nfarray[0] = nfarray[1] = nfarray[2] = 0;
418 nfarray[3] = nfarray[4] = nfarray[5] = 0;
420 switch (ahp->ah_rx_chainmask) {
422 nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
424 nf = 0 - ((nf ^ 0x1ff) + 1);
425 HALDEBUG(ah, HAL_DEBUG_NFCAL,
426 "NF calibrated [ctl] [chain 2] is %d\n", nf);
429 nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
431 nf = 0 - ((nf ^ 0x1ff) + 1);
432 HALDEBUG(ah, HAL_DEBUG_NFCAL,
433 "NF calibrated [ext] [chain 2] is %d\n", nf);
438 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
440 nf = 0 - ((nf ^ 0x1ff) + 1);
441 HALDEBUG(ah, HAL_DEBUG_NFCAL,
442 "NF calibrated [ctl] [chain 1] is %d\n", nf);
446 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
448 nf = 0 - ((nf ^ 0x1ff) + 1);
449 HALDEBUG(ah, HAL_DEBUG_NFCAL,
450 "NF calibrated [ext] [chain 1] is %d\n", nf);
454 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
456 nf = 0 - ((nf ^ 0x1ff) + 1);
457 HALDEBUG(ah, HAL_DEBUG_NFCAL,
458 "NF calibrated [ctl] [chain 0] is %d\n", nf);
461 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
463 nf = 0 - ((nf ^ 0x1ff) + 1);
464 HALDEBUG(ah, HAL_DEBUG_NFCAL,
465 "NF calibrated [ext] [chain 0] is %d\n", nf);
473 * Adjust NF based on statistical values for 5GHz frequencies.
474 * Stubbed:Not used by Fowl
477 ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
483 * Free memory for analog bank scratch buffers
486 ar2133RfDetach(struct ath_hal *ah)
488 struct ath_hal_5212 *ahp = AH5212(ah);
490 HALASSERT(ahp->ah_rfHal != AH_NULL);
491 ath_hal_free(ahp->ah_rfHal);
492 ahp->ah_rfHal = AH_NULL;
496 * Allocate memory for analog bank scratch buffers
497 * Scratch Buffer will be reinitialized every reset so no need to zero now
500 ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status)
502 struct ath_hal_5212 *ahp = AH5212(ah);
503 struct ar2133State *priv;
506 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR2133 radio\n", __func__);
508 HALASSERT(ahp->ah_rfHal == AH_NULL);
509 priv = ath_hal_malloc(sizeof(struct ar2133State)
510 + AH5416(ah)->ah_ini_bank0.rows * sizeof(uint32_t)
511 + AH5416(ah)->ah_ini_bank1.rows * sizeof(uint32_t)
512 + AH5416(ah)->ah_ini_bank2.rows * sizeof(uint32_t)
513 + AH5416(ah)->ah_ini_bank3.rows * sizeof(uint32_t)
514 + AH5416(ah)->ah_ini_bank6.rows * sizeof(uint32_t)
515 + AH5416(ah)->ah_ini_bank7.rows * sizeof(uint32_t)
517 if (priv == AH_NULL) {
518 HALDEBUG(ah, HAL_DEBUG_ANY,
519 "%s: cannot allocate private state\n", __func__);
520 *status = HAL_ENOMEM; /* XXX */
523 priv->base.rfDetach = ar2133RfDetach;
524 priv->base.writeRegs = ar2133WriteRegs;
525 priv->base.getRfBank = ar2133GetRfBank;
526 priv->base.setChannel = ar2133SetChannel;
527 priv->base.setRfRegs = ar2133SetRfRegs;
528 priv->base.setPowerTable = ar2133SetPowerTable;
529 priv->base.getChannelMaxMinPower = ar2133GetChannelMaxMinPower;
530 priv->base.getNfAdjust = ar2133GetNfAdjust;
532 bankData = (uint32_t *) &priv[1];
533 priv->Bank0Data = bankData, bankData += AH5416(ah)->ah_ini_bank0.rows;
534 priv->Bank1Data = bankData, bankData += AH5416(ah)->ah_ini_bank1.rows;
535 priv->Bank2Data = bankData, bankData += AH5416(ah)->ah_ini_bank2.rows;
536 priv->Bank3Data = bankData, bankData += AH5416(ah)->ah_ini_bank3.rows;
537 priv->Bank6Data = bankData, bankData += AH5416(ah)->ah_ini_bank6.rows;
538 priv->Bank7Data = bankData, bankData += AH5416(ah)->ah_ini_bank7.rows;
540 ahp->ah_pcdacTable = priv->pcdacTable;
541 ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
542 ahp->ah_rfHal = &priv->base;
544 * Set noise floor adjust method; we arrange a
545 * direct call instead of thunking.
547 AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
548 AH_PRIVATE(ah)->ah_getNoiseFloor = ar2133GetNoiseFloor;