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54 #ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_
55 #define _SCIC_SDS_CONTROLLER_REGISTERS_H_
60 * @brief This file contains macros used to perform the register reads/writes
61 * to the SCU hardware.
68 #include <dev/isci/scil/scu_registers.h>
69 #include <dev/isci/scil/scic_sds_controller.h>
72 * @name SMU_REGISTER_ACCESS_MACROS
75 #define scic_sds_controller_smu_register_read(controller, reg) \
78 (controller)->smu_registers->reg \
81 #define scic_sds_controller_smu_register_write(controller, reg, value) \
84 (controller)->smu_registers->reg, \
90 * @name AFE_REGISTER_ACCESS_MACROS
93 #define scu_afe_register_write(controller, reg, value) \
96 (controller)->scu_registers->afe.reg, \
100 #define scu_afe_register_read(controller, reg) \
103 (controller)->scu_registers->afe.reg \
108 * @name SGPIO_PEG0_REGISTER_ACCESS_MACROS
111 #define scu_sgpio_peg0_register_read(controller, reg) \
114 (controller)->scu_registers->peg0.sgpio.reg \
117 #define scu_sgpio_peg0_register_write(controller, reg, value) \
118 scu_register_write( \
120 (controller)->scu_registers->peg0.sgpio.reg, \
126 * @name VIIT_REGISTER_ACCESS_MACROS
129 #define scu_controller_viit_register_write(controller, index, reg, value) \
130 scu_register_write( \
132 (controller)->scu_registers->peg0.viit[index].reg, \
138 * @name SCRATCH_RAM_REGISTER_ACCESS_MACROS
141 // Scratch RAM access may be needed before the scu_registers pointer
142 // has been initialized. So instead, explicitly cast BAR1 to a
143 // SCU_REGISTERS_T data structure.
145 // Scratch RAM is stored in the Zoning Permission Table for OROM use.
146 #define scu_controller_scratch_ram_register_write(controller, index, value) \
147 scu_register_write( \
149 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \
153 #define scu_controller_scratch_ram_register_read(controller, index) \
156 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \
159 #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \
160 scu_register_write( \
162 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \
166 #define scu_controller_scratch_ram_register_read_ext(controller, index) \
169 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \
174 //*****************************************************************************
176 //*****************************************************************************
179 * @name SMU_REGISTERS
182 #define SMU_PCP_WRITE(controller, value) \
183 scic_sds_controller_smu_register_write( \
184 controller, post_context_port, value \
187 #define SMU_TCR_READ(controller, value) \
188 scic_sds_controller_smu_register_read( \
189 controller, task_context_range \
192 #define SMU_TCR_WRITE(controller, value) \
193 scic_sds_controller_smu_register_write( \
194 controller, task_context_range, value \
197 #define SMU_HTTBAR_WRITE(controller, address) \
199 scic_sds_controller_smu_register_write( \
201 host_task_table_lower, \
202 sci_cb_physical_address_lower(address) \
204 scic_sds_controller_smu_register_write( \
206 host_task_table_upper, \
207 sci_cb_physical_address_upper(address) \
211 #define SMU_CQBAR_WRITE(controller, address) \
213 scic_sds_controller_smu_register_write( \
215 completion_queue_lower, \
216 sci_cb_physical_address_lower(address) \
218 scic_sds_controller_smu_register_write( \
220 completion_queue_upper, \
221 sci_cb_physical_address_upper(address) \
225 #define SMU_CQGR_WRITE(controller, value) \
226 scic_sds_controller_smu_register_write( \
227 controller, completion_queue_get, value \
230 #define SMU_CQGR_READ(controller, value) \
231 scic_sds_controller_smu_register_read( \
232 controller, completion_queue_get \
235 #define SMU_CQPR_WRITE(controller, value) \
236 scic_sds_controller_smu_register_write( \
237 controller, completion_queue_put, value \
240 #define SMU_RNCBAR_WRITE(controller, address) \
242 scic_sds_controller_smu_register_write( \
244 remote_node_context_lower, \
245 sci_cb_physical_address_lower(address) \
247 scic_sds_controller_smu_register_write( \
249 remote_node_context_upper, \
250 sci_cb_physical_address_upper(address) \
254 #define SMU_AMR_READ(controller) \
255 scic_sds_controller_smu_register_read( \
256 controller, address_modifier \
259 #define SMU_IMR_READ(controller) \
260 scic_sds_controller_smu_register_read( \
261 controller, interrupt_mask \
264 #define SMU_IMR_WRITE(controller, mask) \
265 scic_sds_controller_smu_register_write( \
266 controller, interrupt_mask, mask \
269 #define SMU_ISR_READ(controller) \
270 scic_sds_controller_smu_register_read( \
271 controller, interrupt_status \
274 #define SMU_ISR_WRITE(controller, status) \
275 scic_sds_controller_smu_register_write( \
276 controller, interrupt_status, status \
279 #define SMU_ICC_READ(controller) \
280 scic_sds_controller_smu_register_read( \
281 controller, interrupt_coalesce_control \
284 #define SMU_ICC_WRITE(controller, value) \
285 scic_sds_controller_smu_register_write( \
286 controller, interrupt_coalesce_control, value \
289 #define SMU_CQC_WRITE(controller, value) \
290 scic_sds_controller_smu_register_write( \
291 controller, completion_queue_control, value \
294 #define SMU_SMUSRCR_WRITE(controller, value) \
295 scic_sds_controller_smu_register_write( \
296 controller, soft_reset_control, value \
299 #define SMU_TCA_WRITE(controller, index, value) \
300 scic_sds_controller_smu_register_write( \
301 controller, task_context_assignment[index], value \
304 #define SMU_TCA_READ(controller, index) \
305 scic_sds_controller_smu_register_read( \
306 controller, task_context_assignment[index] \
309 #define SMU_DCC_READ(controller) \
310 scic_sds_controller_smu_register_read( \
311 controller, device_context_capacity \
314 #define SMU_DFC_READ(controller) \
315 scic_sds_controller_smu_register_read( \
316 controller, device_function_capacity \
319 #define SMU_SMUCSR_READ(controller) \
320 scic_sds_controller_smu_register_read( \
321 controller, control_status \
324 #define SMU_CGUCR_READ(controller) \
325 scic_sds_controller_smu_register_read( \
326 controller, clock_gating_control \
329 #define SMU_CGUCR_WRITE(controller, value) \
330 scic_sds_controller_smu_register_write( \
331 controller, clock_gating_control, value \
334 #define SMU_CQPR_READ(controller) \
335 scic_sds_controller_smu_register_read( \
336 controller, completion_queue_put \
342 * @name SCU_REGISTER_ACCESS_MACROS
345 #define scic_sds_controller_scu_register_read(controller, reg) \
348 (controller)->scu_registers->reg \
351 #define scic_sds_controller_scu_register_write(controller, reg, value) \
352 scu_register_write( \
354 (controller)->scu_registers->reg, \
360 //****************************************************************************
361 //* SCU SDMA REGISTERS
362 //****************************************************************************
365 * @name SCU_SDMA_REGISTER_ACCESS_MACROS
368 #define scu_sdma_register_read(controller, reg) \
371 (controller)->scu_registers->sdma.reg \
374 #define scu_sdma_register_write(controller, reg, value) \
375 scu_register_write( \
377 (controller)->scu_registers->sdma.reg, \
383 * @name SCU_SDMA_REGISTERS
386 #define SCU_PUFATHAR_WRITE(controller, address) \
388 scu_sdma_register_write( \
390 uf_address_table_lower, \
391 sci_cb_physical_address_lower(address) \
393 scu_sdma_register_write( \
395 uf_address_table_upper, \
396 sci_cb_physical_address_upper(address) \
400 #define SCU_UFHBAR_WRITE(controller, address) \
402 scu_sdma_register_write( \
404 uf_header_base_address_lower, \
405 sci_cb_physical_address_lower(address) \
407 scu_sdma_register_write( \
409 uf_header_base_address_upper, \
410 sci_cb_physical_address_upper(address) \
414 #define SCU_UFQC_READ(controller) \
415 scu_sdma_register_read( \
417 unsolicited_frame_queue_control \
420 #define SCU_UFQC_WRITE(controller, value) \
421 scu_sdma_register_write( \
423 unsolicited_frame_queue_control, \
427 #define SCU_UFQPP_READ(controller) \
428 scu_sdma_register_read( \
430 unsolicited_frame_put_pointer \
433 #define SCU_UFQPP_WRITE(controller, value) \
434 scu_sdma_register_write( \
436 unsolicited_frame_put_pointer, \
440 #define SCU_UFQGP_WRITE(controller, value) \
441 scu_sdma_register_write( \
443 unsolicited_frame_get_pointer, \
447 #define SCU_PDMACR_READ(controller) \
448 scu_sdma_register_read( \
453 #define SCU_PDMACR_WRITE(controller, value) \
454 scu_sdma_register_write( \
456 pdma_configuration, \
460 #define SCU_CDMACR_READ(controller) \
461 scu_sdma_register_read( \
466 #define SCU_CDMACR_WRITE(controller, value) \
467 scu_sdma_register_write( \
469 cdma_configuration, \
474 //*****************************************************************************
475 //* SCU CRAM AND FBRAM Registers
476 //*****************************************************************************
478 * @name SCU_CRAM_REGISTER_ACCESS_MACROS
481 #define scu_cram_register_read(controller, reg) \
484 (controller)->scu_registers->cram.reg \
487 #define scu_cram_register_write(controller, reg, value) \
488 scu_register_write( \
490 (controller)->scu_registers->cram.reg, \
496 * @name SCU_FBRAM_REGISTER_ACCESS_MACROS
499 #define scu_fbram_register_read(controller, reg) \
502 (controller)->scu_registers->fbram.reg \
505 #define scu_fbram_register_write(controller, reg, value) \
506 scu_register_write( \
508 (controller)->scu_registers->fbram.reg, \
515 * @name SCU_CRAM_REGISTERS
519 // SRAM ECC CONTROL REGISTER BITS
520 #define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001
521 #define MULTI_BIT_ERROR_REPORTING_ENABLE 0x00000002
522 #define SINGLE_BIT_ERROR_REPORTING_ENABLE 0x00000004
524 //SRAM ECC control register (SECR0)
525 #define SCU_SECR0_WRITE(controller, value) \
526 scu_cram_register_write( \
528 sram_ecc_control_0, \
534 * @name SCU_FBRAM_REGISTERS
538 //SRAM ECC control register (SECR1)
539 #define SCU_SECR1_WRITE(controller, value) \
540 scu_fbram_register_write( \
542 sram_ecc_control_1, \
548 //*****************************************************************************
549 //* SCU Port Task Scheduler Group Registers
550 //*****************************************************************************
553 * @name SCU_PTSG_REGISTER_ACCESS_MACROS
556 #define scu_ptsg_register_read(controller, reg) \
559 (controller)->scu_registers->peg0.ptsg.reg \
562 #define scu_ptsg_register_write(controller, reg, value) \
563 scu_register_write( \
565 (controller)->scu_registers->peg0.ptsg.reg, \
571 * @name SCU_PTSG_REGISTERS
574 #define SCU_PTSGCR_READ(controller) \
575 scu_ptsg_register_read( \
580 #define SCU_PTSGCR_WRITE(controller, value) \
581 scu_ptsg_register_write( \
587 #define SCU_PTSGRTC_READ(controller) \
588 scu_ptsg_register_read( \
596 #endif // __cplusplus
598 #endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_