2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/resource.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/stdarg.h>
49 #include <dev/mmc/bridge.h>
50 #include <dev/mmc/mmcreg.h>
51 #include <dev/mmc/mmcbrvar.h>
56 #define DMA_BLOCK_SIZE 4096
57 #define DMA_BOUNDARY 0 /* DMA reload every 4K */
59 /* Controller doesn't honor resets unless we touch the clock register */
60 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
61 /* Controller really supports DMA */
62 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
63 /* Controller has unusable DMA engine */
64 #define SDHCI_QUIRK_BROKEN_DMA (1<<2)
65 /* Controller doesn't like to be reset when there is no card inserted. */
66 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
67 /* Controller has flaky internal state so reset it on each ios change */
68 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
69 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
70 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
71 /* Controller needs to be reset after each request to stay stable */
72 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
73 /* Controller has an off-by-one issue with timeout value */
74 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
75 /* Controller has broken read timings */
76 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
77 /* Controller needs lowered frequency */
78 #define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9)
80 static const struct sdhci_device {
86 { 0x08221180, 0xffff, "RICOH R5C822 SD",
87 SDHCI_QUIRK_FORCE_DMA },
88 { 0xe8221180, 0xffff, "RICOH SD",
89 SDHCI_QUIRK_FORCE_DMA },
90 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
91 SDHCI_QUIRK_LOWER_FREQUENCY },
92 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
93 SDHCI_QUIRK_FORCE_DMA },
94 { 0x05501524, 0xffff, "ENE CB712 SD",
95 SDHCI_QUIRK_BROKEN_TIMINGS },
96 { 0x05511524, 0xffff, "ENE CB712 SD 2",
97 SDHCI_QUIRK_BROKEN_TIMINGS },
98 { 0x07501524, 0xffff, "ENE CB714 SD",
99 SDHCI_QUIRK_RESET_ON_IOS |
100 SDHCI_QUIRK_BROKEN_TIMINGS },
101 { 0x07511524, 0xffff, "ENE CB714 SD 2",
102 SDHCI_QUIRK_RESET_ON_IOS |
103 SDHCI_QUIRK_BROKEN_TIMINGS },
104 { 0x410111ab, 0xffff, "Marvell CaFe SD",
105 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
106 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
107 SDHCI_QUIRK_32BIT_DMA_SIZE |
108 SDHCI_QUIRK_RESET_AFTER_REQUEST },
116 struct sdhci_softc *sc;
117 device_t dev; /* Slot device */
118 u_char num; /* Slot number */
119 u_char opt; /* Slot options */
120 #define SDHCI_HAVE_DMA 1
121 uint32_t max_clk; /* Max possible freq */
122 uint32_t timeout_clk; /* Timeout freq */
123 struct resource *mem_res; /* Memory resource */
125 bus_dma_tag_t dmatag;
128 bus_addr_t paddr; /* DMA buffer address */
129 struct task card_task; /* Card presence check task */
130 struct callout card_callout; /* Card insert delay callout */
131 struct mmc_host host; /* Host parameters */
132 struct mmc_request *req; /* Current request */
133 struct mmc_command *curcmd; /* Current command of current request */
135 uint32_t intmask; /* Current interrupt mask */
136 uint32_t clock; /* Current clock freq. */
137 size_t offset; /* Data buffer offset */
138 uint8_t hostctrl; /* Current host control register */
139 u_char power; /* Current power */
140 u_char bus_busy; /* Bus busy status */
141 u_char cmd_done; /* CMD command part done flag */
142 u_char data_done; /* DAT command part done flag */
143 u_char flags; /* Request execution flags */
144 #define CMD_STARTED 1
145 #define STOP_STARTED 2
146 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */
147 struct mtx mtx; /* Slot mutex */
151 device_t dev; /* Controller device */
152 u_int quirks; /* Chip specific quirks */
153 struct resource *irq_res; /* IRQ resource */
155 void *intrhand; /* Interrupt handle */
157 int num_slots; /* Number of slots on this controller */
158 struct sdhci_slot slots[6];
161 static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
164 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
165 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
167 static inline uint8_t
168 RD1(struct sdhci_slot *slot, bus_size_t off)
170 bus_barrier(slot->mem_res, 0, 0xFF,
171 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
172 return bus_read_1(slot->mem_res, off);
176 WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val)
178 bus_barrier(slot->mem_res, 0, 0xFF,
179 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
180 bus_write_1(slot->mem_res, off, val);
183 static inline uint16_t
184 RD2(struct sdhci_slot *slot, bus_size_t off)
186 bus_barrier(slot->mem_res, 0, 0xFF,
187 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
188 return bus_read_2(slot->mem_res, off);
192 WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val)
194 bus_barrier(slot->mem_res, 0, 0xFF,
195 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
196 bus_write_2(slot->mem_res, off, val);
199 static inline uint32_t
200 RD4(struct sdhci_slot *slot, bus_size_t off)
202 bus_barrier(slot->mem_res, 0, 0xFF,
203 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
204 return bus_read_4(slot->mem_res, off);
208 WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val)
210 bus_barrier(slot->mem_res, 0, 0xFF,
211 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
212 bus_write_4(slot->mem_res, off, val);
215 /* bus entry points */
216 static int sdhci_probe(device_t dev);
217 static int sdhci_attach(device_t dev);
218 static int sdhci_detach(device_t dev);
219 static void sdhci_intr(void *);
221 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
222 static void sdhci_start(struct sdhci_slot *slot);
223 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
225 static void sdhci_card_task(void *, int);
227 /* helper routines */
228 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
229 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
230 #define SDHCI_LOCK_INIT(_slot) \
231 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
232 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
233 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
234 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
237 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
242 retval = printf("%s-slot%d: ",
243 device_get_nameunit(slot->sc->dev), slot->num);
246 retval += vprintf(fmt, ap);
252 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
255 printf("getaddr: error %d\n", error);
258 *(bus_addr_t *)arg = segs[0].ds_addr;
262 sdhci_dumpregs(struct sdhci_slot *slot)
265 "============== REGISTER DUMP ==============\n");
267 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
268 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
269 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
270 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
271 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
272 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
273 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
274 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
275 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
276 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
277 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
278 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
279 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
280 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
281 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
282 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
283 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
284 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
285 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
286 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
289 "===========================================\n");
293 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
298 if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
299 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
304 /* Some controllers need this kick or reset won't work. */
305 if ((mask & SDHCI_RESET_ALL) == 0 &&
306 (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
309 /* This is to force an update */
312 sdhci_set_clock(slot, clock);
315 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
317 if (mask & SDHCI_RESET_ALL) {
322 /* Wait max 100 ms */
324 /* Controller clears the bits when it's done */
325 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
328 "Reset 0x%x never completed - 0x%x.\n",
329 (int)mask, (int)res);
330 sdhci_dumpregs(slot);
339 sdhci_init(struct sdhci_slot *slot)
342 sdhci_reset(slot, SDHCI_RESET_ALL);
344 /* Enable interrupts. */
345 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
346 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
347 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
348 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
349 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
350 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
352 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
353 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
357 sdhci_lower_frequency(device_t dev)
360 /* Enable SD2.0 mode. */
361 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
362 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
363 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
366 * Some SD/MMC cards don't work with the default base
367 * clock frequency of 200MHz. Lower it to 50Hz.
369 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
370 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
371 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
375 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
381 if (clock == slot->clock)
385 /* Turn off the clock. */
386 WR2(slot, SDHCI_CLOCK_CONTROL, 0);
387 /* If no clock requested - left it so. */
390 /* Looking for highest freq <= clock. */
392 for (clk = 1; clk < 256; clk <<= 1) {
397 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
399 /* Now we have got divider, set it. */
400 clk <<= SDHCI_DIVIDER_SHIFT;
401 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
403 clk |= SDHCI_CLOCK_INT_EN;
404 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
405 /* Wait up to 10 ms until it stabilize. */
407 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
408 & SDHCI_CLOCK_INT_STABLE)) {
411 "Internal clock never stabilised.\n");
412 sdhci_dumpregs(slot);
418 /* Pass clock signal to the bus. */
419 clk |= SDHCI_CLOCK_CARD_EN;
420 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
424 sdhci_set_power(struct sdhci_slot *slot, u_char power)
428 if (slot->power == power)
432 /* Turn off the power. */
434 WR1(slot, SDHCI_POWER_CONTROL, pwr);
435 /* If power down requested - left it so. */
439 switch (1 << power) {
440 case MMC_OCR_LOW_VOLTAGE:
441 pwr |= SDHCI_POWER_180;
443 case MMC_OCR_290_300:
444 case MMC_OCR_300_310:
445 pwr |= SDHCI_POWER_300;
447 case MMC_OCR_320_330:
448 case MMC_OCR_330_340:
449 pwr |= SDHCI_POWER_330;
452 WR1(slot, SDHCI_POWER_CONTROL, pwr);
453 /* Turn on the power. */
454 pwr |= SDHCI_POWER_ON;
455 WR1(slot, SDHCI_POWER_CONTROL, pwr);
459 sdhci_read_block_pio(struct sdhci_slot *slot)
465 buffer = slot->curcmd->data->data;
466 buffer += slot->offset;
467 /* Transfer one block at a time. */
468 left = min(512, slot->curcmd->data->len - slot->offset);
469 slot->offset += left;
471 /* If we are too fast, broken controllers return zeroes. */
472 if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
474 /* Handle unalligned and alligned buffer cases. */
475 if ((intptr_t)buffer & 3) {
477 data = RD4(slot, SDHCI_BUFFER);
479 buffer[1] = (data >> 8);
480 buffer[2] = (data >> 16);
481 buffer[3] = (data >> 24);
486 bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
487 (uint32_t *)buffer, left >> 2);
490 /* Handle uneven size case. */
492 data = RD4(slot, SDHCI_BUFFER);
502 sdhci_write_block_pio(struct sdhci_slot *slot)
508 buffer = slot->curcmd->data->data;
509 buffer += slot->offset;
510 /* Transfer one block at a time. */
511 left = min(512, slot->curcmd->data->len - slot->offset);
512 slot->offset += left;
514 /* Handle unalligned and alligned buffer cases. */
515 if ((intptr_t)buffer & 3) {
523 WR4(slot, SDHCI_BUFFER, data);
526 bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
527 (uint32_t *)buffer, left >> 2);
530 /* Handle uneven size case. */
537 WR4(slot, SDHCI_BUFFER, data);
542 sdhci_transfer_pio(struct sdhci_slot *slot)
545 /* Read as many blocks as possible. */
546 if (slot->curcmd->data->flags & MMC_DATA_READ) {
547 while (RD4(slot, SDHCI_PRESENT_STATE) &
548 SDHCI_DATA_AVAILABLE) {
549 sdhci_read_block_pio(slot);
550 if (slot->offset >= slot->curcmd->data->len)
554 while (RD4(slot, SDHCI_PRESENT_STATE) &
555 SDHCI_SPACE_AVAILABLE) {
556 sdhci_write_block_pio(slot);
557 if (slot->offset >= slot->curcmd->data->len)
564 sdhci_card_delay(void *arg)
566 struct sdhci_slot *slot = arg;
568 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
572 sdhci_card_task(void *arg, int pending)
574 struct sdhci_slot *slot = arg;
577 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
578 if (slot->dev == NULL) {
579 /* If card is present - attach mmc bus. */
580 slot->dev = device_add_child(slot->sc->dev, "mmc", -1);
581 device_set_ivars(slot->dev, slot);
583 device_probe_and_attach(slot->dev);
587 if (slot->dev != NULL) {
588 /* If no card present - detach mmc bus. */
589 device_t d = slot->dev;
592 device_delete_child(slot->sc->dev, d);
599 sdhci_probe(device_t dev)
603 uint8_t class, subclass;
606 model = (uint32_t)pci_get_device(dev) << 16;
607 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
608 subvendor = pci_get_subvendor(dev);
609 class = pci_get_class(dev);
610 subclass = pci_get_subclass(dev);
613 for (i = 0; sdhci_devices[i].model != 0; i++) {
614 if (sdhci_devices[i].model == model &&
615 (sdhci_devices[i].subvendor == 0xffff ||
616 sdhci_devices[i].subvendor == subvendor)) {
617 device_set_desc(dev, sdhci_devices[i].desc);
618 result = BUS_PROBE_DEFAULT;
622 if (result == ENXIO && class == PCIC_BASEPERIPH &&
623 subclass == PCIS_BASEPERIPH_SDHC) {
624 device_set_desc(dev, "Generic SD HCI");
625 result = BUS_PROBE_GENERIC;
632 sdhci_attach(device_t dev)
634 struct sdhci_softc *sc = device_get_softc(dev);
637 uint8_t class, subclass, progif;
638 int err, slots, bar, i;
641 model = (uint32_t)pci_get_device(dev) << 16;
642 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
643 subvendor = pci_get_subvendor(dev);
644 class = pci_get_class(dev);
645 subclass = pci_get_subclass(dev);
646 progif = pci_get_progif(dev);
647 /* Apply chip specific quirks. */
648 for (i = 0; sdhci_devices[i].model != 0; i++) {
649 if (sdhci_devices[i].model == model &&
650 (sdhci_devices[i].subvendor == 0xffff ||
651 sdhci_devices[i].subvendor == subvendor)) {
652 sc->quirks = sdhci_devices[i].quirks;
656 /* Some controllers need to be bumped into the right mode. */
657 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
658 sdhci_lower_frequency(dev);
659 /* Read slots info from PCI registers. */
660 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
661 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
662 slots = PCI_SLOT_INFO_SLOTS(slots);
663 if (slots > 6 || bar > 5) {
664 device_printf(dev, "Incorrect slots information (%d, %d).\n",
670 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
671 RF_SHAREABLE | RF_ACTIVE);
672 if (sc->irq_res == NULL) {
673 device_printf(dev, "Can't allocate IRQ\n");
676 /* Scan all slots. */
677 for (i = 0; i < slots; i++) {
678 struct sdhci_slot *slot = &sc->slots[sc->num_slots];
681 SDHCI_LOCK_INIT(slot);
683 slot->num = sc->num_slots;
684 /* Allocate memory. */
685 slot->mem_rid = PCIR_BAR(bar + i);
686 slot->mem_res = bus_alloc_resource(dev,
687 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE);
688 if (slot->mem_res == NULL) {
689 device_printf(dev, "Can't allocate memory\n");
690 SDHCI_LOCK_DESTROY(slot);
693 /* Allocate DMA tag. */
694 err = bus_dma_tag_create(bus_get_dma_tag(dev),
695 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
696 BUS_SPACE_MAXADDR, NULL, NULL,
697 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
698 BUS_DMA_ALLOCNOW, NULL, NULL,
701 device_printf(dev, "Can't create DMA tag\n");
702 SDHCI_LOCK_DESTROY(slot);
705 /* Allocate DMA memory. */
706 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
707 BUS_DMA_NOWAIT, &slot->dmamap);
709 device_printf(dev, "Can't alloc DMA memory\n");
710 SDHCI_LOCK_DESTROY(slot);
713 /* Map the memory. */
714 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
715 (void *)slot->dmamem, DMA_BLOCK_SIZE,
716 sdhci_getaddr, &slot->paddr, 0);
717 if (err != 0 || slot->paddr == 0) {
718 device_printf(dev, "Can't load DMA memory\n");
719 SDHCI_LOCK_DESTROY(slot);
722 /* Initialize slot. */
724 caps = RD4(slot, SDHCI_CAPABILITIES);
725 /* Calculate base clock frequency. */
727 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
728 if (slot->max_clk == 0) {
729 device_printf(dev, "Hardware doesn't specify base clock "
732 slot->max_clk *= 1000000;
733 /* Calculate timeout clock frequency. */
735 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
736 if (slot->timeout_clk == 0) {
737 device_printf(dev, "Hardware doesn't specify timeout clock "
740 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
741 slot->timeout_clk *= 1000;
743 slot->host.f_min = slot->max_clk / 256;
744 slot->host.f_max = slot->max_clk;
745 slot->host.host_ocr = 0;
746 if (caps & SDHCI_CAN_VDD_330)
747 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
748 if (caps & SDHCI_CAN_VDD_300)
749 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
750 if (caps & SDHCI_CAN_VDD_180)
751 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
752 if (slot->host.host_ocr == 0) {
753 device_printf(dev, "Hardware doesn't report any "
754 "support voltages.\n");
756 slot->host.caps = MMC_CAP_4_BIT_DATA;
757 if (caps & SDHCI_CAN_DO_HISPD)
758 slot->host.caps |= MMC_CAP_HSPEED;
759 /* Decide if we have usable DMA. */
760 if (caps & SDHCI_CAN_DO_DMA)
761 slot->opt |= SDHCI_HAVE_DMA;
762 if (class == PCIC_BASEPERIPH &&
763 subclass == PCIS_BASEPERIPH_SDHC &&
764 progif != PCI_SDHCI_IFDMA)
765 slot->opt &= ~SDHCI_HAVE_DMA;
766 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA)
767 slot->opt &= ~SDHCI_HAVE_DMA;
768 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA)
769 slot->opt |= SDHCI_HAVE_DMA;
771 if (bootverbose || sdhci_debug) {
772 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
773 slot->max_clk / 1000000,
774 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
775 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
776 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
777 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
778 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
779 sdhci_dumpregs(slot);
782 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
783 callout_init(&slot->card_callout, 1);
786 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
787 /* Activate the interrupt */
788 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
789 NULL, sdhci_intr, sc, &sc->intrhand);
791 device_printf(dev, "Can't setup IRQ\n");
792 pci_enable_busmaster(dev);
793 /* Process cards detection. */
794 for (i = 0; i < sc->num_slots; i++) {
795 struct sdhci_slot *slot = &sc->slots[i];
797 sdhci_card_task(slot, 0);
804 sdhci_detach(device_t dev)
806 struct sdhci_softc *sc = device_get_softc(dev);
809 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
810 bus_release_resource(dev, SYS_RES_IRQ,
811 sc->irq_rid, sc->irq_res);
813 for (i = 0; i < sc->num_slots; i++) {
814 struct sdhci_slot *slot = &sc->slots[i];
817 callout_drain(&slot->card_callout);
818 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
825 device_delete_child(dev, d);
828 sdhci_reset(slot, SDHCI_RESET_ALL);
830 bus_dmamap_unload(slot->dmatag, slot->dmamap);
831 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
832 bus_dma_tag_destroy(slot->dmatag);
833 bus_release_resource(dev, SYS_RES_MEMORY,
834 slot->mem_rid, slot->mem_res);
835 SDHCI_LOCK_DESTROY(slot);
841 sdhci_suspend(device_t dev)
843 struct sdhci_softc *sc = device_get_softc(dev);
846 err = bus_generic_suspend(dev);
849 for (i = 0; i < sc->num_slots; i++)
850 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL);
855 sdhci_resume(device_t dev)
857 struct sdhci_softc *sc = device_get_softc(dev);
860 for (i = 0; i < sc->num_slots; i++)
861 sdhci_init(&sc->slots[i]);
862 return (bus_generic_resume(dev));
866 sdhci_update_ios(device_t brdev, device_t reqdev)
868 struct sdhci_slot *slot = device_get_ivars(reqdev);
869 struct mmc_ios *ios = &slot->host.ios;
872 /* Do full reset on bus power down to clear from any state. */
873 if (ios->power_mode == power_off) {
874 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
877 /* Configure the bus. */
878 sdhci_set_clock(slot, ios->clock);
879 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
880 if (ios->bus_width == bus_width_4)
881 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
883 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
884 if (ios->timing == bus_timing_hs)
885 slot->hostctrl |= SDHCI_CTRL_HISPD;
887 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
888 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
889 /* Some controllers like reset after bus changes. */
890 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS)
891 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
898 sdhci_set_transfer_mode(struct sdhci_slot *slot,
899 struct mmc_data *data)
906 mode = SDHCI_TRNS_BLK_CNT_EN;
908 mode |= SDHCI_TRNS_MULTI;
909 if (data->flags & MMC_DATA_READ)
910 mode |= SDHCI_TRNS_READ;
912 mode |= SDHCI_TRNS_ACMD12;
913 if (slot->flags & SDHCI_USE_DMA)
914 mode |= SDHCI_TRNS_DMA;
916 WR2(slot, SDHCI_TRANSFER_MODE, mode);
920 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
922 struct mmc_request *req = slot->req;
924 uint32_t mask, state;
929 cmd->error = MMC_ERR_NONE;
931 /* This flags combination is not supported by controller. */
932 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
933 slot_printf(slot, "Unsupported response type!\n");
934 cmd->error = MMC_ERR_FAILED;
941 /* Read controller present state. */
942 state = RD4(slot, SDHCI_PRESENT_STATE);
943 /* Do not issue command if there is no card, clock or power.
944 * Controller will not detect timeout without clock active. */
945 if ((state & SDHCI_CARD_PRESENT) == 0 ||
948 cmd->error = MMC_ERR_FAILED;
954 /* Always wait for free CMD bus. */
955 mask = SDHCI_CMD_INHIBIT;
956 /* Wait for free DAT if we have data or busy signal. */
957 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
958 mask |= SDHCI_DAT_INHIBIT;
959 /* We shouldn't wait for DAT for stop commands. */
960 if (cmd == slot->req->stop)
961 mask &= ~SDHCI_DAT_INHIBIT;
962 /* Wait for bus no more then 10 ms. */
964 while (state & mask) {
966 slot_printf(slot, "Controller never released "
967 "inhibit bit(s).\n");
968 sdhci_dumpregs(slot);
969 cmd->error = MMC_ERR_FAILED;
977 state = RD4(slot, SDHCI_PRESENT_STATE);
980 /* Prepare command flags. */
981 if (!(cmd->flags & MMC_RSP_PRESENT))
982 flags = SDHCI_CMD_RESP_NONE;
983 else if (cmd->flags & MMC_RSP_136)
984 flags = SDHCI_CMD_RESP_LONG;
985 else if (cmd->flags & MMC_RSP_BUSY)
986 flags = SDHCI_CMD_RESP_SHORT_BUSY;
988 flags = SDHCI_CMD_RESP_SHORT;
989 if (cmd->flags & MMC_RSP_CRC)
990 flags |= SDHCI_CMD_CRC;
991 if (cmd->flags & MMC_RSP_OPCODE)
992 flags |= SDHCI_CMD_INDEX;
994 flags |= SDHCI_CMD_DATA;
995 if (cmd->opcode == MMC_STOP_TRANSMISSION)
996 flags |= SDHCI_CMD_TYPE_ABORT;
998 sdhci_start_data(slot, cmd->data);
1000 * Interrupt aggregation: To reduce total number of interrupts
1001 * group response interrupt with data interrupt when possible.
1002 * If there going to be data interrupt, mask response one.
1004 if (slot->data_done == 0) {
1005 WR4(slot, SDHCI_SIGNAL_ENABLE,
1006 slot->intmask &= ~SDHCI_INT_RESPONSE);
1008 /* Set command argument. */
1009 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1010 /* Set data transfer mode. */
1011 sdhci_set_transfer_mode(slot, cmd->data);
1012 /* Set command flags. */
1013 WR1(slot, SDHCI_COMMAND_FLAGS, flags);
1014 /* Start command. */
1015 WR1(slot, SDHCI_COMMAND, cmd->opcode);
1019 sdhci_finish_command(struct sdhci_slot *slot)
1024 /* Interrupt aggregation: Restore command interrupt.
1025 * Main restore point for the case when command interrupt
1026 * happened first. */
1027 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
1028 /* In case of error - reset host and return. */
1029 if (slot->curcmd->error) {
1030 sdhci_reset(slot, SDHCI_RESET_CMD);
1031 sdhci_reset(slot, SDHCI_RESET_DATA);
1035 /* If command has response - fetch it. */
1036 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1037 if (slot->curcmd->flags & MMC_RSP_136) {
1038 /* CRC is stripped so we need one byte shift. */
1040 for (i = 0; i < 4; i++) {
1041 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
1042 slot->curcmd->resp[3 - i] = (val << 8) + extra;
1046 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1048 /* If data ready - finish. */
1049 if (slot->data_done)
1054 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1056 uint32_t target_timeout, current_timeout;
1059 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1060 slot->data_done = 1;
1064 slot->data_done = 0;
1066 /* Calculate and set data timeout.*/
1067 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1068 target_timeout = 1000000;
1070 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1071 while (current_timeout < target_timeout) {
1073 current_timeout <<= 1;
1077 /* Compensate for an off-by-one error in the CaFe chip.*/
1078 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
1081 slot_printf(slot, "Timeout too large!\n");
1084 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1089 /* Use DMA if possible. */
1090 if ((slot->opt & SDHCI_HAVE_DMA))
1091 slot->flags |= SDHCI_USE_DMA;
1092 /* If data is small, broken DMA may return zeroes instead of data, */
1093 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1095 slot->flags &= ~SDHCI_USE_DMA;
1096 /* Some controllers require even block sizes. */
1097 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1098 ((data->len) & 0x3))
1099 slot->flags &= ~SDHCI_USE_DMA;
1100 /* Load DMA buffer. */
1101 if (slot->flags & SDHCI_USE_DMA) {
1102 if (data->flags & MMC_DATA_READ)
1103 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD);
1105 memcpy(slot->dmamem, data->data,
1106 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE);
1107 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE);
1109 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1110 /* Interrupt aggregation: Mask border interrupt
1111 * for the last page and unmask else. */
1112 if (data->len == DMA_BLOCK_SIZE)
1113 slot->intmask &= ~SDHCI_INT_DMA_END;
1115 slot->intmask |= SDHCI_INT_DMA_END;
1116 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1118 /* Current data offset for both PIO and DMA. */
1120 /* Set block size and request IRQ on 4K border. */
1121 WR2(slot, SDHCI_BLOCK_SIZE,
1122 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
1123 /* Set block count. */
1124 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1128 sdhci_finish_data(struct sdhci_slot *slot)
1130 struct mmc_data *data = slot->curcmd->data;
1132 slot->data_done = 1;
1133 /* Interrupt aggregation: Restore command interrupt.
1134 * Auxillary restore point for the case when data interrupt
1135 * happened first. */
1136 if (!slot->cmd_done) {
1137 WR4(slot, SDHCI_SIGNAL_ENABLE,
1138 slot->intmask |= SDHCI_INT_RESPONSE);
1140 /* Unload rest of data from DMA buffer. */
1141 if (slot->flags & SDHCI_USE_DMA) {
1142 if (data->flags & MMC_DATA_READ) {
1143 size_t left = data->len - slot->offset;
1144 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD);
1145 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1146 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1148 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE);
1150 /* If there was error - reset the host. */
1151 if (slot->curcmd->error) {
1152 sdhci_reset(slot, SDHCI_RESET_CMD);
1153 sdhci_reset(slot, SDHCI_RESET_DATA);
1157 /* If we already have command response - finish. */
1163 sdhci_start(struct sdhci_slot *slot)
1165 struct mmc_request *req;
1171 if (!(slot->flags & CMD_STARTED)) {
1172 slot->flags |= CMD_STARTED;
1173 sdhci_start_command(slot, req->cmd);
1176 /* We don't need this until using Auto-CMD12 feature
1177 if (!(slot->flags & STOP_STARTED) && req->stop) {
1178 slot->flags |= STOP_STARTED;
1179 sdhci_start_command(slot, req->stop);
1183 if (sdhci_debug > 1)
1184 slot_printf(slot, "result: %d\n", req->cmd->error);
1185 if (!req->cmd->error &&
1186 (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1187 sdhci_reset(slot, SDHCI_RESET_CMD);
1188 sdhci_reset(slot, SDHCI_RESET_DATA);
1191 /* We must be done -- bad idea to do this while locked? */
1193 slot->curcmd = NULL;
1198 sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1200 struct sdhci_slot *slot = device_get_ivars(reqdev);
1203 if (slot->req != NULL) {
1207 if (sdhci_debug > 1) {
1208 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1209 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1210 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1211 (req->cmd->data)?req->cmd->data->flags:0);
1218 while (slot->req != NULL) {
1219 sdhci_intr(slot->sc);
1227 sdhci_get_ro(device_t brdev, device_t reqdev)
1229 struct sdhci_slot *slot = device_get_ivars(reqdev);
1233 val = RD4(slot, SDHCI_PRESENT_STATE);
1235 return (!(val & SDHCI_WRITE_PROTECT));
1239 sdhci_acquire_host(device_t brdev, device_t reqdev)
1241 struct sdhci_slot *slot = device_get_ivars(reqdev);
1245 while (slot->bus_busy)
1246 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1249 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1255 sdhci_release_host(device_t brdev, device_t reqdev)
1257 struct sdhci_slot *slot = device_get_ivars(reqdev);
1260 /* Deactivate led. */
1261 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1269 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1272 if (!slot->curcmd) {
1273 slot_printf(slot, "Got command interrupt 0x%08x, but "
1274 "there is no active command.\n", intmask);
1275 sdhci_dumpregs(slot);
1278 if (intmask & SDHCI_INT_TIMEOUT)
1279 slot->curcmd->error = MMC_ERR_TIMEOUT;
1280 else if (intmask & SDHCI_INT_CRC)
1281 slot->curcmd->error = MMC_ERR_BADCRC;
1282 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1283 slot->curcmd->error = MMC_ERR_FIFO;
1285 sdhci_finish_command(slot);
1289 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1292 if (!slot->curcmd) {
1293 slot_printf(slot, "Got data interrupt 0x%08x, but "
1294 "there is no active command.\n", intmask);
1295 sdhci_dumpregs(slot);
1298 if (slot->curcmd->data == NULL &&
1299 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1300 slot_printf(slot, "Got data interrupt 0x%08x, but "
1301 "there is no active data operation.\n",
1303 sdhci_dumpregs(slot);
1306 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1307 slot->curcmd->error = MMC_ERR_TIMEOUT;
1308 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1309 slot->curcmd->error = MMC_ERR_BADCRC;
1310 if (slot->curcmd->data == NULL &&
1311 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1312 SDHCI_INT_DMA_END))) {
1313 slot_printf(slot, "Got data interrupt 0x%08x, but "
1314 "there is busy-only command.\n", intmask);
1315 sdhci_dumpregs(slot);
1316 slot->curcmd->error = MMC_ERR_INVALID;
1318 if (slot->curcmd->error) {
1319 /* No need to continue after any error. */
1320 sdhci_finish_data(slot);
1324 /* Handle PIO interrupt. */
1325 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1326 sdhci_transfer_pio(slot);
1327 /* Handle DMA border. */
1328 if (intmask & SDHCI_INT_DMA_END) {
1329 struct mmc_data *data = slot->curcmd->data;
1332 /* Unload DMA buffer... */
1333 left = data->len - slot->offset;
1334 if (data->flags & MMC_DATA_READ) {
1335 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1336 BUS_DMASYNC_POSTREAD);
1337 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1338 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1340 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1341 BUS_DMASYNC_POSTWRITE);
1343 /* ... and reload it again. */
1344 slot->offset += DMA_BLOCK_SIZE;
1345 left = data->len - slot->offset;
1346 if (data->flags & MMC_DATA_READ) {
1347 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1348 BUS_DMASYNC_PREREAD);
1350 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1351 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1352 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1353 BUS_DMASYNC_PREWRITE);
1355 /* Interrupt aggregation: Mask border interrupt
1356 * for the last page. */
1357 if (left == DMA_BLOCK_SIZE) {
1358 slot->intmask &= ~SDHCI_INT_DMA_END;
1359 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1362 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1364 /* We have got all data. */
1365 if (intmask & SDHCI_INT_DATA_END)
1366 sdhci_finish_data(slot);
1370 sdhci_acmd_irq(struct sdhci_slot *slot)
1374 err = RD4(slot, SDHCI_ACMD12_ERR);
1375 if (!slot->curcmd) {
1376 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1377 "there is no active command.\n", err);
1378 sdhci_dumpregs(slot);
1381 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1382 sdhci_reset(slot, SDHCI_RESET_CMD);
1386 sdhci_intr(void *arg)
1388 struct sdhci_softc *sc = (struct sdhci_softc *)arg;
1391 for (i = 0; i < sc->num_slots; i++) {
1392 struct sdhci_slot *slot = &sc->slots[i];
1396 /* Read slot interrupt status. */
1397 intmask = RD4(slot, SDHCI_INT_STATUS);
1398 if (intmask == 0 || intmask == 0xffffffff) {
1402 if (sdhci_debug > 2)
1403 slot_printf(slot, "Interrupt %#x\n", intmask);
1405 /* Handle card presence interrupts. */
1406 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1407 WR4(slot, SDHCI_INT_STATUS, intmask &
1408 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1410 if (intmask & SDHCI_INT_CARD_REMOVE) {
1411 if (bootverbose || sdhci_debug)
1412 slot_printf(slot, "Card removed\n");
1413 callout_stop(&slot->card_callout);
1414 taskqueue_enqueue(taskqueue_swi_giant,
1417 if (intmask & SDHCI_INT_CARD_INSERT) {
1418 if (bootverbose || sdhci_debug)
1419 slot_printf(slot, "Card inserted\n");
1420 callout_reset(&slot->card_callout, hz / 2,
1421 sdhci_card_delay, slot);
1423 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1425 /* Handle command interrupts. */
1426 if (intmask & SDHCI_INT_CMD_MASK) {
1427 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1428 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1430 /* Handle data interrupts. */
1431 if (intmask & SDHCI_INT_DATA_MASK) {
1432 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1433 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1435 /* Handle AutoCMD12 error interrupt. */
1436 if (intmask & SDHCI_INT_ACMD12ERR) {
1437 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1438 sdhci_acmd_irq(slot);
1440 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1441 intmask &= ~SDHCI_INT_ACMD12ERR;
1442 intmask &= ~SDHCI_INT_ERROR;
1443 /* Handle bus power interrupt. */
1444 if (intmask & SDHCI_INT_BUS_POWER) {
1445 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1447 "Card is consuming too much power!\n");
1448 intmask &= ~SDHCI_INT_BUS_POWER;
1450 /* The rest is unknown. */
1452 WR4(slot, SDHCI_INT_STATUS, intmask);
1453 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1455 sdhci_dumpregs(slot);
1463 sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1465 struct sdhci_slot *slot = device_get_ivars(child);
1470 case MMCBR_IVAR_BUS_MODE:
1471 *result = slot->host.ios.bus_mode;
1473 case MMCBR_IVAR_BUS_WIDTH:
1474 *result = slot->host.ios.bus_width;
1476 case MMCBR_IVAR_CHIP_SELECT:
1477 *result = slot->host.ios.chip_select;
1479 case MMCBR_IVAR_CLOCK:
1480 *result = slot->host.ios.clock;
1482 case MMCBR_IVAR_F_MIN:
1483 *result = slot->host.f_min;
1485 case MMCBR_IVAR_F_MAX:
1486 *result = slot->host.f_max;
1488 case MMCBR_IVAR_HOST_OCR:
1489 *result = slot->host.host_ocr;
1491 case MMCBR_IVAR_MODE:
1492 *result = slot->host.mode;
1494 case MMCBR_IVAR_OCR:
1495 *result = slot->host.ocr;
1497 case MMCBR_IVAR_POWER_MODE:
1498 *result = slot->host.ios.power_mode;
1500 case MMCBR_IVAR_VDD:
1501 *result = slot->host.ios.vdd;
1503 case MMCBR_IVAR_CAPS:
1504 *result = slot->host.caps;
1506 case MMCBR_IVAR_TIMING:
1507 *result = slot->host.ios.timing;
1509 case MMCBR_IVAR_MAX_DATA:
1517 sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1519 struct sdhci_slot *slot = device_get_ivars(child);
1524 case MMCBR_IVAR_BUS_MODE:
1525 slot->host.ios.bus_mode = value;
1527 case MMCBR_IVAR_BUS_WIDTH:
1528 slot->host.ios.bus_width = value;
1530 case MMCBR_IVAR_CHIP_SELECT:
1531 slot->host.ios.chip_select = value;
1533 case MMCBR_IVAR_CLOCK:
1535 uint32_t clock = slot->max_clk;
1538 for (i = 0; i < 8; i++) {
1543 slot->host.ios.clock = clock;
1545 slot->host.ios.clock = 0;
1547 case MMCBR_IVAR_MODE:
1548 slot->host.mode = value;
1550 case MMCBR_IVAR_OCR:
1551 slot->host.ocr = value;
1553 case MMCBR_IVAR_POWER_MODE:
1554 slot->host.ios.power_mode = value;
1556 case MMCBR_IVAR_VDD:
1557 slot->host.ios.vdd = value;
1559 case MMCBR_IVAR_TIMING:
1560 slot->host.ios.timing = value;
1562 case MMCBR_IVAR_CAPS:
1563 case MMCBR_IVAR_HOST_OCR:
1564 case MMCBR_IVAR_F_MIN:
1565 case MMCBR_IVAR_F_MAX:
1566 case MMCBR_IVAR_MAX_DATA:
1572 static device_method_t sdhci_methods[] = {
1574 DEVMETHOD(device_probe, sdhci_probe),
1575 DEVMETHOD(device_attach, sdhci_attach),
1576 DEVMETHOD(device_detach, sdhci_detach),
1577 DEVMETHOD(device_suspend, sdhci_suspend),
1578 DEVMETHOD(device_resume, sdhci_resume),
1581 DEVMETHOD(bus_read_ivar, sdhci_read_ivar),
1582 DEVMETHOD(bus_write_ivar, sdhci_write_ivar),
1585 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios),
1586 DEVMETHOD(mmcbr_request, sdhci_request),
1587 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro),
1588 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host),
1589 DEVMETHOD(mmcbr_release_host, sdhci_release_host),
1594 static driver_t sdhci_driver = {
1597 sizeof(struct sdhci_softc),
1599 static devclass_t sdhci_devclass;
1602 DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0);