2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef _SYS_EFX_IMPL_H
29 #define _SYS_EFX_IMPL_H
36 #include "falcon_impl.h"
37 #endif /* EFSYS_OPT_FALCON */
40 #include "siena_impl.h"
41 #endif /* EFSYS_OPT_SIENA */
47 #define EFX_MOD_MCDI 0x00000001
48 #define EFX_MOD_PROBE 0x00000002
49 #define EFX_MOD_NVRAM 0x00000004
50 #define EFX_MOD_VPD 0x00000008
51 #define EFX_MOD_NIC 0x00000010
52 #define EFX_MOD_INTR 0x00000020
53 #define EFX_MOD_EV 0x00000040
54 #define EFX_MOD_RX 0x00000080
55 #define EFX_MOD_TX 0x00000100
56 #define EFX_MOD_PORT 0x00000200
57 #define EFX_MOD_MON 0x00000400
58 #define EFX_MOD_WOL 0x00000800
59 #define EFX_MOD_FILTER 0x00001000
61 #define EFX_RESET_MAC 0x00000001
62 #define EFX_RESET_PHY 0x00000002
64 typedef enum efx_mac_type_e {
72 typedef struct efx_mac_ops_s {
73 int (*emo_reset)(efx_nic_t *); /* optional */
74 int (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
75 int (*emo_up)(efx_nic_t *, boolean_t *);
76 int (*emo_reconfigure)(efx_nic_t *);
77 #if EFSYS_OPT_LOOPBACK
78 int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
80 #endif /* EFSYS_OPT_LOOPBACK */
81 #if EFSYS_OPT_MAC_STATS
82 int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
83 int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
85 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
86 efsys_stat_t *, uint32_t *);
87 #endif /* EFSYS_OPT_MAC_STATS */
90 typedef struct efx_phy_ops_s {
91 int (*epo_power)(efx_nic_t *, boolean_t); /* optional */
92 int (*epo_reset)(efx_nic_t *);
93 int (*epo_reconfigure)(efx_nic_t *);
94 int (*epo_verify)(efx_nic_t *);
95 int (*epo_uplink_check)(efx_nic_t *,
96 boolean_t *); /* optional */
97 int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
98 unsigned int *, uint32_t *);
99 int (*epo_oui_get)(efx_nic_t *, uint32_t *);
100 #if EFSYS_OPT_PHY_STATS
101 int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
103 #endif /* EFSYS_OPT_PHY_STATS */
104 #if EFSYS_OPT_PHY_PROPS
106 const char __cs *(*epo_prop_name)(efx_nic_t *, unsigned int);
107 #endif /* EFSYS_OPT_PHY_PROPS */
108 int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
110 int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
111 #endif /* EFSYS_OPT_PHY_PROPS */
112 #if EFSYS_OPT_PHY_BIST
113 int (*epo_bist_start)(efx_nic_t *, efx_phy_bist_type_t);
114 int (*epo_bist_poll)(efx_nic_t *, efx_phy_bist_type_t,
115 efx_phy_bist_result_t *, uint32_t *,
116 unsigned long *, size_t);
117 void (*epo_bist_stop)(efx_nic_t *, efx_phy_bist_type_t);
118 #endif /* EFSYS_OPT_PHY_BIST */
121 typedef struct efx_port_s {
122 efx_mac_type_t ep_mac_type;
123 uint32_t ep_phy_type;
126 uint8_t ep_mac_addr[6];
127 efx_link_mode_t ep_link_mode;
130 unsigned int ep_fcntl;
131 boolean_t ep_fcntl_autoneg;
132 efx_oword_t ep_multicst_hash[2];
133 #if EFSYS_OPT_LOOPBACK
134 efx_loopback_type_t ep_loopback_type;
135 efx_link_mode_t ep_loopback_link_mode;
136 #endif /* EFSYS_OPT_LOOPBACK */
137 #if EFSYS_OPT_PHY_FLAGS
138 uint32_t ep_phy_flags;
139 #endif /* EFSYS_OPT_PHY_FLAGS */
140 #if EFSYS_OPT_PHY_LED_CONTROL
141 efx_phy_led_mode_t ep_phy_led_mode;
142 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
143 efx_phy_media_type_t ep_fixed_port_type;
144 efx_phy_media_type_t ep_module_type;
145 uint32_t ep_adv_cap_mask;
146 uint32_t ep_lp_cap_mask;
147 uint32_t ep_default_adv_cap_mask;
148 uint32_t ep_phy_cap_mask;
149 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
152 unsigned int bug10934_count;
155 unsigned int bug17190_count;
159 boolean_t ep_mac_poll_needed; /* falcon only */
160 boolean_t ep_mac_up; /* falcon only */
161 uint32_t ep_fwver; /* falcon only */
162 boolean_t ep_mac_drain;
163 boolean_t ep_mac_stats_pending;
164 #if EFSYS_OPT_PHY_BIST
165 efx_phy_bist_type_t ep_current_bist;
167 efx_mac_ops_t *ep_emop;
168 efx_phy_ops_t *ep_epop;
171 typedef struct efx_mon_ops_s {
172 int (*emo_reset)(efx_nic_t *);
173 int (*emo_reconfigure)(efx_nic_t *);
174 #if EFSYS_OPT_MON_STATS
175 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
176 efx_mon_stat_value_t *);
177 #endif /* EFSYS_OPT_MON_STATS */
180 typedef struct efx_mon_s {
181 efx_mon_type_t em_type;
182 efx_mon_ops_t *em_emop;
185 typedef struct efx_intr_s {
186 efx_intr_type_t ei_type;
187 efsys_mem_t *ei_esmp;
188 unsigned int ei_level;
191 typedef struct efx_nic_ops_s {
192 int (*eno_probe)(efx_nic_t *);
193 int (*eno_reset)(efx_nic_t *);
194 int (*eno_init)(efx_nic_t *);
196 int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
197 int (*eno_register_test)(efx_nic_t *);
198 #endif /* EFSYS_OPT_DIAG */
199 void (*eno_fini)(efx_nic_t *);
200 void (*eno_unprobe)(efx_nic_t *);
203 #define EFX_TXQ_LIMIT_TARGET 259
204 #define EFX_RXQ_LIMIT_TARGET 768
208 typedef enum efx_filter_type_e {
209 EFX_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
210 EFX_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
211 EFX_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
212 EFX_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
215 EFX_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
216 EFX_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
218 EFX_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
219 EFX_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
220 EFX_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
221 EFX_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
223 EFX_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
224 EFX_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
225 #endif /* EFSYS_OPT_SIENA */
230 typedef enum efx_filter_tbl_id_e {
231 EFX_FILTER_TBL_RX_IP = 0,
232 EFX_FILTER_TBL_RX_MAC,
233 EFX_FILTER_TBL_TX_IP,
234 EFX_FILTER_TBL_TX_MAC,
236 } efx_filter_tbl_id_t;
238 typedef struct efx_filter_tbl_s {
239 int eft_size; /* number of entries */
240 int eft_used; /* active count */
241 uint32_t *eft_bitmap; /* active bitmap */
242 efx_filter_spec_t *eft_spec; /* array of saved specs */
245 typedef struct efx_filter_s {
246 efx_filter_tbl_t ef_tbl[EFX_FILTER_NTBLS];
247 unsigned int ef_depth[EFX_FILTER_NTYPES];
251 extern __checkReturn int
252 efx_filter_insert_filter(
254 __in efx_filter_spec_t *spec,
255 __in boolean_t replace);
257 extern __checkReturn int
258 efx_filter_remove_filter(
260 __in efx_filter_spec_t *spec);
263 efx_filter_remove_index(
264 __inout efx_nic_t *enp,
265 __in efx_filter_type_t type,
266 __in int filter_idx);
269 efx_filter_redirect_index(
270 __inout efx_nic_t *enp,
271 __in efx_filter_type_t type,
272 __in int filter_index,
275 extern __checkReturn int
276 efx_filter_clear_tbl(
278 __in efx_filter_tbl_id_t tbl);
280 #endif /* EFSYS_OPT_FILTER */
283 typedef struct efx_nvram_ops_s {
285 int (*envo_test)(efx_nic_t *);
286 #endif /* EFSYS_OPT_DIAG */
287 int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
288 int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
289 uint32_t *, uint16_t *);
290 int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
291 int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
292 unsigned int, caddr_t, size_t);
293 int (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
294 int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
295 unsigned int, caddr_t, size_t);
296 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
297 int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *);
300 #endif /* EFSYS_OPT_NVRAM */
303 typedef struct efx_vpd_ops_s {
304 int (*evpdo_init)(efx_nic_t *);
305 int (*evpdo_size)(efx_nic_t *, size_t *);
306 int (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
307 int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
308 int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
309 int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
310 int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
311 int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *,
313 int (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
314 void (*evpdo_fini)(efx_nic_t *);
316 #endif /* EFSYS_OPT_VPD */
320 efx_family_t en_family;
321 uint32_t en_features;
322 efsys_identifier_t *en_esip;
323 efsys_lock_t *en_eslp;
324 efsys_bar_t *en_esbp;
325 unsigned int en_mod_flags;
326 unsigned int en_reset_flags;
327 efx_nic_cfg_t en_nic_cfg;
331 uint32_t en_ev_qcount;
332 uint32_t en_rx_qcount;
333 uint32_t en_tx_qcount;
334 efx_nic_ops_t *en_enop;
336 efx_filter_t en_filter;
337 #endif /* EFSYS_OPT_FILTER */
339 efx_nvram_type_t en_nvram_locked;
340 efx_nvram_ops_t *en_envop;
341 #endif /* EFSYS_OPT_NVRAM */
343 efx_vpd_ops_t *en_evpdop;
344 #endif /* EFSYS_OPT_VPD */
348 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
349 falcon_i2c_t enu_fip;
350 boolean_t enu_i2c_locked;
351 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
352 const uint8_t *enu_forced_cfg;
353 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
354 uint8_t enu_mon_devid;
355 #if EFSYS_OPT_PCIE_TUNE
356 unsigned int enu_nlanes;
357 #endif /* EFSYS_OPT_PCIE_TUNE */
358 uint16_t enu_board_rev;
359 boolean_t enu_internal_sram;
360 uint8_t enu_sram_num_bank;
361 uint8_t enu_sram_bank_size;
363 #endif /* EFSYS_OPT_FALCON */
367 efx_mcdi_iface_t enu_mip;
368 #endif /* EFSYS_OPT_MCDI */
369 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
370 unsigned int enu_partn_mask;
371 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
374 size_t enu_svpd_length;
375 #endif /* EFSYS_OPT_VPD */
377 #endif /* EFSYS_OPT_SIENA */
382 #define EFX_NIC_MAGIC 0x02121996
384 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
385 const efx_ev_callbacks_t *, void *);
390 unsigned int ee_index;
391 unsigned int ee_mask;
392 efsys_mem_t *ee_esmp;
394 uint32_t ee_stat[EV_NQSTATS];
395 #endif /* EFSYS_OPT_QSTATS */
396 efx_ev_handler_t ee_handler[1 << FSF_AZ_EV_CODE_WIDTH];
399 #define EFX_EVQ_MAGIC 0x08081997
401 #define EFX_EV_TIMER_QUANTUM 5
406 unsigned int er_index;
407 unsigned int er_mask;
408 efsys_mem_t *er_esmp;
411 #define EFX_RXQ_MAGIC 0x15022005
416 unsigned int et_index;
417 unsigned int et_mask;
418 efsys_mem_t *et_esmp;
420 uint32_t et_stat[TX_NQSTATS];
421 #endif /* EFSYS_OPT_QSTATS */
424 #define EFX_TXQ_MAGIC 0x05092005
426 #define EFX_MAC_ADDR_COPY(_dst, _src) \
428 (_dst)[0] = (_src)[0]; \
429 (_dst)[1] = (_src)[1]; \
430 (_dst)[2] = (_src)[2]; \
431 (_dst)[3] = (_src)[3]; \
432 (_dst)[4] = (_src)[4]; \
433 (_dst)[5] = (_src)[5]; \
434 _NOTE(CONSTANTCONDITION) \
437 #if EFSYS_OPT_CHECK_REG
438 #define EFX_CHECK_REG(_enp, _reg) \
440 const char __cs *name = #_reg; \
441 char min = name[4]; \
442 char max = name[5]; \
445 switch ((_enp)->en_family) { \
446 case EFX_FAMILY_FALCON: \
450 case EFX_FAMILY_SIENA: \
459 EFSYS_ASSERT3S(rev, >=, min); \
460 EFSYS_ASSERT3S(rev, <=, max); \
462 _NOTE(CONSTANTCONDITION) \
465 #define EFX_CHECK_REG(_enp, _reg) do { \
466 _NOTE(CONSTANTCONDITION) \
470 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
472 EFX_CHECK_REG((_enp), (_reg)); \
473 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
475 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
476 uint32_t, _reg ## _OFST, \
477 uint32_t, (_edp)->ed_u32[0]); \
478 _NOTE(CONSTANTCONDITION) \
481 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
483 EFX_CHECK_REG((_enp), (_reg)); \
484 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
485 uint32_t, _reg ## _OFST, \
486 uint32_t, (_edp)->ed_u32[0]); \
487 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
489 _NOTE(CONSTANTCONDITION) \
492 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
494 EFX_CHECK_REG((_enp), (_reg)); \
495 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
497 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
498 uint32_t, _reg ## _OFST, \
499 uint32_t, (_eqp)->eq_u32[1], \
500 uint32_t, (_eqp)->eq_u32[0]); \
501 _NOTE(CONSTANTCONDITION) \
504 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
506 EFX_CHECK_REG((_enp), (_reg)); \
507 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
508 uint32_t, _reg ## _OFST, \
509 uint32_t, (_eqp)->eq_u32[1], \
510 uint32_t, (_eqp)->eq_u32[0]); \
511 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
513 _NOTE(CONSTANTCONDITION) \
516 #define EFX_BAR_READO(_enp, _reg, _eop) \
518 EFX_CHECK_REG((_enp), (_reg)); \
519 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
521 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
522 uint32_t, _reg ## _OFST, \
523 uint32_t, (_eop)->eo_u32[3], \
524 uint32_t, (_eop)->eo_u32[2], \
525 uint32_t, (_eop)->eo_u32[1], \
526 uint32_t, (_eop)->eo_u32[0]); \
527 _NOTE(CONSTANTCONDITION) \
530 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
532 EFX_CHECK_REG((_enp), (_reg)); \
533 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
534 uint32_t, _reg ## _OFST, \
535 uint32_t, (_eop)->eo_u32[3], \
536 uint32_t, (_eop)->eo_u32[2], \
537 uint32_t, (_eop)->eo_u32[1], \
538 uint32_t, (_eop)->eo_u32[0]); \
539 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
541 _NOTE(CONSTANTCONDITION) \
544 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
546 EFX_CHECK_REG((_enp), (_reg)); \
547 EFSYS_BAR_READD((_enp)->en_esbp, \
548 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
550 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
551 uint32_t, (_index), \
552 uint32_t, _reg ## _OFST, \
553 uint32_t, (_edp)->ed_u32[0]); \
554 _NOTE(CONSTANTCONDITION) \
557 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
559 EFX_CHECK_REG((_enp), (_reg)); \
560 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
561 uint32_t, (_index), \
562 uint32_t, _reg ## _OFST, \
563 uint32_t, (_edp)->ed_u32[0]); \
564 EFSYS_BAR_WRITED((_enp)->en_esbp, \
565 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
567 _NOTE(CONSTANTCONDITION) \
570 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
572 EFX_CHECK_REG((_enp), (_reg)); \
573 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
574 uint32_t, (_index), \
575 uint32_t, _reg ## _OFST, \
576 uint32_t, (_edp)->ed_u32[0]); \
577 EFSYS_BAR_WRITED((_enp)->en_esbp, \
579 (3 * sizeof (efx_dword_t)) + \
580 ((_index) * _reg ## _STEP)), \
582 _NOTE(CONSTANTCONDITION) \
585 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
587 EFX_CHECK_REG((_enp), (_reg)); \
588 EFSYS_BAR_READQ((_enp)->en_esbp, \
589 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
591 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
592 uint32_t, (_index), \
593 uint32_t, _reg ## _OFST, \
594 uint32_t, (_eqp)->eq_u32[1], \
595 uint32_t, (_eqp)->eq_u32[0]); \
596 _NOTE(CONSTANTCONDITION) \
599 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
601 EFX_CHECK_REG((_enp), (_reg)); \
602 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
603 uint32_t, (_index), \
604 uint32_t, _reg ## _OFST, \
605 uint32_t, (_eqp)->eq_u32[1], \
606 uint32_t, (_eqp)->eq_u32[0]); \
607 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
608 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
610 _NOTE(CONSTANTCONDITION) \
613 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop) \
615 EFX_CHECK_REG((_enp), (_reg)); \
616 EFSYS_BAR_READO((_enp)->en_esbp, \
617 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
619 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
620 uint32_t, (_index), \
621 uint32_t, _reg ## _OFST, \
622 uint32_t, (_eop)->eo_u32[3], \
623 uint32_t, (_eop)->eo_u32[2], \
624 uint32_t, (_eop)->eo_u32[1], \
625 uint32_t, (_eop)->eo_u32[0]); \
626 _NOTE(CONSTANTCONDITION) \
629 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop) \
631 EFX_CHECK_REG((_enp), (_reg)); \
632 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
633 uint32_t, (_index), \
634 uint32_t, _reg ## _OFST, \
635 uint32_t, (_eop)->eo_u32[3], \
636 uint32_t, (_eop)->eo_u32[2], \
637 uint32_t, (_eop)->eo_u32[1], \
638 uint32_t, (_eop)->eo_u32[0]); \
639 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
640 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
642 _NOTE(CONSTANTCONDITION) \
645 extern __checkReturn int
647 __in efx_nic_t *enp);
649 extern __checkReturn int
651 __in efx_nic_t *enp);
655 __in efx_nic_t *enp);
659 /* VPD utility functions */
661 extern __checkReturn int
663 __in_bcount(size) caddr_t data,
665 __out size_t *lengthp);
667 extern __checkReturn int
669 __in_bcount(size) caddr_t data,
671 __out_opt boolean_t *cksummedp);
673 extern __checkReturn int
677 __in boolean_t wantpid);
679 extern __checkReturn int
681 __in_bcount(size) caddr_t data,
683 __in efx_vpd_tag_t tag,
684 __in efx_vpd_keyword_t keyword,
685 __out unsigned int *payloadp,
686 __out uint8_t *paylenp);
688 extern __checkReturn int
690 __in_bcount(size) caddr_t data,
692 __out efx_vpd_tag_t *tagp,
693 __out efx_vpd_keyword_t *keyword,
694 __out_bcount_opt(*paylenp) unsigned int *payloadp,
695 __out_opt uint8_t *paylenp,
696 __inout unsigned int *contp);
698 extern __checkReturn int
700 __in_bcount(size) caddr_t data,
702 __in efx_vpd_value_t *evvp);
704 #endif /* EFSYS_OPT_VPD */
708 extern efx_sram_pattern_fn_t __cs __efx_sram_pattern_fns[];
710 typedef struct efx_register_set_s {
711 unsigned int address;
715 } efx_register_set_t;
717 extern __checkReturn int
718 efx_nic_test_registers(
720 __in efx_register_set_t *rsp,
723 extern __checkReturn int
726 __in efx_register_set_t *rsp,
727 __in efx_pattern_type_t pattern,
730 #endif /* EFSYS_OPT_DIAG */
736 #endif /* _SYS_EFX_IMPL_H */