2 * Copyright (c) 2008 Benno Rice. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
29 * Driver for SMSC LAN91C111, may work for older variants.
32 #ifdef HAVE_KERNEL_OPTION_HEADERS
33 #include "opt_device_polling.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/errno.h>
39 #include <sys/kernel.h>
40 #include <sys/sockio.h>
41 #include <sys/malloc.h>
43 #include <sys/queue.h>
44 #include <sys/socket.h>
45 #include <sys/syslog.h>
46 #include <sys/taskqueue.h>
48 #include <sys/module.h>
51 #include <machine/bus.h>
52 #include <machine/resource.h>
55 #include <net/ethernet.h>
57 #include <net/if_arp.h>
58 #include <net/if_dl.h>
59 #include <net/if_types.h>
60 #include <net/if_mib.h>
61 #include <net/if_media.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/in_var.h>
67 #include <netinet/ip.h>
71 #include <net/bpfdesc.h>
73 #include <dev/smc/if_smcreg.h>
74 #include <dev/smc/if_smcvar.h>
76 #include <dev/mii/mii.h>
77 #include <dev/mii/mii_bitbang.h>
78 #include <dev/mii/miivar.h>
80 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx)
81 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx)
82 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED)
84 #define SMC_INTR_PRIORITY 0
85 #define SMC_RX_PRIORITY 5
86 #define SMC_TX_PRIORITY 10
88 devclass_t smc_devclass;
90 static const char *smc_chip_ids[16] = {
92 /* 3 */ "SMSC LAN91C90 or LAN91C92",
93 /* 4 */ "SMSC LAN91C94",
94 /* 5 */ "SMSC LAN91C95",
95 /* 6 */ "SMSC LAN91C96",
96 /* 7 */ "SMSC LAN91C100",
97 /* 8 */ "SMSC LAN91C100FD",
98 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
103 static void smc_init(void *);
104 static void smc_start(struct ifnet *);
105 static void smc_stop(struct smc_softc *);
106 static int smc_ioctl(struct ifnet *, u_long, caddr_t);
108 static void smc_init_locked(struct smc_softc *);
109 static void smc_start_locked(struct ifnet *);
110 static void smc_reset(struct smc_softc *);
111 static int smc_mii_ifmedia_upd(struct ifnet *);
112 static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *);
113 static void smc_mii_tick(void *);
114 static void smc_mii_mediachg(struct smc_softc *);
115 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
117 static void smc_task_intr(void *, int);
118 static void smc_task_rx(void *, int);
119 static void smc_task_tx(void *, int);
121 static driver_filter_t smc_intr;
122 static timeout_t smc_watchdog;
123 #ifdef DEVICE_POLLING
124 static poll_handler_t smc_poll;
130 static uint32_t smc_mii_bitbang_read(device_t);
131 static void smc_mii_bitbang_write(device_t, uint32_t);
133 static const struct mii_bitbang_ops smc_mii_bitbang_ops = {
134 smc_mii_bitbang_read,
135 smc_mii_bitbang_write,
137 MGMT_MDO, /* MII_BIT_MDO */
138 MGMT_MDI, /* MII_BIT_MDI */
139 MGMT_MCLK, /* MII_BIT_MDC */
140 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */
141 0, /* MII_BIT_DIR_PHY_HOST */
146 smc_select_bank(struct smc_softc *sc, uint16_t bank)
149 bus_barrier(sc->smc_reg, BSR, 2,
150 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
151 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
152 bus_barrier(sc->smc_reg, BSR, 2,
153 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
156 /* Never call this when not in bank 2. */
158 smc_mmu_wait(struct smc_softc *sc)
161 KASSERT((bus_read_2(sc->smc_reg, BSR) &
162 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
163 device_get_nameunit(sc->smc_dev)));
164 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
168 static __inline uint8_t
169 smc_read_1(struct smc_softc *sc, bus_size_t offset)
172 return (bus_read_1(sc->smc_reg, offset));
176 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
179 bus_write_1(sc->smc_reg, offset, val);
182 static __inline uint16_t
183 smc_read_2(struct smc_softc *sc, bus_size_t offset)
186 return (bus_read_2(sc->smc_reg, offset));
190 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
193 bus_write_2(sc->smc_reg, offset, val);
197 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
201 bus_read_multi_2(sc->smc_reg, offset, datap, count);
205 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
209 bus_write_multi_2(sc->smc_reg, offset, datap, count);
213 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length,
217 bus_barrier(sc->smc_reg, offset, length, flags);
221 smc_probe(device_t dev)
223 int rid, type, error;
225 struct smc_softc *sc;
226 struct resource *reg;
228 sc = device_get_softc(dev);
230 type = SYS_RES_IOPORT;
234 type = SYS_RES_MEMORY;
236 reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE);
240 "could not allocate I/O resource for probe\n");
244 /* Check for the identification value in the BSR. */
245 val = bus_read_2(reg, BSR);
246 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
248 device_printf(dev, "identification value not in BSR\n");
254 * Try switching banks and make sure we still get the identification
257 bus_write_2(reg, BSR, 0);
258 val = bus_read_2(reg, BSR);
259 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
262 "identification value not in BSR after write\n");
269 bus_write_2(reg, BSR, 1);
270 val = bus_read_2(reg, BAR);
271 val = BAR_ADDRESS(val);
272 if (rman_get_start(reg) != val) {
274 device_printf(dev, "BAR address %x does not match "
275 "I/O resource address %lx\n", val,
276 rman_get_start(reg));
282 /* Compare REV against known chip revisions. */
283 bus_write_2(reg, BSR, 3);
284 val = bus_read_2(reg, REV);
285 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
286 if (smc_chip_ids[val] == NULL) {
288 device_printf(dev, "Unknown chip revision: %d\n", val);
293 device_set_desc(dev, smc_chip_ids[val]);
296 bus_release_resource(dev, type, rid, reg);
301 smc_attach(device_t dev)
305 u_char eaddr[ETHER_ADDR_LEN];
306 struct smc_softc *sc;
309 sc = device_get_softc(dev);
314 ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
320 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
322 /* Set up watchdog callout. */
323 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0);
325 type = SYS_RES_IOPORT;
327 type = SYS_RES_MEMORY;
330 sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0,
332 if (sc->smc_reg == NULL) {
337 sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0,
338 ~0, 1, RF_ACTIVE | RF_SHAREABLE);
339 if (sc->smc_irq == NULL) {
348 smc_select_bank(sc, 3);
349 val = smc_read_2(sc, REV);
350 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
351 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
353 device_printf(dev, "revision %x\n", sc->smc_rev);
355 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx,
356 CALLOUT_RETURNUNLOCKED);
357 if (sc->smc_chip >= REV_CHIP_91110FD) {
358 (void)mii_attach(dev, &sc->smc_miibus, ifp,
359 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK,
360 MII_PHY_ANY, MII_OFFSET_ANY, 0);
361 if (sc->smc_miibus != NULL) {
362 sc->smc_mii_tick = smc_mii_tick;
363 sc->smc_mii_mediachg = smc_mii_mediachg;
364 sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
368 smc_select_bank(sc, 1);
369 eaddr[0] = smc_read_1(sc, IAR0);
370 eaddr[1] = smc_read_1(sc, IAR1);
371 eaddr[2] = smc_read_1(sc, IAR2);
372 eaddr[3] = smc_read_1(sc, IAR3);
373 eaddr[4] = smc_read_1(sc, IAR4);
374 eaddr[5] = smc_read_1(sc, IAR5);
376 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
378 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
379 ifp->if_init = smc_init;
380 ifp->if_ioctl = smc_ioctl;
381 ifp->if_start = smc_start;
382 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
383 IFQ_SET_READY(&ifp->if_snd);
385 ifp->if_capabilities = ifp->if_capenable = 0;
387 #ifdef DEVICE_POLLING
388 ifp->if_capabilities |= IFCAP_POLLING;
391 ether_ifattach(ifp, eaddr);
393 /* Set up taskqueue */
394 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
395 TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
396 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
397 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
398 taskqueue_thread_enqueue, &sc->smc_tq);
399 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
400 device_get_nameunit(sc->smc_dev));
402 /* Mask all interrupts. */
404 smc_write_1(sc, MSK, 0);
406 /* Wire up interrupt */
407 error = bus_setup_intr(dev, sc->smc_irq,
408 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
419 smc_detach(device_t dev)
422 struct smc_softc *sc;
424 sc = device_get_softc(dev);
429 if (sc->smc_ifp != NULL) {
430 ether_ifdetach(sc->smc_ifp);
433 callout_drain(&sc->smc_watchdog);
434 callout_drain(&sc->smc_mii_tick_ch);
436 #ifdef DEVICE_POLLING
437 if (sc->smc_ifp->if_capenable & IFCAP_POLLING)
438 ether_poll_deregister(sc->smc_ifp);
441 if (sc->smc_ih != NULL)
442 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
444 if (sc->smc_tq != NULL) {
445 taskqueue_drain(sc->smc_tq, &sc->smc_intr);
446 taskqueue_drain(sc->smc_tq, &sc->smc_rx);
447 taskqueue_drain(sc->smc_tq, &sc->smc_tx);
448 taskqueue_free(sc->smc_tq);
452 if (sc->smc_ifp != NULL) {
453 if_free(sc->smc_ifp);
456 if (sc->smc_miibus != NULL) {
457 device_delete_child(sc->smc_dev, sc->smc_miibus);
458 bus_generic_detach(sc->smc_dev);
461 if (sc->smc_reg != NULL) {
462 type = SYS_RES_IOPORT;
464 type = SYS_RES_MEMORY;
466 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
470 if (sc->smc_irq != NULL)
471 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
474 if (mtx_initialized(&sc->smc_mtx))
475 mtx_destroy(&sc->smc_mtx);
481 smc_start(struct ifnet *ifp)
483 struct smc_softc *sc;
487 smc_start_locked(ifp);
492 smc_start_locked(struct ifnet *ifp)
494 struct smc_softc *sc;
496 u_int len, npages, spin_count;
499 SMC_ASSERT_LOCKED(sc);
501 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
503 if (IFQ_IS_EMPTY(&ifp->if_snd))
507 * Grab the next packet. If it's too big, drop it.
509 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
510 len = m_length(m, NULL);
512 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
513 if_printf(ifp, "large packet discarded\n");
516 return; /* XXX readcheck? */
520 * Flag that we're busy.
522 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
526 * Work out how many 256 byte "pages" we need. We have to include the
527 * control data for the packet in this calculation.
529 npages = (len * PKT_CTRL_DATA_LEN) >> 8;
536 smc_select_bank(sc, 2);
538 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
541 * Spin briefly to see if the allocation succeeds.
543 spin_count = TX_ALLOC_WAIT_TIME;
545 if (smc_read_1(sc, IST) & ALLOC_INT) {
546 smc_write_1(sc, ACK, ALLOC_INT);
549 } while (--spin_count);
552 * If the allocation is taking too long, unmask the alloc interrupt
555 if (spin_count == 0) {
556 sc->smc_mask |= ALLOC_INT;
557 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
558 smc_write_1(sc, MSK, sc->smc_mask);
562 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
566 smc_task_tx(void *context, int pending)
569 struct smc_softc *sc;
576 ifp = (struct ifnet *)context;
581 if (sc->smc_pending == NULL) {
586 m = m0 = sc->smc_pending;
587 sc->smc_pending = NULL;
588 smc_select_bank(sc, 2);
591 * Check the allocation result.
593 packet = smc_read_1(sc, ARR);
596 * If the allocation failed, requeue the packet and retry.
598 if (packet & ARR_FAILED) {
599 IFQ_DRV_PREPEND(&ifp->if_snd, m);
601 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
602 smc_start_locked(ifp);
608 * Tell the device to write to our packet number.
610 smc_write_1(sc, PNR, packet);
611 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
614 * Tell the device how long the packet is (including control data).
616 len = m_length(m, 0);
617 len += PKT_CTRL_DATA_LEN;
618 smc_write_2(sc, DATA0, 0);
619 smc_write_2(sc, DATA0, len);
622 * Push the data out to the device.
626 for (; m != NULL; m = m->m_next) {
627 data = mtod(m, uint8_t *);
628 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
633 * Push out the control byte and and the odd byte if needed.
635 if ((len & 1) != 0 && data != NULL)
636 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]);
638 smc_write_2(sc, DATA0, 0);
641 * Unmask the TX empty interrupt.
643 sc->smc_mask |= TX_EMPTY_INT;
644 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
645 smc_write_1(sc, MSK, sc->smc_mask);
648 * Enqueue the packet.
651 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
652 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
658 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
665 * See if there's anything else to do.
671 smc_task_rx(void *context, int pending)
673 u_int packet, status, len;
676 struct smc_softc *sc;
677 struct mbuf *m, *mhead, *mtail;
680 ifp = (struct ifnet *)context;
682 mhead = mtail = NULL;
686 packet = smc_read_1(sc, FIFO_RX);
687 while ((packet & FIFO_EMPTY) == 0) {
689 * Grab an mbuf and attach a cluster.
691 MGETHDR(m, M_NOWAIT, MT_DATA);
696 if ((m->m_flags & M_EXT) == 0) {
702 * Point to the start of the packet.
704 smc_select_bank(sc, 2);
705 smc_write_1(sc, PNR, packet);
706 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
709 * Grab status and packet length.
711 status = smc_read_2(sc, DATA0);
712 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
714 if (status & RX_ODDFRM)
720 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
722 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
729 * Set the mbuf up the way we want it.
731 m->m_pkthdr.rcvif = ifp;
732 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
733 m_adj(m, ETHER_ALIGN);
736 * Pull the packet out of the device. Make sure we're in the
737 * right bank first as things may have changed while we were
738 * allocating our mbuf.
740 smc_select_bank(sc, 2);
741 smc_write_1(sc, PNR, packet);
742 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
743 data = mtod(m, uint8_t *);
744 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
747 *data = smc_read_1(sc, DATA0);
751 * Tell the device we're done.
754 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
766 packet = smc_read_1(sc, FIFO_RX);
769 sc->smc_mask |= RCV_INT;
770 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
771 smc_write_1(sc, MSK, sc->smc_mask);
775 while (mhead != NULL) {
777 mhead = mhead->m_next;
780 (*ifp->if_input)(ifp, m);
784 #ifdef DEVICE_POLLING
786 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
788 struct smc_softc *sc;
793 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
799 if (cmd == POLL_AND_CHECK_STATUS)
800 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
805 smc_intr(void *context)
807 struct smc_softc *sc;
809 sc = (struct smc_softc *)context;
810 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
811 return (FILTER_HANDLED);
815 smc_task_intr(void *context, int pending)
817 struct smc_softc *sc;
819 u_int status, packet, counter, tcr;
822 ifp = (struct ifnet *)context;
827 smc_select_bank(sc, 2);
830 * Get the current mask, and then block all interrupts while we're
833 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
834 smc_write_1(sc, MSK, 0);
837 * Find out what interrupts are flagged.
839 status = smc_read_1(sc, IST) & sc->smc_mask;
844 if (status & TX_INT) {
846 * Kill off the packet if there is one and re-enable transmit.
848 packet = smc_read_1(sc, FIFO_TX);
849 if ((packet & FIFO_EMPTY) == 0) {
850 smc_write_1(sc, PNR, packet);
851 smc_write_2(sc, PTR, 0 | PTR_READ |
853 tcr = smc_read_2(sc, DATA0);
854 if ((tcr & EPHSR_TX_SUC) == 0)
855 device_printf(sc->smc_dev,
858 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
860 smc_select_bank(sc, 0);
861 tcr = smc_read_2(sc, TCR);
862 tcr |= TCR_TXENA | TCR_PAD_EN;
863 smc_write_2(sc, TCR, tcr);
864 smc_select_bank(sc, 2);
865 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
871 smc_write_1(sc, ACK, TX_INT);
877 if (status & RCV_INT) {
878 smc_write_1(sc, ACK, RCV_INT);
879 sc->smc_mask &= ~RCV_INT;
880 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx);
886 if (status & ALLOC_INT) {
887 smc_write_1(sc, ACK, ALLOC_INT);
888 sc->smc_mask &= ~ALLOC_INT;
889 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
895 if (status & RX_OVRN_INT) {
896 smc_write_1(sc, ACK, RX_OVRN_INT);
903 if (status & TX_EMPTY_INT) {
904 smc_write_1(sc, ACK, TX_EMPTY_INT);
905 sc->smc_mask &= ~TX_EMPTY_INT;
906 callout_stop(&sc->smc_watchdog);
909 * Update collision stats.
911 smc_select_bank(sc, 0);
912 counter = smc_read_2(sc, ECR);
913 smc_select_bank(sc, 2);
914 ifp->if_collisions +=
915 (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT;
916 ifp->if_collisions +=
917 (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT;
920 * See if there are any packets to transmit.
922 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
926 * Update the interrupt mask.
928 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
929 smc_write_1(sc, MSK, sc->smc_mask);
935 smc_mii_bitbang_read(device_t dev)
937 struct smc_softc *sc;
940 sc = device_get_softc(dev);
942 SMC_ASSERT_LOCKED(sc);
943 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
944 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)",
945 device_get_nameunit(sc->smc_dev),
946 smc_read_2(sc, BSR) & BSR_BANK_MASK));
948 val = smc_read_2(sc, MGMT);
949 smc_barrier(sc, MGMT, 2,
950 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
956 smc_mii_bitbang_write(device_t dev, uint32_t val)
958 struct smc_softc *sc;
960 sc = device_get_softc(dev);
962 SMC_ASSERT_LOCKED(sc);
963 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
964 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)",
965 device_get_nameunit(sc->smc_dev),
966 smc_read_2(sc, BSR) & BSR_BANK_MASK));
968 smc_write_2(sc, MGMT, val);
969 smc_barrier(sc, MGMT, 2,
970 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
974 smc_miibus_readreg(device_t dev, int phy, int reg)
976 struct smc_softc *sc;
979 sc = device_get_softc(dev);
983 smc_select_bank(sc, 3);
985 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
992 smc_miibus_writereg(device_t dev, int phy, int reg, int data)
994 struct smc_softc *sc;
996 sc = device_get_softc(dev);
1000 smc_select_bank(sc, 3);
1002 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);
1009 smc_miibus_statchg(device_t dev)
1011 struct smc_softc *sc;
1012 struct mii_data *mii;
1015 sc = device_get_softc(dev);
1016 mii = device_get_softc(sc->smc_miibus);
1020 smc_select_bank(sc, 0);
1021 tcr = smc_read_2(sc, TCR);
1023 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1028 smc_write_2(sc, TCR, tcr);
1034 smc_mii_ifmedia_upd(struct ifnet *ifp)
1036 struct smc_softc *sc;
1037 struct mii_data *mii;
1040 if (sc->smc_miibus == NULL)
1043 mii = device_get_softc(sc->smc_miibus);
1044 return (mii_mediachg(mii));
1048 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1050 struct smc_softc *sc;
1051 struct mii_data *mii;
1054 if (sc->smc_miibus == NULL)
1057 mii = device_get_softc(sc->smc_miibus);
1059 ifmr->ifm_active = mii->mii_media_active;
1060 ifmr->ifm_status = mii->mii_media_status;
1064 smc_mii_tick(void *context)
1066 struct smc_softc *sc;
1068 sc = (struct smc_softc *)context;
1070 if (sc->smc_miibus == NULL)
1075 mii_tick(device_get_softc(sc->smc_miibus));
1076 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1080 smc_mii_mediachg(struct smc_softc *sc)
1083 if (sc->smc_miibus == NULL)
1085 mii_mediachg(device_get_softc(sc->smc_miibus));
1089 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1091 struct mii_data *mii;
1093 if (sc->smc_miibus == NULL)
1096 mii = device_get_softc(sc->smc_miibus);
1097 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1101 smc_reset(struct smc_softc *sc)
1105 SMC_ASSERT_LOCKED(sc);
1107 smc_select_bank(sc, 2);
1110 * Mask all interrupts.
1112 smc_write_1(sc, MSK, 0);
1115 * Tell the device to reset.
1117 smc_select_bank(sc, 0);
1118 smc_write_2(sc, RCR, RCR_SOFT_RST);
1121 * Set up the configuration register.
1123 smc_select_bank(sc, 1);
1124 smc_write_2(sc, CR, CR_EPH_POWER_EN);
1128 * Turn off transmit and receive.
1130 smc_select_bank(sc, 0);
1131 smc_write_2(sc, TCR, 0);
1132 smc_write_2(sc, RCR, 0);
1135 * Set up the control register.
1137 smc_select_bank(sc, 1);
1138 ctr = smc_read_2(sc, CTR);
1139 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
1140 smc_write_2(sc, CTR, ctr);
1145 smc_select_bank(sc, 2);
1147 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1151 smc_enable(struct smc_softc *sc)
1155 SMC_ASSERT_LOCKED(sc);
1159 * Set up the receive/PHY control register.
1161 smc_select_bank(sc, 0);
1162 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1163 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1166 * Set up the transmit and receive control registers.
1168 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1169 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1172 * Set up the interrupt mask.
1174 smc_select_bank(sc, 2);
1175 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1176 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1177 smc_write_1(sc, MSK, sc->smc_mask);
1181 smc_stop(struct smc_softc *sc)
1184 SMC_ASSERT_LOCKED(sc);
1187 * Turn off callouts.
1189 callout_stop(&sc->smc_watchdog);
1190 callout_stop(&sc->smc_mii_tick_ch);
1193 * Mask all interrupts.
1195 smc_select_bank(sc, 2);
1197 smc_write_1(sc, MSK, 0);
1198 #ifdef DEVICE_POLLING
1199 ether_poll_deregister(sc->smc_ifp);
1200 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING;
1201 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT;
1205 * Disable transmit and receive.
1207 smc_select_bank(sc, 0);
1208 smc_write_2(sc, TCR, 0);
1209 smc_write_2(sc, RCR, 0);
1211 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1215 smc_watchdog(void *arg)
1217 struct smc_softc *sc;
1219 sc = (struct smc_softc *)arg;
1220 device_printf(sc->smc_dev, "watchdog timeout\n");
1221 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr);
1225 smc_init(void *context)
1227 struct smc_softc *sc;
1229 sc = (struct smc_softc *)context;
1231 smc_init_locked(sc);
1236 smc_init_locked(struct smc_softc *sc)
1242 SMC_ASSERT_LOCKED(sc);
1247 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1248 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1250 smc_start_locked(ifp);
1252 if (sc->smc_mii_tick != NULL)
1253 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1255 #ifdef DEVICE_POLLING
1257 ether_poll_register(smc_poll, ifp);
1259 ifp->if_capenable |= IFCAP_POLLING;
1260 ifp->if_capenable |= IFCAP_POLLING_NOCOUNT;
1265 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1267 struct smc_softc *sc;
1275 if ((ifp->if_flags & IFF_UP) == 0 &&
1276 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1282 if (sc->smc_mii_mediachg != NULL)
1283 sc->smc_mii_mediachg(sc);
1299 if (sc->smc_mii_mediaioctl == NULL) {
1303 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1307 error = ether_ioctl(ifp, cmd, data);