1 /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
4 * Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
33 * 1. Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * 2. Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in the
37 * documentation and/or other materials provided with the distribution.
38 * 3. All advertising materials mentioning features or use of this software
39 * must display the following acknowledgement:
40 * This product includes software developed by Per Fogelstrom.
41 * 4. The name of the author may not be used to endorse or promote products
42 * derived from this software without specific prior written permission
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
59 #ifndef _MACHINE_CPUFUNC_H_
60 #define _MACHINE_CPUFUNC_H_
62 #include <sys/types.h>
63 #include <machine/cpuregs.h>
66 * These functions are required by user-land atomi ops
73 __asm __volatile("" : : : "memory");
75 __asm __volatile (".set noreorder\n\t"
92 __asm __volatile (__XSTRING(COP0_SYNC));
98 #if defined(CPU_CNMIPS)
99 __asm __volatile (".set noreorder\n\t"
104 __asm __volatile ("sync" : : : "memory");
110 mips_read_membar(void)
116 mips_write_membar(void)
124 * It would be nice to add variants that read/write register_t, to avoid some
127 #if defined(__mips_n32) || defined(__mips_n64)
128 #define MIPS_RW64_COP0(n,r) \
129 static __inline uint64_t \
130 mips_rd_ ## n (void) \
133 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
138 static __inline void \
139 mips_wr_ ## n (uint64_t a0) \
141 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
142 __XSTRING(COP0_SYNC)";" \
150 #define MIPS_RW64_COP0_SEL(n,r,s) \
151 static __inline uint64_t \
152 mips_rd_ ## n(void) \
155 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
160 static __inline void \
161 mips_wr_ ## n(uint64_t a0) \
163 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
164 __XSTRING(COP0_SYNC)";" \
170 #if defined(__mips_n64)
171 MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC);
172 MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
173 MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
175 MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6);
176 MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7);
177 MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7);
178 MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0);
179 MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1);
182 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
183 MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
184 MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
186 MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
188 #undef MIPS_RW64_COP0
189 #undef MIPS_RW64_COP0_SEL
192 #define MIPS_RW32_COP0(n,r) \
193 static __inline uint32_t \
194 mips_rd_ ## n (void) \
197 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
202 static __inline void \
203 mips_wr_ ## n (uint32_t a0) \
205 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
206 __XSTRING(COP0_SYNC)";" \
214 #define MIPS_RW32_COP0_SEL(n,r,s) \
215 static __inline uint32_t \
216 mips_rd_ ## n(void) \
219 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
224 static __inline void \
225 mips_wr_ ## n(uint32_t a0) \
227 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
228 __XSTRING(COP0_SYNC)";" \
237 static __inline void mips_sync_icache (void)
242 ".word 0x041f0000\n" /* xxx ICACHE */
249 MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE);
250 MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG);
251 MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
252 MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
253 MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
255 MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
258 MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
259 MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
261 MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
262 MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX);
263 MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
264 MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
265 #if !defined(__mips_n64)
266 MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
268 MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
270 /* XXX: Some of these registers are specific to MIPS32. */
271 #if !defined(__mips_n64)
272 MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
273 MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
275 #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
276 MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
277 MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
279 MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
281 MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
282 MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
283 MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
284 MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
285 MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
286 MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
287 MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
288 MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
289 MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
291 MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
292 MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
293 MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
294 MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
296 #undef MIPS_RW32_COP0
297 #undef MIPS_RW32_COP0_SEL
299 static __inline register_t
304 s = mips_rd_status();
305 mips_wr_status(s & ~MIPS_SR_INT_IE);
307 return (s & MIPS_SR_INT_IE);
310 static __inline register_t
315 s = mips_rd_status();
316 mips_wr_status(s | MIPS_SR_INT_IE);
322 intr_restore(register_t ie)
324 if (ie == MIPS_SR_INT_IE) {
329 static __inline uint32_t
330 set_intr_mask(uint32_t mask)
334 ostatus = mips_rd_status();
335 mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
336 mips_wr_status(mask);
340 static __inline uint32_t
344 return (mips_rd_status() & MIPS_SR_INT_MASK);
350 __asm __volatile ("break");
353 #if defined(__GNUC__) && !defined(__mips_o32)
354 static inline uint64_t
355 mips3_ld(const volatile uint64_t *va)
362 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va));
369 mips3_sd(volatile uint64_t *va, uint64_t v)
374 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va));
378 uint64_t mips3_ld(volatile uint64_t *va);
379 void mips3_sd(volatile uint64_t *, uint64_t);
380 #endif /* __GNUC__ */
384 #define readb(va) (*(volatile uint8_t *) (va))
385 #define readw(va) (*(volatile uint16_t *) (va))
386 #define readl(va) (*(volatile uint32_t *) (va))
388 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
389 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
390 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
396 #define outb(a,v) (*(volatile unsigned char*)(a) = (v))
397 #define out8(a,v) (*(volatile unsigned char*)(a) = (v))
398 #define outw(a,v) (*(volatile unsigned short*)(a) = (v))
399 #define out16(a,v) outw(a,v)
400 #define outl(a,v) (*(volatile unsigned int*)(a) = (v))
401 #define out32(a,v) outl(a,v)
402 #define inb(a) (*(volatile unsigned char*)(a))
403 #define in8(a) (*(volatile unsigned char*)(a))
404 #define inw(a) (*(volatile unsigned short*)(a))
405 #define in16(a) inw(a)
406 #define inl(a) (*(volatile unsigned int*)(a))
407 #define in32(a) inl(a)
409 #define out8rb(a,v) (*(volatile unsigned char*)(a) = (v))
410 #define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v))
411 #define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v))
412 #define in8rb(a) (*(volatile unsigned char*)(a))
413 #define in16rb(a) (__in16rb((volatile uint16_t *)(a)))
414 #define in32rb(a) (__in32rb((volatile uint32_t *)(a)))
416 #define _swap_(x) (((x) >> 24) | ((x) << 24) | \
417 (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8))
419 static __inline void __out32rb(volatile uint32_t *, uint32_t);
420 static __inline void __out16rb(volatile uint16_t *, uint16_t);
421 static __inline uint32_t __in32rb(volatile uint32_t *);
422 static __inline uint16_t __in16rb(volatile uint16_t *);
425 __out32rb(volatile uint32_t *a, uint32_t v)
434 __out16rb(volatile uint16_t *a, uint16_t v)
438 _v_ = ((v >> 8) & 0xff) | (v << 8);
442 static __inline uint32_t
443 __in32rb(volatile uint32_t *a)
452 static __inline uint16_t
453 __in16rb(volatile uint16_t *a)
458 _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8);
462 void insb(uint8_t *, uint8_t *,int);
463 void insw(uint16_t *, uint16_t *,int);
464 void insl(uint32_t *, uint32_t *,int);
465 void outsb(uint8_t *, const uint8_t *,int);
466 void outsw(uint16_t *, const uint16_t *,int);
467 void outsl(uint32_t *, const uint32_t *,int);
468 u_int loadandclear(volatile u_int *addr);
470 #endif /* !_MACHINE_CPUFUNC_H_ */